DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed January 21st, 2026 have been fully considered but they are not persuasive. Claims 21-23 are new. Claims 1, 3-5, 7-16, and 20 are amended. Claims 17-19 are canceled. Claims 1-16, 20-23 are pending and presented for examination.
Applicant’s arguments, see page 8-10, filed 01/21/2026, with respect to the rejection(s) of claim(s) 1, 2, 5, 8, 9, 11, 12, 20, 23 under U.S.C. 101 have been fully considered and is not fully persuasive.
Regarding claims 1, 2, 5, 8, 9, 11, 12, 20, 23, as they currently stand, they allow a user to use a general-purpose computing device, which typically includes an OS, to make a decision about selection and scheduling. Scheduling is not execution, and therefore does not constitute and execution step to make this a practical application. Thus, the rejection under U.S.C 101 remains.
Applicant’s arguments, see page 10-14, filed 01/21/2026, with respect to the rejection(s) of claim(s) 1, 2-10, 11 and 20, and 12-16 under US 20200026569 A1 (Bahramshahry et. al), and further in view of US 20250094307 A1 (Lebdeh et. al), have been fully considered and are not persuasive.
Regarding claim 1, 11, and 20, applicant claims Bahramshahry and further in view of Lebdeh fails to disclose: "storage configured to store a margin table that maintains margin information for a plurality of hardware components of the system, the margin information describing, for each of the plurality of hardware components, a margin for operating without errors, and one or more processors operable to implement an operating system which includes a scheduler to: receive a request to perform one or more tasks, select a hardware component of the plurality of hardware components based on the margin information and the one or more tasks, and schedule performance of the one or more tasks using the selected hardware component.". Lebdeh teaches a storage on a system that stores a margin table, that margin table stores information about the hardware components of the system, (paragraph 34, 36, 43, 45, 61, 100). In combination with Bahramshahry, information is passed into a system with a scheduler, which schedules performance of tasks on a component (paragraph 83, 105, 238, 128, 184). Therefore, based on the teachings provided by the reference the argument is not persuasive.
Applicant’s arguments, see page 10-14, filed 01/21/2026, with respect to the rejection(s) of claim(s) 5, 8, 15 under US 20200026569 A1 (Bahramshahry et. al), and further in view of US 20250094307 A1 (Lebdeh et. al) and further view of Applicant Admitted Prior Art, have been fully considered and are not persuasive. Regarding the argument that the combination is not well known in the art, and such the combination of references would not lead a person of ordinary skill in the art to the claimed invention. “Safe Overclocking for CNN Accelerators Through Algorithm-Level Error Detection” teaches the use of overclocked processors and hardware accelerators and minimizing errors, (see page 1, column 1, Introduction, page 12, column 2, D. Other Techniques for Timing Error Detection). This can be selected by the margin table to allow for achieving faster operating speeds for tasks with low error. Therefore, based on the teachings provided by the reference the argument is not persuasive.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1, 2, 5, 8, 9, 11, 12, and 20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to (an) abstract idea(s) without significantly more.
As to claim 1, A system comprising: storage configured to store a margin table that maintains margin information for a plurality of hardware components of the system, the margin information describing, for each of the plurality of hardware components, a margin for operating without errors; and one or more processors operable to implement an operating system which includes a scheduler configured to: receive a request to perform one or more tasks; select a hardware component of the plurality of hardware components based on the margin information and the one or more tasks; and schedule performance of the one or more tasks using the selected hardware component.
The system of claim 1, which recites the limitations of “s select a hardware component of the plurality of hardware components based on the margin information and the one or more tasks” as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the function through observation, evaluation, judgment and/or opinion, or even with the aid of pen and paper; for a human making a mental determination regarding the performance of a workflow and based on an intelligent decision predicting / assigning additional resources accordingly. Thus, this limitation recites and falls within the “Mental Processes” grouping of abstract ideas under Prong 1.
Under Prong 2, this judicial exception is not integrated into a practical application. The additional element “a margin table that maintains margin information for a plurality of hardware components of the system, the margin information describing, for each of the plurality of hardware components, a margin for operating without errors; and one or more processors operable to implement an operating system” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using generic computers, and/or mere computer components, MPEP 2106.05(f), or does nothing more than add insignificant extra solution activity to the judicial exception of data gathering. Accordingly, the additional elements do not integrate the recited judicial exception into a practical application and the claim is therefore directed to the judicial exception. See MPEP 2106.05(g).
Under Prong 2B, the claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of element “a margin table that maintains margin information for a plurality of hardware components of the system, the margin information describing, for each of the plurality of hardware components, a margin for operating without errors; and one or more processors operable to implement an operating system” amount to no more than mere instructions / data gathering using generic computer/computer components to carry out the exception, further, mere data gathering has been recognized by the courts as being well understood, routine, and conventional, See MPEP 2106.05(d) and (f). The recitation of generic computer instruction and computer components to apply the judicial exception, and mere data gathering do not amount to significantly more, thus, cannot provide an inventive concept. Accordingly, the claims are not patent eligible under 35 USC 101.
As to claim 2, The system of claim 1, wherein the scheduler is further configured to classify the one or more tasks as being associated with accuracy or performance.
The system of claim 2, which recites the abstract idea of “wherein the scheduler is further configured to classify the one or more tasks”. This amounts to no more than mere instructions, or generic computer/computer components to carry out the exception, See MPEP 2106.05(f). The recitation of generic computer instruction and computer components to apply the judicial exception, and mere data gathering do not amount to significantly more, thus, cannot provide an inventive concept. The additional element itself or in combination with the elements of parent claims would not amount to a practical application of the abstract idea or amount to significantly more than such. See MPEP 2106.05(d); 2106.05(f) for prong 2 analysis and 2106.05(d) for 2B analysis.
As to claim 5, The system of claim 4, wherein the hardware component with the low margin for operating without errors comprises an overclocked component.
The system of claim 5, which recites the additional element “the hardware component for operating without errors comprises an overclocked component”. This amounts to no more than mere instructions, or generic computer/computer components to carry out the exception, See MPEP 2106.05(f). The recitation of generic computer instruction and computer components to apply the judicial exception, and mere data gathering do not amount to significantly more, thus, cannot provide an inventive concept. The additional element itself or in combination with the elements of parent claims would not amount to a practical application of the abstract idea or amount to significantly more than such. See MPEP 2106.05(d); 2106.05(f) for prong 2 analysis and 2106.05(d) for 2B analysis.
As to claim 8, The system of claim 1, wherein the plurality of hardware components comprises a plurality of processing cores, wherein the plurality of processing cores includes at least one overclocked processing core.
The system of claim 8, which recites the additional elements of “wherein the plurality of hardware components comprises a plurality of processing cores”, and “wherein the plurality of processing cores includes at least one overclocked processing core” - amount to no more than mere instructions, or generic computer/computer components to carry out the exception, See MPEP 2106.05(f). The recitation of generic computer instruction and computer components to apply the judicial exception. The additional element itself or in combination with the elements of parent claims would not amount to a practical application of the abstract idea or amount to significantly more than such. See MPEP 2106.05(g); 2106.05(f) for prong 2 analysis and 2106.05(d) for 2B analysis as the limitation in conjunction with the parent claims do not amount to a practical application of the abstract idea or amount to significantly more.
As to claim 9, The system of claim 1, wherein the selected hardware component comprises at least one of a graphics processing unit (GPU) or a memory.
The system of claim 9, which recites the additional element of “selected hardware component comprises at least one of a graphics processing unit (GPU) or a memory”. Amount to no more than mere instructions, or generic computer/computer components to carry out the exception, See MPEP 2106.05(f). The recitation of generic computer instruction and computer components to apply the judicial exception. The additional element itself or in combination with the elements of parent claims would not amount to a practical application of the abstract idea or amount to significantly more than such. See MPEP 2106.05(g); 2106.05(f) for prong 2 analysis and 2106.05(d) for 2B analysis as the limitation in conjunction with the parent claims do not amount to a practical application of the abstract idea or amount to significantly more.
With regards to the system of Claim 11, Claim 11 teaches the same abstract idea of Claim 1, thus it is rejected under U.S.C. 101 with the same rationale as applied to Claim 1 above.
With regards to the system of Claim 12, Claim 12 teaches the same abstract idea of Claim 2, thus it is rejected under U.S.C. 101 with the same rationale as applied to Claim 2 above.
With regards to the medium of Claim 20, Claim 20 teaches the same abstract idea of Claim 20, thus it is rejected under U.S.C. 101 with the same rationale as applied to Claim 1 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 - 4, 6, 7, 9 – 14, 16, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20200026569 A1 (Bahramshahry et. al), and further in view of US 20250094307 A1 (Lebdeh et. al).
Regarding claim 1, Bahramshahry teaches A system comprising: one or more processors operable to implement an operating system which includes a scheduler to: receive a request to perform one or more tasks; select a component of the plurality of components based on margin information and the one or more tasks; and schedule performance of the one or more tasks using the selected component (paragraph 83, 105, 238, 128, 184, a scheduler that receives a request according a QoS requirement, and based off that requirement, schedule performance on components, figure 1A, paragraphs 70, 73, 268, 304, the host runs a computing environment, which includes an operating system).
However, Bahramshahry fails to teach storage configured to store a margin table that maintains margin information for a plurality of components of the system, the margin information describing, for each of the plurality of components, a margin for operating without errors.
Lebdeh teaches a system comprising: scheduling considerations associated with a margin table that maintains margin information for a plurality of components of the system, the margin information describing, for each of the plurality of components, a margin for operating without errors (paragraph 34, 36, 43, 45, 61, 100 a table of performance for each component, that stores the working range for each component).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the scheduling considerations of Lebdeh to the margin table of Bahramshahry, as it allows for selecting components that minimize errors for each component.
Regarding claim 2, Bahramshahry teaches, the system of claim 1, wherein the scheduler is further configured to classify the one or more tasks as being associated with accuracy or performance (paragraph 105, 238, 315, the workload can have different task types and selecting specific performances requirements, allowing it to minimize accuracy or performance).
Further, Lebdeh teaches wherein the scheduler is further configured to classify the one or more tasks as being associated with accuracy or performance (paragraph 34, 36, 69, according to requirements, the task can have performance or accuracy considerations).
See claim 1 for rationale to combine.
Regarding claim 3, Bahramshahry teaches, the system of claim 2, wherein the scheduler selects a hardware component with a high margin for operating without errors if the one or more tasks classified as being associated with accuracy (paragraph 104, 114, 164, 570, choosing a component according to its error rate, where the task has been decided to be ran with accuracy).
Further, Lebdeh teaches wherein the scheduler is further configured to classify the one or more tasks as being associated with accuracy or performance (paragraph 34, 36, 69, according to requirements, the task can have performance or accuracy considerations according to optimization objectives, paragraph 41).
See claim 1 for rationale to combine.
Regarding claim 4, Bahramshahry teaches, the system of claim 2, wherein the scheduler selects a hardware component with a low margin for operating without errors if the one or more tasks are classified as being associated with performance (from a cloud of components, paragraph 104, 114, 164, 570, 534, 644, 645, choosing components to minimize errors, where the task has been decided to be ran with performance).
Further, Lebdeh teaches wherein the scheduler is further configured to classify the one or more tasks as being associated with accuracy or performance (paragraph 34, 36, 69, according to requirements, the task can have performance or accuracy considerations, according to optimization objectives, paragraph 41).
See claim 1 for rationale to combine.
Regarding claim 6, Bahramshahry teaches, the system of claim 1, wherein the scheduler is configured to classify the one or more tasks as being associated with accuracy or performance based on a type of the one or more tasks paragraph 105, 238, 315, the workload can have different task types and selecting specific performances requirements, allowing it to minimize accuracy or performance).
Further, Lebdeh teaches wherein the scheduler is further configured to classify the one or more tasks as being associated with accuracy or performance (paragraph 34, 36, 69, according to requirements, the task can have performance or accuracy considerations, according to optimization objectives, paragraph 41).
See claim 1 for rationale to combine.
Regarding claim 7, Bahramshahry teaches, The system of claim 1.
However, Bahramshahry fails to teach, wherein the scheduler is further configured to initiate a test of the selected hardware prior to selecting the hardware component to ensure that the margin of the selected component in the margin table is accurate.
Lebdeh teaches, wherein the scheduler is further configured to initiate a test of the selected component prior to selecting the component to ensure that the margin of the selected component in the margin table is accurate (paragraph 31, dynamically updating the margins of specific components for variations in performance).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the scheduling considerations of Lebdeh to the margin table of Bahramshahry, as it allows for selecting components that minimize errors for each component.
Regarding claim 9, Bahramshahry teaches, the system of claim 1, wherein the selected hardware component comprises at least one of a graphics processing unit (GPU) or a memory (paragraph 571, 642 , the optimizations are done for a GPU or memory).
Regarding claim 10, Lebdeh teaches, The system of claim 1, further comprising a controller to dynamically adjust a margin of a particular hardware component of the plurality of hardware components to perform at least one task using the particular hardware component with the dynamically adjusted margin (paragraph 49, 69, 77, 96, 102, 103, performance measurements in profiles, used to determine ranges for optimal use of that component, which can be adjusted to mirror the actual performance of the component).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the scheduling considerations of Lebdeh to the margin table of Bahramshahry, as it allows for selecting components that minimize errors for each component.
With regards to Claim 11, Bahramshahry teaches the medium of Claim 1 as referenced above. The method of Claim 11 performs the same steps as the medium of Claim 1, and Claim 11 is therefore rejected using the same art and rationale set forth above in the rejection of Claim 1 by the teachings of Bahramshahry.
With regards to Claim 12, Bahramshahry teaches the medium of Claim 2 as referenced above. The method of Claim 12 performs the same steps as the medium of Claim 2, and Claim 12 is therefore rejected using the same art and rationale set forth above in the rejection of Claim 2 by the teachings of Bahramshahry.
With regards to Claim 13, Bahramshahry teaches the medium of Claim 3 as referenced above. The method of Claim 13 performs the same steps as the medium of Claim 3, and Claim 13 is therefore rejected using the same art and rationale set forth above in the rejection of Claim 3 by the teachings of Bahramshahry.
With regards to Claim 14, Bahramshahry teaches the medium of Claim 4 as referenced above. The method of Claim 14 performs the same steps as the medium of Claim 4, and Claim 14 is therefore rejected using the same art and rationale set forth above in the rejection of Claim 4 by the teachings of Bahramshahry.
With regards to Claim 16 Bahramshahry and further in view of Lebdeh teaches the medium of Claim 7 as referenced above. The method of Claim 16 performs the same steps as the medium of Claim 7, and Claim 16 is therefore rejected using the same art and rationale set forth above in the rejection of Claim 7 by the teachings of Bahramshahry and further in view of Lebdeh.
With regards to Claim 20, Bahramshahry teaches the system of Claim 1 as referenced above. The device of Claim 20 performs the same steps as the method of Claim 1, and Claim 20 is therefore rejected using the same art and rationale set forth above in the rejection of Claim 1 by the teachings of Bahramshahry.
21. Regarding claim 21, Bahramshahry teaches, The system of claim 1.
However, Bahramshahry fails to teach, wherein the margin for operating without errors is based on at least one operating point of a hardware component where errors begin when operating the hardware component and the hardware component loses functionality, wherein the at least one operating point is established using one or more operations performed in relation to the hardware component during a training process.
Lebdeh teaches, wherein the margin for operating without errors is based on at least one operating point of a hardware component where errors begin when operating the hardware component and the hardware component loses functionality, wherein the at least one operating point is established using one or more operations performed in relation to the hardware component during a training process (paragraph 31, 49, 50, dynamically updating the margins of specific components for variations in performance, in a validation process, selecting the margins as an operating point).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the scheduling considerations of Lebdeh to the margin table of Bahramshahry, as it allows for selecting components that minimize errors for each component.
Regarding claim 23, Bahramshahry teaches The method of claim 11, further comprising performing, by the selected hardware component, the one or more tasks. (The hardware component executes a task, paragraph 168, 169, 221, 224, 226, 229, 277, 280, 569, 669).
Claim(s) 5, 8, 15, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20210263779 A1 (Bahramshahry et. al) and further in view of US 20250094307 A1 (Lebdeh et. al), as applied to claim 1 - 4, 6, 9 – 14, 16, 18-20 above, and further view of Applicant Admitted Prior Art.
Regarding claim 5, Lebdeh teaches, The system of claim 4, wherein the selected component with the low margin for operating without errors (paragraph 34, 36, 43, 45, 61, 100 a table of performance for each component, that stores the working range for each component).
However, Bahramshahry and further in view of Lebdeh fails to teach comprises an overclocked component.
Applicant Admitted Prior Art teaches, comprises an overclocked component (paragraph 1, adjusting the components to be overclocked).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the margin table of Bahramshahry and further in view of Lebdeh with the overclocked components of the applicant admitted prior art, as it allows for achieving faster operating speeds.
Regarding claim 8, Lebdeh teaches, The system of claim 1, wherein the plurality of components comprises a plurality of processing cores, wherein the plurality of processing cores (paragraph 34, 36, 43, 45, 61, 100 a table of performance for each component, that stores the working range for each component, these components are selected for processing tasks).
However, Bahramshahry and further in view of Lebdeh fails to teach, wherein the plurality of processing cores includes at least one overclocked processing core.
Applicant Admitted Prior Art teaches teaches, wherein the plurality of processing cores includes at least one overclocked processing core (paragraph 1, adjusting the components to be overclocked).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the margin table of Bahramshahry and further in view of Lebdeh with the overclocked components of the applicant admitted prior art, as it allows for achieving faster operating speeds.
With regards to Claim 15, Bahramshahry, Lebdeh, and further in view of Applicant Admitted Prior Art teaches the medium of Claim 5 as referenced above. The method of Claim 15 performs the same steps as the medium of Claim 5, and Claim 15 is therefore rejected using the same art and rationale set forth above in the rejection of Claim 5 by the teachings of Bahramshahry, Lebdeh, and further in view of the Applicant Admitted Prior Art.
Allowable Subject Matter
Claim 22 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTIAN BAKHIT whose telephone number is (571)272-4314. The examiner can normally be reached Monday-Thursday: 6:30-5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LEWIS BULLOCK can be reached at (571) 272-3759. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.M.B./Examiner, Art Unit 2199
/LEWIS A BULLOCK JR/Supervisory Patent Examiner, Art Unit 2199
Prosecution Insights