FINAL OFFICE ACTION
Status of the Claims
Claims 1-17 and 19-21 are rejected under 35 U.S.C. 103.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 13, 15-17, 19, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Kfir et al. (U.S. Patent No. 9,946,624 B1), hereinafter referred to as Kfir, in view of Jarrett et al. (U.S. Publication No. 2015/0227410), hereinafter referred to as Jarrett.
Regarding Claim 1, Kfir teaches:
An integrated circuit (IC) device, comprising: (Col. 5, lines 18-20);
functional circuitry… configured to execute functions of a computer program; (Col. 5, lines 18-20; lines 54-63; regarding, “The target system 306 is an operating environment, or another electronic device… the target system 306 for a microprocessor DUT may be a personal computer. The target system 306 may also include memory, microprocessors, application specific integrated circuits (ASIC), field programmable gate arrays (FPGAs), and any number of similar circuitry components, which may communicate with one another to perform specific functions.”);
a processor configured provide data to the functional circuitry associated with the computer program over a first communication path based on the computer program and to initiate a trigger; (Col. 5, lines 58-63; Col. 6, lines 64-67; regarding, “the logic analyzer system is programmable to select a plurality of data signals to be sampled and probe selected data signals from the DUT 202. The selected data signals may be outputs from processors”; Col. 8, lines 54-55; regarding, “The trigger detection circuit is programmed to generate the trigger signal…”); Col. 11, lines 13-20; regarding, “in each clock cycle, the data samples captured from the DUT are first written into the segment #0 402 of the trace buffer 106 at a trace address generated by an intra-segment address counter. A trigger detection circuit detects a trigger pattern from the received data signals, and is programmable to generate a trigger signal when a trigger condition is met.”);
and data capture circuitry configured to store a state of the functional circuitry in a buffer, (Col. 5, lines 25-27; regarding, “The embedded logic analyzer may include a trace buffer to store the captured data signals from the IC.”);
and to output contents of the buffer to an external device based on the trigger. (Col. 5, lines 29-32; regarding, “The data signals stored by the embedded logic analyzer in the trace buffer may be transferred to a processing unit of an external computing device for further analysis.”).
Kfir fails to explicitly disclose but Jarrett teaches:
functional circuitry comprising intellectual property blocks configured to execute functions of a computer program; ([0041]; regarding, “Integrated circuit 300 may include processor 305, hardware state data logger 310, and logical units 340 and 345. Integrated circuit 300 may also include various other components and logical units, depending on the embodiment. Processor 305 may include L1 cache 325, which may be utilized to store data utilized by processor 305. Processor 305 may also include other logic, including execution units, fetch units, and various other units of a processor pipeline.”);
wherein the state of the functional circuitry corresponds to a point within the functional computer program. ([0033]; regarding, “hardware state data logger 130 may store the most recent information regarding one or more functional circuits which may prove to be useful in debugging when a malfunction occurs and the status of the functional circuits can be analyzed using this captured data.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to have modified Kfir with the teachings of Jarrett. Doing so can aid in the debug process and reduce the amount of time needed to verify the correct operation (Jarrett, [0042]).
Regarding Claim 2, Kfir in view of Jarrett teaches the IC device of claim 1 as referenced above. Kfir in view of Jarrett further teaches:
wherein the processor is further configured to initiate the trigger at a selectable breakpoint of the computer program. (Kfir, Col. 8, lines 54-56; regarding, “The trigger detection circuit is programmed to generate the trigger signal when the circuit designer defined trigger condition has been met.”).
Regarding Claim 3, Kfir in view of Jarrett teaches the IC device of claim 1 as referenced above. Kfir in view of Jarrett further teaches:
wherein the processor is further configured to initiate the trigger based on data generated by the functional circuitry. (Kfir, Col. 8, lines 56-58; regarding, “The trigger condition may be defined by the circuit designer based on an event or series of events that occur…”).
Regarding Claim 4, Kfir in view of Jarrett teaches the IC device of claim 3 as referenced above. Kfir in view of Jarrett further teaches:
wherein the processor is further configured to evaluate the data generated by the functional circuitry for correctness, and to initiate the trigger based on the evaluation. (Kfir, Col. 8, lines 61-66; regarding, “if A, B, and C, are data signals… when the values of these three data signals match their expected values… the trigger detection circuit would produce the trigger signal indicating that the trigger condition has been met.”)
Regarding Claim 5, Kfir in view of Jarrett teaches the IC device of claim 1 as referenced above. Kfir in view of Jarrett further teaches:
wherein the processor is further configured to output states of variables managed by the processor to the external device when the processor initiates the trigger. (Kfir, Col. 6, lines 3-5; regarding, “The trace buffer 308 stores a record of changing states of signal inputs, signal outputs…”); (Col. 5, lines 29-32; regarding, “The data signals stored by the embedded logic analyzer in the trace buffer may be transferred to a processing unit of an external computing device for further analysis.”).
Regarding Claim 6, Kfir in view of Jarrett teaches the IC device of claim 1 as referenced above. Kfir in view of Jarrett further teaches:
wherein the processor is further configured to initiate the trigger by asserting a predetermined value on the first communication path; (Kfir, Col. 8, lines 59-60; regarding, “the trigger condition may be defined based on the values of a predetermined set of data signals…”); (Col. 12, lines 13-23; regarding, “hardware emulator may include… buses for communicating data between the processors, and data lanes connecting the components of a processor.”);
and the data capture circuitry is further configured to monitor the first communication path for the predetermined value. (Col. 8, lines 54-58; regarding, “The trigger detection circuit is programmed to generate the trigger signal when the circuit designer defined trigger condition has been met. The trigger condition may be defined by the circuit designer based on an event or series of events that occur…”).
Regarding Claim 13, Kfir in view of Jarrett teaches:
An integrated circuit (IC) device, comprising:
functional circuitry comprising intellectual property blocks configured to execute functions of a computer program; (Jarrett, [0041]; regarding, “Integrated circuit 300 may include processor 305, hardware state data logger 310, and logical units 340 and 345. Integrated circuit 300 may also include various other components and logical units, depending on the embodiment. Processor 305 may include L1 cache 325, which may be utilized to store data utilized by processor 305. Processor 305 may also include other logic, including execution units, fetch units, and various other units of a processor pipeline.”);
a processor configured to provide data to the functional circuitry over a first communication path based on a computer program, (Kfir, Col. 5, lines 58-63; Col. 6, lines 64-67; regarding, “the logic analyzer system is programmable to select a plurality of data signals to be sampled and probe selected data signals from the DUT 202. The selected data signals may be outputs from processors”; Col. 12, lines 13-23; regarding, “hardware emulator may include… buses for communicating data between the processors, and data lanes connecting the components of a processor.”);
initiate a trigger, and output states of variables managed by the processor to an external device at a selectable breakpoint of the computer program; (Kfir, Col. 8, lines 54-55; regarding, “The trigger detection circuit is programmed to generate the trigger signal…”); (Col. 6, lines 3-5; regarding, “The trace buffer 308 stores a record of changing states of signal inputs, signal outputs…”); (Col. 5, lines 29-32; regarding, “The data signals stored by the embedded logic analyzer in the trace buffer may be transferred to a processing unit of an external computing device…”).
and data capture circuitry configured to store a state of the functional circuitry in a buffer, (Kfir, Col. 5, lines 25-27; regarding, “The embedded logic analyzer may include a trace buffer to store the captured data signals from the IC.”);
and to output contents of the buffer to the external device based on the trigger. (Kfir, Col. 5, lines 29-32; regarding, “The data signals stored by the embedded logic analyzer in the trace buffer may be transferred to a processing unit of an external computing device for further analysis.”).
wherein the state of the functional circuitry corresponds to a point within the functional computer program. (Jarrett, [0033]; regarding, “hardware state data logger 130 may store the most recent information regarding one or more functional circuits which may prove to be useful in debugging when a malfunction occurs and the status of the functional circuits can be analyzed using this captured data.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to have modified Kfir with the teachings of Jarrett. Doing so can aid in the debug process and reduce the amount of time needed to verify the correct operation (Jarrett, [0042]).
Regarding Claim 16, Kfir in view of Jarrett teaches:
An integrated circuit (IC) device, comprising:
programmable logic, comprising functional circuitry and data capture circuitry configured to store a state of the functional circuitry in a buffer (Kfir, Col. 5, lines 25-27; regarding, “The embedded logic analyzer may include a trace buffer to store the captured data signals from the IC.”);
and to output contents of the buffer to an external device based on a trigger, (Kfir, Col. 5, lines 29-32; regarding, “The data signals stored by the embedded logic analyzer in the trace buffer may be transferred to a processing unit of an external computing device for further analysis.”).
wherein the functional circuitry comprises intellectual property blocks configured to execute functions of a computer program, (Jarrett, [0041]; regarding, “Integrated circuit 300 may include processor 305, hardware state data logger 310, and logical units 340 and 345. Integrated circuit 300 may also include various other components and logical units, depending on the embodiment. Processor 305 may include L1 cache 325, which may be utilized to store data utilized by processor 305. Processor 305 may also include other logic, including execution units, fetch units, and various other units of a processor pipeline.”);
and wherein the state of the functional circuitry corresponds to a point within the functional computer program; (Jarrett, [0033]; regarding, “hardware state data logger 130 may store the most recent information regarding one or more functional circuits which may prove to be useful in debugging when a malfunction occurs and the status of the functional circuits can be analyzed using this captured data.”).
and a processor configured to provide data to the functional circuitry associated with the computer program over a first communication path based on the computer program, and to initiate the trigger. (Col. 5, lines 58-63; Col. 6, lines 64-67; regarding, “the logic analyzer system is programmable to select a plurality of data signals to be sampled and probe selected data signals from the DUT 202. The selected data signals may be outputs from processors”; Col. 8, lines 54-55; regarding, “The trigger detection circuit is programmed to generate the trigger signal…”); Col. 11, lines 13-20; regarding, “in each clock cycle, the data samples captured from the DUT are first written into the segment #0 402 of the trace buffer 106 at a trace address generated by an intra-segment address counter. A trigger detection circuit detects a trigger pattern from the received data signals, and is programmable to generate a trigger signal when a trigger condition is met.”);
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to have modified Kfir with the teachings of Jarrett. Doing so can aid in the debug process and reduce the amount of time needed to verify the correct operation (Jarrett, [0042]).
Regarding Claim 17, Kfir in view of Jarrett teaches the device of claim 16 as referenced above. Kfir in view of Jarrett further teaches:
Wherein the processor is further configured to at least one of: initiate the trigger at selectable breakpoint of the computer program; and initiate the trigger based on data generated by the functional circuitry. (Kfir, Col. 8, lines 54-56; regarding, “The trigger detection circuit is programmed to generate the trigger signal when the circuit designer defined trigger condition has been met.”; Col. 8, lines 59-61; regarding, “the trigger condition may be defined based on the values of a predetermined set of data signals in the DUT 202.”).
Regarding Claim 21, Kfir in view of Jarrett teaches the device of claim 1 as referenced above. Kfir in view of Jarrett further teaches:
Wherein the data capture circuitry operates synchronously with the functional circuitry. (Jarrett, Fig. 3-6, [0041]; regarding, “FIG. 3, a block diagram of one embodiment of a hardware state data logger 310 in an integrated circuit (IC) 300 is shown. Integrated circuit 300 may include processor 305, hardware state data logger 310, and logical units 340 and 345. Integrated circuit 300 may also include various other components and logical units, depending on the embodiment. Processor 305 may include L1 cache 325, which may be utilized to store data utilized by processor 305. Processor 305 may also include other logic, including execution units, fetch units, and various other units of a processor pipeline.”).
Claims 15 and 19 are rejected under 35 U.S.C 103 under the same grounds of rejections as claim 6.
Claims 7-12, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kfir et al. (U.S. Patent No. 9,946,624 B1), hereinafter referred to as Kfir, in view of Jarrett et al. (U.S. Publication No. 2015/0227410), hereinafter referred to as Jarrett, in further view of Levy et al. (U.S. Patent No. US 10754760 B1), hereinafter referred to as Levy.
Regarding Claim 7, Kfir in view of Jarrett teaches the IC device of claim 6 as referenced above. Kfir in view of Jarrett does not explicitly disclose but Levy teaches:
wherein the processor is further configured to assert the predetermined value in an address field of a memory access request. (Col. 9, lines 11-15; regarding, “In some implementations, the processor subsystem 410 and the programmable logic subsystem 430 may also read or write to memory locations of an on-chip memory (OCM) 422 or off-chip memory (not shown) via memory controller 421.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to have modified Kfir and Jarrett with the teachings of Levy. Doing so can minimize errors resulting from common cause initiators (Col. 7, lines 18-20).
Regarding Claim 8, Kfir in view of Jarrett teaches the IC device of claim 6 as referenced above. Kfir in view of Jarrett does not explicitly disclose but Levy teaches:
wherein the functional circuitry comprises a register; and the predetermined value corresponds to an address of the register. (Col. 4, lines 50-53; regarding, “Examples of trigger parameters can include program counter contents, register contents, CPU state flag contents, timestamps, etc.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to have modified Kfir and Jarrett with the teachings of Levy. Doing so can minimize errors resulting from common cause initiators (Col. 7, lines 18-20).
Regarding Claim 9, Kfir in view of Jarrett teaches the IC device of claim 1 as referenced above. Kfir in view of Jarrett does not explicitly disclose but Levy teaches:
further comprising: a second communication path between the data capture circuitry and the processor; (Col. 9, lines 1-4; regarding, “The programmable IC 402 may include various circuits to interconnect the processor subsystem 410 with circuitry implemented within the programmable logic subsystem 430. In this example, the programmable IC 402 includes a core switch 426 that can route data signals between various data ports of the processor subsystem 410 and the programmable logic subsystem 430. The core switch 426 may also route data signals between either of the programmable logic or processing subsystems 410 and 430 and various other circuits of the programmable IC, such as an internal data bus.”);
wherein the processor is further configured to initiate the trigger over the second communication path. (Col. 4, lines 64-67; Col. 5, line 1; regarding, “The fabric trigger macrocell (FTM) 230 signals the sequencer circuit 232 in the programmable logic subsystem 104 that a triggering event for capturing trace data has occurred.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to have modified Kfir and Jarrett with the teachings of Levy. Doing so can minimize errors resulting from common cause initiators (Col. 7, lines 18-20).
Regarding Claim 10, Kfir in view if Jarrett, in further view of Levy teaches the IC device of claim 9 as referenced above. Kfir in view of Jarrett in further view of Levy teaches:
wherein the processor and the data capture circuitry comprise respective master and slave interface circuitry configured to communicate with one another over the second communication path. (Levy, Col. 9, lines 66-67; Col. 10, line 1; regarding, “One or more of interfaces 466 can be implemented in the form of a Serial Peripheral Interface (SPI) bus type of interface.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to have modified Kfir and Jarrett with the teachings of Levy. Doing so can minimize errors resulting from common cause initiators (Col. 7, lines 18-20).
Regarding Claim 11, Kfir in view if Jarrett, in further view of Levy teaches the IC device of claim 9 as referenced above. Kfir in view of Jarrett in further view of Levy teaches:
wherein the processor and the data capture circuitry comprise respective first and second drivers configured to permit the processor and the data capture circuitry to communicate with one another over the second communication path; (Levy, Col. 8, lines 16-18; regarding, “The processor subsystem 410 may include various circuits 412, 414, 416, and 418 for executing one or more software programs.”); (Col. 9, lines 1-4; regarding, “The core switch 426 may also route data signals between either of the programmable logic or processing subsystems 410 and 430 and various other circuits of the programmable IC, such as an internal data bus.”);
and the processor is further configured to monitor and control the data capture circuitry through an application programming interface (API) of the first driver. (Levy, Col. 4, lines 6-9; regarding, “The debug access port provides a data and control interface between the fault detection circuitry 112 in the programmable logic subsystem and the debug interface 116 in the processor subsystem 102.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to one of ordinary skill in the art to which said subject matter pertains to have modified Kfir and Jarrett with the teachings of Levy. Doing so can minimize errors resulting from common cause initiators (Col. 7, lines 18-20).
Regarding Claim 12, Kfir in view if Jarrett, in further view of Levy teaches the IC device of claim 11 as referenced above. Kfir in view of Jarrett in further view of Levy teaches:
wherein the processor is further configured to control the data capture circuitry by configuring the data capture circuitry to output the contents of the buffer based on a selectable state of the functional circuitry. (Col. 6, lines 3-5; regarding, “The trace buffer 308 stores a record of changing states of signal inputs, signal outputs…”); (Col. 5, lines 29-32; regarding, “The data signals stored by the embedded logic analyzer in the trace buffer may be transferred to a processing unit...”).
It would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Kfir and Jarrett with the teachings of Levy for the same reasons disclosed above in the rejection of claim 11.
Claim 14 and 20 are rejected under 35 U.S.C 103 under the same grounds of rejection as claim 9.
Response to Arguments
Applicant’s arguments filed 11/20/2025, with respect to the previous rejection under 35 U.S.C. 102 on independent Claim 1, and similarly Claims 13 and 16, have been considered and a new grounds of rejection has been provided addressing the newly claimed matter. See the above detailed rejection of the newly recited subject matter.
Newly cited reference Jarrett teaches: functional circuitry comprising intellectual property blocks configured to execute functions of a computer program; wherein the state of the functional circuitry corresponds to a point within the functional computer program.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/M.D.G./Examiner, Art Unit 2113 /BRYCE P BONZO/Supervisory Patent Examiner, Art Unit 2113