DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This is response to Application 18/203,662 filed on 05/31/2023. Claims 1-4 are pending in the office action. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: F ig. 3: eqs . (4) and (5) (line 1); eqs . (16) to (23) (line 10); eqs . (11) and (12) (line 14); and eq. (15) (line 18) . Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification The disclosure is objected to because of the following informalities: there are many mathematical equations, but are not defined/labeled the equation number (see the drawing objection as above). Appropriate correction is required. Claim Objections Claim 1 is objected to because of the following informalities: line 1, after “network-on-chip” inserts -- ( NoC ) --. Appropriate correction is required. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claim s 1-4 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea of a mathematical concepts without significantly more. Step 1 : claim(s) 1 is directed to a method which is considered as a process. Thus, it falls into one of four categories statutory of invention (Step 1: Yes). Step 2A Prong One Analysis : Claim 1 is broadest reasonable interpretation to describe a numerous of steps calculating using different mathematical formulas of an integer linear programming problem of a layout method of the FPGA architecture (see the claim language and mathematical formula/calculation). Hence, claim 1 is directed to the mathematical concepted which is a judicial exception (Step 1A, Prong One: Yes). Step 2A Prong Two Analysis : Claim 1 does not recited (1) additional elements in claim beyond the judicial exception, and (2) evaluating those additional elements individual or combination to determine whether the claim as a whole integrates the exception into a practical application. See MPEP 2106.04(d). The claim itself does not include additional elements. It appears that the mathematical calculation can be solved by manual or by pen (pencil) and paper , not even solving by a generic computer. Hence, there is not additional elements integrate the recited judicial exception into a practical application (Step 2A, Prong Two: NO). Step 2B Analysis: Claim 1 does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception . Hence, claim 1 is insufficient extra-solution actively, which does not provide an inventive concept (Step 2B: No). Therefore, claim 1 is ineligible patentability subjected matter. As per claims 2-3: are also continues the mathematical calculating of claim 1. Hence, they are also ineligible patentability subjected matters. As per claim 4: is further limit of claim 1 and recited to “improve a scalability of the FPGA architecture and facilitate a scale implementation of a matched electronic design automation (EDA) tool. Thus, it is similar analysis to the claim 1. Step 1 : claim(s) 4 is directed to a method which is considered as a process. Thus, it falls into one of four categories statutory of invention (Step 1: Yes). Step 2A Prong One Analysis : Claim 4 is further limit of claim 1, Hence, claim 1 is directed to the mathematical concepted which is a judicial exception (Step 1A, Prong One: Yes). Step 2A Prong Two Analysis : Claim 4 does not recited (1) additional elements in claim beyond the judicial exception, and (2) evaluating those additional elements individual or combination to determine whether the claim as a whole integrates the exception into a practical application. See MPEP 2106.04(d). The claim itself does not include additional elements. It appears that the mathematical calculation can be solved by manual or by pen (pencil) and paper, or by a generic computer. Claim 4 is further limit of claim 1 and recited to “improve a scalability of the FPGA architecture and facilitate a scale implementation of a matched electronic design automation (EDA) tool. For the reasonable interpretation that the EDA tool may be consider as “an additional element”. However, the EDA tool have been well-known a generic tool/software to be used to solve mathematical concept. It is still a mathematical concept. Hence, this additional element does not integrate the recited judicial exception into a practical application. Hence, there is not additional elements integrate the recited judicial exception into a practical application (Step 2A, Prong Two: NO). Step 2B Analysis: C laim 4 recited “improve a scalability of the FPGA architecture and facilitate a scale implementation of a matched electronic design automation (EDA) tool”, but the claim language does not recite what feature or how to mathematical to “improve a scalability of the FPGA architecture and facilitate a scale implementation of a matched electronic design automation (EDA) tool”. It is an abstract idea of mathematical concepts. Thus, claim 4 is insufficient extra-solution actively, which does not provide an inventive concept (Step 2B: No). Therefore, claim 4 is ineligible patentability subjected matter. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claim s 1-4 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. As per claim 1: recited the limitation “the structure parameter” has different values (e.g., (), (m), (m1, m2), and (m1, …, m n ) to implement different FPGA structures, but the steps 1-5 in claim 1 does not show which parameters to be presented to FPGA structure. It appears a generic calculation without provides the different FPGA structures in the claim. Hence, these 5-calculation steps do not show the relationship to FPGA structures. Claims 2-4 are also rejected because are depended directly or indirectly from claim 1. Further claim 4, recited “using the layout method for the scalable multi-die network-on-chip FPGA architecture according to claim 1 to improve a scalability of the FPGA architecture and facilitate a scale implementation of a matched electronic design automation (EDA) tool”, but one of ordinary skill in the art unclear what step/feature/element that be able to improve a scalability of the FPGA architecture and facilitate a scale implementation of a matched electronic design automation (EDA) tool. Hence, it is indefinite. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT NGHIA M DOAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-5973 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Mon - Fri 7:00 AM - 5:00 PM . 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Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. FILLIN "Examiner Stamp" \* MERGEFORMAT NGHIA M. DOAN Primary Examiner Art Unit 2851 /NGHIA M DOAN/ Primary Examiner, Art Unit 2851