DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s election of Species I (Fig. 2, claims 1-10) in the reply filed on 10/30/2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-3 and 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over KWON (U.S 2023/0023672 A1) in view of Goh et al. (U.S 2023/0178502 A1).
As to claims 1 and 2, KWON discloses in Fig. 4A a semiconductor package, comprising: a bottom substrate (100) and a top substrate (700) space apart from the bottom substrate (100) such that the bottom substrate (100) and the top substrate (700) define a gap therebetween (Fig. 4A, para. [0022]-[0023], [0066]); a logic die (“first semiconductor chip” 201 may include a logic chip, para. [0067]) and a memory die (“second semiconductor chip” 202 may include a memory chip, para. [0067]) mounted on a top surface of the bottom substrate (100) in a side-by-side fashion (see Fig. 4A, para. [0067]); a connection structure (“conductive structures” 650) disposed between the bottom substrate (100) and the top substrate (700) around the logic die (“first semiconductor chip” 201) and the memory die (“second semiconductor chip” 202) to electrically connect the bottom substrate (100) with the top substrate (700) (Fig. 4A, para. [0066]); and a sealing resin (“molding layer” 400) filling in the gap and sealing the logic die (“first semiconductor chip” 201), the memory die (“second semiconductor chip” 202), and the connection structure (“conductive structures” 650) in the gap (Fig. 4A, para. [0025]-[0026]).
KWON does not disclose the logic die has a thickness not less than 125 micrometers; and wherein the logic die has a thickness of 125-750 micrometers.
Goh et al. disclose in Fig. 2 a semiconductor package comprising: a logic die (“processor die” 206) (Fig. 2, para. [0025]-[0026]); wherein the logic die (“processor die” 206) has a thickness not less than 125 micrometers {see Fig. 2, para. [0027], a processor die 206 can have a thickness 234 of approximately 355 μm, which is “not less than 125 micrometers” as recited in the claim}; and wherein the logic die (“processor die” 206) has a thickness of 125 -750 micrometers {see Fig. 2, para. [0027], a processor die 206 can have a thickness 234 of approximately 355 μm which falls in the recited range of “a thickness of 125 -750 micrometers” as claimed}.
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of KWON by having a logic die has a thickness not less than 125 micrometers, and wherein the logic die has a thickness of 125-750 micrometers, as taught by Goh et al., in order to improve thermal management and accommodate higher, more complex, or mixed-technology chiplet stacks without the risks of warpage or breakage by using the thicker logic die.
As to claim 3, as applied to claim 1 above, KWON and Goh et al. disclose all claimed limitations including the limitation: wherein the logic die (“first semiconductor chip” 201) is mounted on the top surface of the bottom substrate (100) in a flip-chip fashion (see Fig. 4A in KWON).
As to claim 9, as applied to claim 1 above, KWON and Goh et al. disclose all claimed limitations including the limitation: wherein the connection structure (“conductive structures” 650) comprises a plurality of conductive structures (“conductive structures” 650) and an insulating layer (400) surrounding the plurality of conductive structures (“conductive structures” 650) (Fig. 4A, para. [0068]-[0069] in KWON).
As to claim 10, as applied to claim 1 above, KWON and Goh et al. disclose all claimed limitations including the limitation: wherein the logic die (“first semiconductor chip” 201) comprises a system-on-chip die (Fig. 4A in KWON), an application processor die, or a baseband processor die.
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over KWON (U.S 2023/0023672 A1) in view of Goh et al. (U.S 2023/0178502 A1) as applied to claims 1 and 3 above, and further in view of KIM et al. (U.S 2022/0285328 A1).
As to claim 4, as applied to claims 1 and 3 above, KWON and Goh et al. disclose all claimed limitations except the limitation: wherein the logic die comprises an active front side and a passive rear side, and wherein, a plurality of input/output (I/O) pads is provided on the active front side and the logic die is electrically connected to the bottom substrate through a plurality of conductive elements formed on the plurality of I/O pads, respectively.
KIM et al. disclose in Fig. 3B a semiconductor package comprising: the logic die (701) comprises an active front side (bottom side/surface) and a passive rear side (top side/surface), and wherein, a plurality of input/output (I/O) pads (731) is provided on the active front side (bottom side/surface) and the logic die (701) is electrically connected to the bottom substrate (100) through a plurality of conductive elements (751) formed on the plurality of I/O pads, respectively (Fig. 3B, para. [0056], [0065]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of KWON with Goh et al. by having the logic die comprises an active front side and a passive rear side, and wherein, a plurality of input/output (I/O) pads is provided on the active front side and the logic die is electrically connected to the bottom substrate through a plurality of conductive elements formed on the plurality of I/O pads, respectively, as taught by KIM et al., in order to provide a greater number of signal, power, and ground connections for improving signal integrity and power distribution, and reduce the noises.
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over KWON (U.S 2023/0023672 A1) in view of Goh et al. (U.S 2023/0178502 A1) as applied to claim 1 above, and further in view of KIM et al. (U.S 2022/0285328 A1).
As to claims 5 and 6, as applied to claim 1 above, KWON and Goh et al. disclose all claimed limitations except the limitation: wherein the memory die comprises a dynamic random access memory (DRAM) die; and wherein the DRAM die comprise a Double Data Rate (DDR) DRAM die.
KIM et al. disclose in Fig. 3B a semiconductor package comprising: the memory die (702) comprises a dynamic random access memory (DRAM) die (“SDRAM”, para. [0080]) (Fig. 3B, para. [0080]); and wherein the DRAM die comprise a Double Data Rate (DDR) DRAM die (“GDDR SDRAM”, para. [0080]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of KWON with Goh et al. by having the memory die comprises a dynamic random access memory (DRAM) die, as taught by KIM et al., in order to provide a high-speed memory die having high-density capacity and high-bandwidth.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over KWON (U.S 2023/0023672 A1) in view of Goh et al. (U.S 2023/0178502 A1) as applied to claim 1 above, and further in view of KIM et al. (U.S 2022/0285328 A1) as applied to claims 5 and 6 above, and further in view of LEE et al. (U.S 2016/0329298 A1).
As to claim 7, as applied to claims 1, 5, and 6 above, KWON and Goh et al. disclose all claimed limitations except the limitation: wherein the DDR DRAM die comprise a Low Power DDR DRAM die.
LEE et al. disclose in Fig. 2 a semiconductor package comprising: a memory die (320), wherein the memory die (320) comprises a Low Power DDR DRAM die (Fig. 2, para. [0040]).
Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was made to modify reference of KWON with Goh et al. and KIM et al. by having a memory die comprises a Low Power DDR DRAM die, as taught by LEE et al., in order to reduce memory power consumption and operational costs.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANH Y TRAN whose telephone number is (571)272-2110. The examiner can normally be reached M-F, 10am-10pm (flex) (PST).
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/Thanh Y. Tran/Primary Examiner, Art Unit 2817 February 21, 2026