DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jisong(USPGPUB DOCUMENT: 2020/0343132, hereinafter Jisong) in view of Han(USPGPUB DOCUMENT: 2018/0197778, hereinafter Han) and Kim(USPGPUB DOCUMENT: 2012/0146125, hereinafter Kim).
Re claim 1 Jisong discloses in Fig 27 a semiconductor structure, comprising: a base(100); a bottom film layer(101a) structure, located on the base(100) and comprising a plurality of discrete first regions(region other than region of 600) and a plurality of second regions(region of 600) located among the first regions(region other than region of 600); top conductive layers(106a/102a), located on the bottom film layer(101a) structure of the first regions(region other than region of 600), wherein openings are enclosed between adjacent top conductive layers(106a/102a) and the bottom film layer(101a) structure; grooves(grooves of 102a/101a), located in the bottom film layer(101a) structure at bottoms of the openings, wherein bottoms of the grooves(grooves of 102a/101a) are lower than bottoms of the top conductive layers(106a/102a); and a first layer(103a/104a), located on the top conductive layers(106a/102a) and further located in the grooves(grooves of 102a/101a), wherein the first layer(103a/104a) seals tops of the openings and encloses air gaps(600) together with the openings, and bottoms of the air gaps(600) are lower than the bottoms of the top conductive layers(106a/102a).
Jisong does not disclose a first dielectric layer(103a/104a), wherein the first dielectric layer(103a/104a) seals tops of the openings and encloses air gaps(600) together with the openings, grooves, located in the bottom film layer structure in the second regions at bottoms of the openings; bottoms of the air gaps are lower than the bottoms of the top conductive layers and lower than a top of the bottom film layer structure.
Han discloses in Fig 7 a first dielectric layer(240 of Han)[0061],
It would have been obvious to one of ordinary skill in the art at the time of the inventions to use the material of Han to replace the material of Jisong’s device because such material replacement is art recognized suitability for an intended purpose. See MPEP 2144.07. In doing so, a first dielectric layer(240 of Han)[0061], wherein the first dielectric layer(103a/104a) seals tops of the openings and encloses air gaps(600) together with the openings,
Jisong and Han does not disclose grooves, located in the bottom film layer structure in the second regions at bottoms of the openings; bottoms of the air gaps are lower than the bottoms of the top conductive layers and lower than a top of the bottom film layer structure.
Kim disclose in Fig 5 grooves (groove of 150), located in the bottom film layer structure in the second regions (regions of grooves of 150) at bottoms of the openings, wherein bottoms of the grooves are lower than bottoms of the top conductive layers(175a); bottoms of the air gaps(157) are lower than the bottoms of the top conductive layers(175a) and lower than a top of the bottom film layer structure(120a/170a).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Kim to the teachings of Jisong in order to to realize semiconductor devices that operate at higher frequency and with more favorable reliability [0004, Kim].
Re claim 2 Jisong and Han and Kim disclose the semiconductor structure according to claim 1, wherein:the bottom film layer(101a) structure comprises conductive plugs[0061 of Han] located in at least a part of the first regions(region other than region of 600) and a second dielectric layer located between the conductive plugs[0061 of Han]; the top conductive layers(106a/102a) are configured to serve as top interconnect wires; and the second dielectric layer is positioned at the bottoms of the grooves(grooves of 102a/101a).
Re claim 3 Jisong and Han and Kim disclose the semiconductor structure according to claim 2, wherein a depth[0015 of Han] of each groove is 100 Angstr6m to 200 Angstr6m.
Re claim 4 Jisong and Han and Kim disclose the semiconductor structure according to claim 3, wherein: a third dielectric layer is further formed between the base(100) and the bottom film layer(101a) structure, bottom interconnect wires are formed in the third dielectric layer, and the conductive plugs[0061 of Han] are located on the bottom interconnect wires and make contact with the bottom interconnect wires.
Re claim 5 Jisong and Han and Kim disclose the semiconductor structure according to claim 1, wherein:the bottom film layer(101a) structure comprises a plurality of floating gate material layers(211 of Han) extending in a first direction and arranged in a second direction;the top conductive layers(106a/102a) are control gate layers(213 of Han), the control gate layers(213 of Han) are located on the floating gate material layers(211 of Han) in the first regions(region other than region of 600) and extend in the second direction, and the plurality of control gate layers(213 of Han) are arranged in sequence in the first direction; and the grooves(grooves of 102a/101a) penetrate through the floating gate material layers(211 of Han) located in the second regions(region of 600), and the remaining of the floating gate material layers(211 of Han) located in the first regions(region other than region of 600) are configured to serve as a floating gate layer.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Prosecution Insights