DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-5 in the reply filed on 12/03/25 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jisong(USPGPUB DOCUMENT: 2020/0343132, hereinafter Jisong) in view of Han(USPGPUB DOCUMENT: 2018/0197778, hereinafter Han).
Re claim 1 Jisong discloses in Fig 27 a semiconductor structure, comprising: a base(100); a bottom film layer(101a) structure, located on the base(100) and comprising a plurality of discrete first regions(region other than region of 600) and a plurality of second regions(region of 600) located among the first regions(region other than region of 600); top conductive layers(106a/102a), located on the bottom film layer(101a) structure of the first regions(region other than region of 600), wherein openings are enclosed between adjacent top conductive layers(106a/102a) and the bottom film layer(101a) structure; grooves(grooves of 102a/101a), located in the bottom film layer(101a) structure at bottoms of the openings, wherein bottoms of the grooves(grooves of 102a/101a) are lower than bottoms of the top conductive layers(106a/102a); and a first layer(103a/104a), located on the top conductive layers(106a/102a) and further located in the grooves(grooves of 102a/101a), wherein the first layer(103a/104a) seals tops of the openings and encloses air gaps(600) together with the openings, and bottoms of the air gaps(600) are lower than the bottoms of the top conductive layers(106a/102a).
Jisong does not disclose a first dielectric layer(103a/104a), wherein the first dielectric layer(103a/104a) seals tops of the openings and encloses air gaps(600) together with the openings,
Han discloses in Fig 7 a first dielectric layer(240 of Han)[0061],
It would have been obvious to one of ordinary skill in the art at the time of the inventions to use the material of Han to replace the material of Jisong’s device because such material replacement is art recognized suitability for an intended purpose. See MPEP 2144.07. In doing so, a first dielectric layer(240 of Han)[0061], wherein the first dielectric layer(103a/104a) seals tops of the openings and encloses air gaps(600) together with the openings,
Re claim 2 Jisong and Han disclose the semiconductor structure according to claim 1, wherein:the bottom film layer(101a) structure comprises conductive plugs[0061 of Han] located in at least a part of the first regions(region other than region of 600) and a second dielectric layer located between the conductive plugs[0061 of Han]; the top conductive layers(106a/102a) are configured to serve as top interconnect wires; and the second dielectric layer is positioned at the bottoms of the grooves(grooves of 102a/101a).
Re claim 3 Jisong and Han disclose the semiconductor structure according to claim 2, wherein a depth[0015 of Han] of each groove is 100 Angstr6m to 200 Angstr6m.
Re claim 4 Jisong and Han disclose the semiconductor structure according to claim 3, wherein: a third dielectric layer is further formed between the base(100) and the bottom film layer(101a) structure, bottom interconnect wires are formed in the third dielectric layer, and the conductive plugs[0061 of Han] are located on the bottom interconnect wires and make contact with the bottom interconnect wires.
Re claim 5 Jisong and Han disclose the semiconductor structure according to claim 1, wherein:the bottom film layer(101a) structure comprises a plurality of floating gate material layers(211 of Han) extending in a first direction and arranged in a second direction;the top conductive layers(106a/102a) are control gate layers(213 of Han), the control gate layers(213 of Han) are located on the floating gate material layers(211 of Han) in the first regions(region other than region of 600) and extend in the second direction, and the plurality of control gate layers(213 of Han) are arranged in sequence in the first direction; and the grooves(grooves of 102a/101a) penetrate through the floating gate material layers(211 of Han) located in the second regions(region of 600), and the remaining of the floating gate material layers(211 of Han) located in the first regions(region other than region of 600) are configured to serve as a floating gate layer.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812