DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 07/24/2026 has been entered.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 07/24/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3 & 5-20 have been considered but are moot because the new ground rejection is made in view of newly found prior art. The new ground rejection is detailed below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10 & 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In claim 10, the recitation of “the amplifying stage comprises a Doherty amplifier” is unclear because a Doherty amplifier does not appear to subjected to memory distortion. It is noted that Fig. 8 is disclosed a power amplifier 800 having a Doherty amplifier as illustrated in Figure 8 but does not appear subjected to memory distortion. Further clarification is needed.
In claim 17, the recitation of “a quadrature power amplifier having a gain path and a phase path” is unclear because the a quadrature power amplifier having a gain path and a phase path does not appear to subject to memory distortion as recited in claim 11.
For the purpose of the examining the examiner will treat the “memory distortion” as cited in claims 10 & 17 as inherent feature.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 & 6-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Petrovic et al. (US 10727788 B2, hereinafter called Petrovic).
Regarding claim 1:
Petrovic discloses in Fig. 8, a power amplifier comprising:
an amplifying stage (PA 508) subjected to memory distortion (Col. 15, lines 8-17 which cites “the peak envelope look-ahead block 802 may include a buffer memory that stores a running sequence of values representing the envelope E; the buffer memory length may be optimized to match the response time of the variable voltage supply 806. The stored values are analyzed to track high envelope peaks (e.g., point P in FIG. 3), and whether lower peaks can be tracked downwards from the higher peaks, based on their time occurrence and level values, considering the timing and level of the next incoming higher peak”), wherein the amplifying stage comprises a driver stage and an output stage (Col. 7, lines 61-63, preamplifiers or PA drivers ahead of a final PA stage, for even greater power savings); and
an analog predistortion (APD) circuit (form by Delay, pre-distortion block 514 and DAC 512) coupled to the amplifying stage (PA 508) and configured to predistort a signal to offset the memory distortion (Col. 15, lines 53-57, a calibration process similar to one of the types described above may be iteratively applied to adjust both the predistortion block 514 and the peak envelope look-ahead block 802 for optimum operation with respect to each other).
Regarding claim 2:
Petrovic discloses in Fig. 8, the power amplifier of claim 1, wherein the APD circuit is configured to pre-distort a phase portion of the signal to offset the memory distortion (Col. 9, lines 29-33,The measurement performance metrics and the signals used for calibration may include one or more of the following: outputting a single tone as a test signal, with measurement of gain and phase, including gain and phase compression and harmonics).
Regarding claim 3:
Petrovic discloses in Fig. 8, the power amplifier of claim 1, wherein the APD circuit is configured to predistort a phase portion and a gain portion of the signal to offset the memory distortion (Col. 9, lines 29-33,The measurement performance metrics and the signals used for calibration may include one or more of the following: outputting a single tone as a test signal, with measurement of gain and phase, including gain and phase compression and harmonics).
Regarding claim 6:
Petrovic discloses in Fig. 8, the power amplifier of claim 1, wherein the amplifying stage comprises a quadrature power amplifier having a gain path and a phase path (as shown in Fig. 9, I and Q data streams and Col. 6, lines 15-23, This particular example embodiment is useful in RF transmission systems that utilize some form of “IQ modulation”, where “I” is the “In-phase” component of a signal waveform, and “Q” is the “Quadrature” component of the signal waveform, 90° out of phase with respect to the I component. Examples of IQ modulation-based systems include QAM and PSK transmission systems).
Regarding claim 7:
Petrovic discloses in Fig. 8, the power amplifier of claim 1, wherein the APD circuit comprises a delay circuit (516) and an amplifier (e.g. DAC 512).
Claim(s) 11-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Alon et al. (US 20150333781 A1 of record, hereinafter called Alon).
Regarding claim 11:
Alon discloses in Fig. 3, a transceiver comprising:
a baseband processor (BBP) (34) comprising a digital predistortion (DPD) circuit (e.g. DPD 40) configured to apply memoryless DPD (see paragraph [0056], he DPD table 40 implements memoryless DPD, e.g., where the current output of the DPD corrected transmit signal depends only on the current input) to a signal to be transmitted; and
a power amplifier (modules 45, PA 17) coupled to the BBP and configured to receive the signal to be transmitted after the DPD circuit has applied the memoryless DPD, wherein the power amplifier comprises:
an amplifying stage (PA 17) subjected to memory distortion; and
an analog predistortion (APD) circuit (Module 37 which include DAC, paragraph [0047], modulator 37 can include DACs configured to signals into an analog format, mixers for upconverting the signals to radio frequency, and modulator 37 can include one or more filters configured to filter frequency content of signals processed therein) coupled to the amplifying stage and configured to predistort the signal to be transmitted to offset the memory distortion.
Regarding claim 12:
Alon discloses in Fig. 3, the transceiver of claim 11, wherein the DPD circuit is further configured to apply a low-depth memory DPD (DPD 40) to the signal to be transmitted.
Regarding claim 13:
Alon discloses in Fig. 3, the transceiver of claim 11, wherein the APD circuit (Module 37, paragraph [0047], example, the I/Q modulator 37 can include DACs configured to convert the I and Q signals into an analog format, mixers for upconverting the I and Q signals to radio frequency, and a signal combiner for combining the upconverted I and Q signals into an RF signal suitable for amplification by the power amplifier 17. In certain implementations, the I/Q modulator 37 can include one or more filters configured to filter frequency content of signals processed therein) is configured to predistort a phase portion of the signal to be transmitted to offset the memory distortion.
Regarding claim 14:
Alon discloses in Fig. 3, the transceiver of claim 11, wherein the APD circuit is configured to predistort a phase portion and a gain portion of the signal to be transmitted to offset the memory distortion (paragraph [0047] modulator 37 can include DACs configured to convert the I and Q signals into an analog format, mixers for upconverting the I and Q signals to radio frequency, and a signal combiner for combining the upconverted I and Q signals into an RF signal suitable (i.e., predistort a phase portion and a gain portion of the signal to be transmitted) for amplification by the power amplifier 17. In certain implementations, the I/Q modulator 37 can include one or more filters configured to filter frequency content of signals processed therein).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Petrovic in view of Kwon et al. (US 20150349731 A1, hereinafter, Kwon).
Regarding claim 5:
Petrovic discloses the limitations as applied in claim 1 and further discloses the output stage comprises a bipolar structure (Col. 7, lines 61-63, preamplifiers or PA drivers ahead of a final PA stage, for even greater power savings, and last two line of Col. 4 and first two lines of Col. 5, which states junction FETs, other insulated gate FET (IGFET) types (e.g., MOSFETs), or bipolar junction transistors (BJTs), the latter having base, emitter, and collector terminals.
Petrovic does not explicitly discloses wherein the driver stage comprises a complementary metal oxide semiconductor (CMOS) structure.
Kwon discloses in Fig. 1B, an amplifier circuit comprising a driver stage 110 (see paragraph 0034, lines 15-16, the pre-driver stage 110 may include CMOS transistors 115) being connected to an amplifier stage (includes BJT transistor, see circuit 200).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of Petrovic to have the driver stage comprises a complementary metal oxide semiconductor (CMOS) structure as taught by Kwon. Such a modification would have imparted the advantageous benefit of improve the circuit performance, see paragraph 0061, lines 9-10, as taught by Kwon to Petrovic reference, thereby suggesting the obviousness of such a modification.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Petrovic in view of Embar et al. (US 20140312975 A1, hereinafter, Embar).
Regarding claim 10 as best understood:
Petrovic discloses the limitations as applied in claim 1 except for
wherein the amplifying stage comprises a Doherty amplifier.
Embar discloses in Fig. 1 an amplifier circuit comprising main or carrier amplifier 113 and peaking amplifier 115 and wherein driver 10 being connected to the main amplifier and driver 111 being connected to the peaking amplifier.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced a generic amplifying stage of Petrovic with a Doherty amplifier as taught by Embar. Such a modification would have imparted the advantageous benefit of improve improved linearity and efficiency, see paragraph 0013, improved linearity and efficiency, as taught by Embar to Petrovic reference, thereby suggesting the obviousness of such a modification.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alon in view of Petrovic.
Regarding claim 15:
Alon discloses the limitations as applied in claim 11 except for wherein the amplifying stage comprises a driver stage.
Petrovic discloses the amplifying stage comprises a driver stage and an output stage (Col. 7, lines 61-63, preamplifiers or PA drivers ahead of a final PA stage, for even greater power savings).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of Alon to include a driver stage as taught by Petrovic. Such a modification would have imparted the advantageous benefit of improve improved gain and greater power saving as taught by Petrovic (see Col. 7, lines 60-63, such as preamplifiers or PA drivers ahead of a final PA stage, for even greater power savings) to Alon reference, thereby suggesting the obviousness of such a modification.
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Alon in view of Petrovic and further in view of Kwon et al. (US 20150349731 A1, hereinafter, Kwon).
Regarding claim 16:
The combination (Alon in view of Petrovic) discloses the limitations as applied in claim 16 except for wherein the driver stage comprises a complementary metal oxide semiconductor (CMOS) structure and the output stage comprises a bipolar structure.
Kwon discloses in Fig. 1B, an amplifier circuit comprising a driver stage 110 (see paragraph 0034, lines 15-16, the pre-driver stage 110 may include CMOS transistors 115) being connected to an amplifier stage (includes BJT transistor, see circuit 200).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the circuit of the combination ( Alon in view of Petrovic) to have the driver stage comprises a complementary metal oxide semiconductor (CMOS) structure as taught by Kwon. Such a modification would have imparted the advantageous benefit of improve the circuit performance, see paragraph 0061, lines 9-10, as taught by Kwon to Petrovic reference, thereby suggesting the obviousness of such a modification.
Claim(s) 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Alon et al. (US 20150333781 A1 of record, hereinafter called Alon) in view of Embar et al. (US 20140312975 A1, hereinafter, Embar).
Regarding claim 17 as best understood:
Alon discloses the limitations as applied in claim 11 except for wherein the amplifying stage comprises a quadrature power amplifier having a gain path and a phase path.
Embar discloses in Fig. 1 an amplifier circuit comprising main amplifier 113 and peaking amplifier 115 and wherein driver 10 being connected to the main amplifier and driver 111 being connected to the peaking amplifier.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have replaced a generic amplifying stage of Petrovic with the amplifier circuit as taught by Embar. Such a modification would have imparted the advantageous benefit of improve improved linearity and efficiency, see paragraph 0013, improved linearity and efficiency, as taught by Embar to Petrovic reference, thereby suggesting the obviousness of such a modification.
The combination (Alon in view of Embar) further discloses wherein the amplifying stage comprises a quadrature power amplifier (Fig. 1 of Embar) having a gain path (input of driver 109 to output of amplifier 113) or and a phase path (input of driver 111 to output of amplifier 115).
Allowable Subject Matter
Claims 8-9 & 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
Prosecution Insights