Prosecution Insights
Last updated: April 19, 2026
Application No. 18/203,886

FERROELECTRIC MEMORY ARRAYS WITH LOW PERMITTIVITY DIELECTRIC BARRIERS

Non-Final OA §103
Filed
May 31, 2023
Examiner
WARREN, MATTHEW E
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology, Inc.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
93%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
862 granted / 986 resolved
+19.4% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
25 currently pending
Career history
1011
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
47.8%
+7.8% vs TC avg
§102
39.7%
-0.3% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 986 resolved cases

Office Action

§103
DETAILED ACTION This Office Action is in response to the Election and Amendment filed on October 17, 2025. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Group I, claims 1-12 in the reply filed on October 17, 2025 is acknowledged. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Cronin et al. (US 9,318,693 B2) in view of the cited case law. In re claim 1, Cronin et al. shows (figs. 25, 26) an apparatus, comprising: have coplanar surfaces (the same height), and wherein at least a subset of electrode segments of the row have sidewalls that oppose sidewalls of adjacent electrode segments of the row; In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04 VI. (B). Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the device of Cronin by forming a plurality of rows of electrodes and dielectrics to provide a complete array of memory devices. In re claim 2, Cronin et al. shows (figs. 25, 26) a plurality of transistors (110, 104, 114) arranged in one or more rows of transistors (left side) extending in the first direction and one or more columns of transistors (right side) extending in a second direction orthogonal to the first direction, each transistor comprising a respective first terminal (at 112); a plurality of digit lines (114) extending in the first direction, wherein each digit line of the plurality of digit lines is coupled with respective second terminals of a respective row of transistors (right side); and a plurality of word lines (104) extending in the second direction, wherein each word line of the plurality of word lines is coupled with respective gates of a respective column of transistors. In re claim 3, Cronin, when combined with the cited case law, shows (figs. 25, 26) a plurality of dielectric walls (202), wherein each dielectric wall of the plurality of dielectric walls extends in the first direction, the plurality of dielectric walls comprising a first dielectric wall positioned between a first row of electrode segments and a second row of electrode segments adjacent to the first row and a second dielectric wall positioned between a third row of electrode segments adjacent to the second row and a fourth row of electrode segments adjacent to the third row. In re claim 4, Cronin, when combined with the cited case law, shows (figs. 25, 26) the plurality of plates comprises a first plate positioned between the second row of electrode segments and the third row of electrode segments. In re claim 5, Cronin, when combined with the cited case law, shows (figs. 25, 26) the first row of electrode segments are formed on a first sidewall of the first dielectric wall (202) and the second row of electrode segments are formed on a second sidewall of the first dielectric wall. In re claim 6, Cronin et al. shows (figs. 25, 26) each dielectric wall of the plurality of dielectric walls comprises a first dielectric material (TiALN 602) and each dielectric segment of the plurality of dielectric segments (oxide 902) comprises a second dielectric material different from the first dielectric material. In re claim 7, Cronin et al. shows (figs. 25, 26) a permittivity of the ferroelectric material (PZT 1602) is greater than a permittivity of a dielectric material (oxide 902) forming the plurality of dielectric segments (PZT has a higher permittivity than oxide). In re claim 8, Cronin et al. shows (figs. 25, 26) (Original) An apparatus, comprising: a layer of dielectric material (fig. 3, 202) comprising the art. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960). See also MPEP 2144.04 VI. (B). Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the device of Cronin by forming a plurality of cavities and other components to provide a complete array of memory devices. In re claim 9, Cronin, when combined with the cited case law, shows (figs. 25, 26) a plurality of transistors arranged in one or more rows of transistors extending in the first direction and one or more columns of transistors extending in a second direction orthogonal to the first direction, each transistor comprising a respective first terminal; a plurality of digit lines extending in the first direction, wherein each digit line of the plurality of digit lines is coupled with respective second terminals of a respective row of transistors; and a plurality of word lines extending in the second direction, wherein each word line of the plurality of word lines is coupled with respective gates of a respective column of transistors. In re claim 10, Cronin, when combined with the cited case law, shows (figs. 25, 26) each of the respective sets of electrode segments comprises: a first electrode segment coupled with a first terminal (110 left) of a first transistor; a second electrode segment coupled with a first terminal of a second transistor (110 right), the second electrode segment adjacent to the first electrode segment in the first direction; and a third electrode segment coupled with a first terminal of a third transistor, the third electrode segment adjacent to the first electrode segment in the second direction, wherein the opposing pair of sidewalls of adjacent electrode segments comprises a first sidewall of the first electrode segment and a sidewall of the second electrode segment or a second sidewall of the first electrode segment and a sidewall of the third electrode segment. In re claim 11, Cronin, when combined with the cited case law, shows (figs. 25, 26) a plurality of plate lines (2506, 2508) of the conductive material, wherein each plate line of the plurality extends in the first direction and is in contact with each post of a respective row of cavities of the plurality of cavities. In re claim 12, Cronin et al. shows (figs. 25, 26) the layer of dielectric material comprises a first dielectric material (TiAlN; 202,602) and each barrier segment (oxide, 902) of the respective sets of barrier segments comprises a second dielectric material (oxide) different from the first dielectric material (TiAlN). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Joo (US Pub. 2005/0170599 A1), Nakamura (US 6,756,262 B1), Lajoie (US Pub. 2020/0411520 A1), Avci (US Pub. 2020/0006346 A1), Manabe (US Pub. 2015/0340367 A1), Lee (US 11,903,184 B2), Tung (WO-2021056984 A1), and Nagano (JP-2006210386 A) disclose various elements of the claims. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW E WARREN/Primary Examiner, Art Unit 2815
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Prosecution Timeline

May 31, 2023
Application Filed
Jan 24, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
93%
With Interview (+5.6%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 986 resolved cases by this examiner. Grant probability derived from career allow rate.

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