Prosecution Insights
Last updated: July 17, 2026
Application No. 18/203,916

MICRO PACKAGE STRUCTURE

Non-Final OA §103
Filed
May 31, 2023
Priority
Jun 02, 2022 — CN PCT/CN2022/096932
Examiner
ARROYO, TERESA M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Jade Bird Display (shanghai) Limited
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
357 granted / 497 resolved
+3.8% vs TC avg
Strong +23% interview lift
Without
With
+23.2%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
47 currently pending
Career history
539
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
79.5%
+39.5% vs TC avg
§102
10.4%
-29.6% vs TC avg
§112
7.3%
-32.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 497 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species A (claims 1-20) in the reply filed on 4/13/2026 is acknowledged. Claim Objections Claim 4 is objected to because of the following informalities: The phrase “the IC substrate comprises: a plurality of first metal connected holes connecting the plurality of micro LEDs and the IC substrate” implies the substrate is connected to itself. Instead, according to paragraph [0026] of the specification of this application, the holes 193 / 194 are formed in a top layer 134 of the IC substrate 131. Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1, 4, 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2022/0020310 (Gray) in view of U.S. Patent Application Publication No. 2017/0301283 (Liu). Gray discloses (Fig. 3A) 1. A micro package structure, comprising: a micro LED panel 300 ([0024]) comprising an IC (integrated circuit) substrate 330 (Abstract) and an micro LED array area 340 ([0057]) formed on the IC substrate 330, the IC substrate 330 comprising a first connected area (under LED layer 370) corresponding to the micro LED array area 340 and a second connected area (surrounding the first connected area) away from the first connected area, a plurality of signal metal pads 350 / 360 (equivalent traces / redistribution) are formed on the second connected area; and one or more bonding wires 355 to connect the signal metal pads 350 with an external circuit ([0055], [0066]). Gray fails to disclose a top cover plane formed above the micro LED panel, wherein light emitted from the micro LED array area is transmitted upward to the top cover plane. Liu teaches (Fig. 2) A micro package structure, comprising: a top cover plane 203 / 204 formed above the micro LED panel 202, wherein light emitted from the micro LED array area (where LEDs 202B are mounted) is transmitted upward to the top cover plane 203 / 204 ([0028]). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a top cover plane in Gray. The motivation would be to provide a color filter and protection for the structure which is well-known in LED packages as taught by Liu. See MPEP 2144.03. Gray discloses (Figs. 3A-3C) 4. The micro package structure according to claim 1, wherein the micro LED array area 370 comprises a plurality of micro LEDs ([0028]); and the IC substrate 330 comprises: a plurality of first metal connected holes 332 connecting the plurality of micro LEDs [[and]] to a bottom 334 / 365 of the IC substrate 330, and a plurality of second metal connected holes 332 (surrounding area) connecting to the plurality of signal metal pads 350 / 360. Liu teaches ([0028]) 18. The micro package structure according to claim 4, wherein the top cover plane 203 / 204 is transparent. Liu teaches ([0028]) 19. The micro package structure according to claim 18, wherein a material of the top cover plane 203 / 204 is organic glass or inorganic glass. Liu teaches (Fig. 2) 20. The micro package structure according to claim 18, wherein a thickness of the top cover plane 203 / 204 is not greater than a thickness of the micro LED panel. Claim(s) 2, 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gray in view of Liu as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2021/0066828 (Woo). The combination of references fails to teach 2. The micro package structure according to claim 1, wherein the signal metal pads comprise a plurality of IO (input/output) metal pads and a plurality of dummy metal pads; and all of the IO metal pads and at least some of the dummy metal pads are formed on the second connected area. Woo teaches (Figs. 5, 7, 10, 14) A micro package structure, comprising: the signal metal pads DMP1 - DMP4, DTP1, DTP2 comprise a plurality of IO (input/output) metal pads DTP1, DTP2 and a plurality of dummy metal pads DMP1 - DMP4; and all of the IO metal pads DTP1, DTP2 and at least some of the dummy metal pads DMP1 - DMP4 are formed on the second connected area 510. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide signal metal pads in the modified device of Gray. The motivation would be to provide reduce tilting and shifting, thereby reducing or preventing damage, such as electrical and/or mechanical disconnection, which is well-known in LED packages as taught by Woo ([0007]). See MPEP 2144.03. Woo teaches 3. The micro package structure according to claim 2, wherein all of the dummy metal pads DMP1 - DMP4 are formed on the second connected area 510. Claim(s) 5-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gray in view of Liu as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2023/0176407 (Haisch). The combination of references fails to teach 5. The micro package structure according to claim 1, further comprising a protective layer formed on a surface of the second connected area and covering around a surface of the one or more bonding wires. Haisch teaches (Figs. 3A-3C, 4A-4C, 5A-5C) A micro package structure, comprising: a protective layer ([0091]-[0095]) formed on a surface of the second connected area 408 / 409 and covering around a surface of the one or more bonding wires 406. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide a protective layer in the modified device of Gray. The motivation would be to provide mechanical protection, which is well-known in LED packages as taught by Haisch. See MPEP 2144.03. Haisch teaches (Figs. 4A-4C) 6. The micro package structure according to claim 5, further comprising an external circuit plane 408 / 409 formed at a bottom of the micro LED panel 401 with an extruded part extending outside of the micro LED panel. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide an external circuit plane in the modified device of Gray. The motivation would be to couple to a flex printed circuit (FPC) that provides electrical connections from a host platform as taught by Haisch ([0070]). Haisch teaches (Figs. 4A-4C) 7. The micro package structure according to claim 6, wherein the protective layer is further formed on a surface of the extruded part 408 / 409. Haisch teaches (Figs. 4A-4C) 8. The micro package structure according to claim 6, further comprising a support base plane 414 formed at a bottom of the external circuit plane 408 / 409. Haisch teaches ([0088]) 9. The micro package structure according to claim 8, wherein the support base 414 plane is rigid. Haisch teaches (Figs. 4A-4C) 10. The micro package structure according to claim 5, further comprising an external circuit plane 408 / 409 formed extending outside of a bottom of the micro LED panel 401. Haisch teaches (Figs. 4A-4C) 11. The micro package structure according to claim 10, wherein the protective layer ([0091]-[0095]) is further formed on a part of the external circuit plane 408 / 409. Haisch teaches (Figs. 4A-4C) 12. The micro package structure according to claim 4, further comprising a support base plane 414 formed at a bottom surface of the micro LED panel 401. Haisch teaches ([0088]) 13. The micro package structure according to claim 12, wherein the support base plane 414 is rigid. Haisch teaches (Figs. 4A-4C) 14. The micro package structure according to claim 5, wherein a top of the protective layer ([0091]-[0095]) is lower than a top of the top cover plane 412. Haisch fails to teach 15. The micro package structure according to claim 14, wherein the top of the protective layer is lower than a top of the micro LED array area. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select the height of the protective layer in the modified device of Gray. The motivation would a matter of routine engineering design considerations as taught by Haisch. See MPEP 2144.04. Haisch teaches ([0087]) 16. The micro package structure according to claim 5, wherein a material of the protective layer ([0091]-[0095]) comprises a resin and a polymer. Haisch teaches ([0087]) 17. The micro package structure according to claim 16, wherein the resin is epoxy resin and the polymer is silicone. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. WO Publication No. 2020/017823 (Jung), U.S. Patent Application Publication No. 2015/0373793 (Bower), U.S. Patent No. 12,020,630 (He), U.S. Patent Application Publication No. 2019/0067533 (Chen) teach a micro package structure including features such as a micro LED panel, a top cover plane, and bonding wires. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TERESA M ARROYO whose telephone number is (703)756-1576. The examiner can normally be reached Monday - Friday (8:30 A.M. E.T. - 5:00 P.M. E.T.). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571.272.1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TERESA M. ARROYO/Primary Examiner, Art Unit 2893
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Prosecution Timeline

May 31, 2023
Application Filed
May 04, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
95%
With Interview (+23.2%)
3y 0m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 497 resolved cases by this examiner. Grant probability derived from career allowance rate.

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