Prosecution Insights
Last updated: April 19, 2026
Application No. 18/204,039

SEMICONDUCTOR DEVICE, FABRICATING METHOD, MEMORY DEVICE AND DEVICE SYSTEM

Non-Final OA §103
Filed
May 31, 2023
Examiner
NGUYEN, THANH T
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Yangtze Memory Technologies Co. Ltd.
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
2y 10m
To Grant
97%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allow Rate
1162 granted / 1397 resolved
+15.2% vs TC avg
Moderate +14% lift
Without
With
+13.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
39 currently pending
Career history
1436
Total Applications
across all art units

Statute-Specific Performance

§101
3.2%
-36.8% vs TC avg
§103
51.7%
+11.7% vs TC avg
§102
28.1%
-11.9% vs TC avg
§112
5.8%
-34.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1397 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Election/Restrictions Applicant’s election without traverse of group I, claims 1-13, 20 in the reply filed on 1/28/26 is acknowledged. Claims 14-19 are withdrawn from further consideration by the examiner, 37 C.F.R. 1.142(b) as being drawn to a non-elected invention. Oath/Declaration Oath/Declaration filed on 5/31/23 has been considered. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 1-13, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Miccoli et al. (U.S. Patent Publication No. 2012/0211748) in view of Wong et al. (U.S. Patent Publication No. 2023/0290684). Referring to figures 3A-4F, Miccoli et al. teaches a semiconductor device, comprising: a first device (120a); a dicing street (132a) adjoining the first device laterally; a metal structure (CP/M1/V1/M2/V2/M3/V3/M4/V4/M5/V5/M6) located in the dicing street (see figure 3C); and a stealth cleavage lane extending in the dicing street (see paragraphs# 69-75); However, the reference does not clearly teach a first orthogonal projection of the stealth cleavage lane on a lateral cross-section of the dicing street is distant from a second orthogonal projection of the metal structure on the lateral cross-section of the dicing street (in claim 1) and a peripheral circuit coupled with the memory array (in claims 13, 20). Wong et al. teaches a first orthogonal projection of the stealth cleavage lane on a lateral cross-section of the dicing street is distant from a second orthogonal projection of the metal structure on the lateral cross-section of the dicing street (see paragraphs# 19, 24, 30, s 1-2, meeting claim 1) and a peripheral circuit coupled with the memory array (see paragraphs# 24-25, figures 2, 9, meeting claims 13, 20). Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would provide a first orthogonal projection of the stealth cleavage lane on a lateral cross-section of the dicing street is distant from a second orthogonal projection of the metal structure on the lateral cross-section of the dicing street and a peripheral circuit coupled with the memory array in Miccoli et al. as taught by Wong et al. because it is known in the art to improve dicing quality and reduce chipping at edges and corners in a memory die. Regarding to claim 2, a second device (120b), wherein the first device (120a) comprises a first sealing ring (160a), the second device (120b) comprises a second sealing ring (160b), and the dicing street (132a) is located between the first sealing ring and the second sealing ring (see figure 3d). Regarding to claim 3, the metal structure (CP/M1/V1/M2/V2/M3/V3/M4/V4/M5/V5/M6) comprises a first side edge adjacent to the first sealing ring (160a) and a second side edge adjacent to the second sealing ring (160b); and the stealth cleavage lane is located between the first side edge and the first sealing ring (see figures 3A-3I). Regarding to claim 4, the first device (120a) comprises at least one pad (M6) disposed on a side of the first sealing ring away from the dicing street (see figures 3A-3I). Regarding to claim 5, the second side edge is distant from the second sealing ring (160b) by at least one unit-length of distance; the stealth cleavage lane (132) is distant from the first sealing ring (160a) by at least two unit-lengths of distance; and the first side edge is distant from the first sealing ring (160a) by at least three unit-lengths of distance (see figures 3A-3I). However, the reference does not clearly teach specific each unit-length (in claims 5-6), a specific distance between the side edges and sealing rings (in claims 7-8), specific distance between the stealth cleavage lane and the first sealing ring (in claims 9-10), the specific first, second and third distance (in claims 10-12). In re claims 5-11, the selection of the specific distance is obvious because it is a matter of determining optimum process condition by routine experimentation with a limited number of species. In re Jones, 162 USPQ 224 (CCPA 1955) (the selection of optimum ranges within prior art general conditions is obvious) and In re Boesch, 205 USPQ 215 (CCPA 1980) (discovery of optimum value of result effective variable in a known process is obvious). In such a situation, applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to prior art range. See M.P.E.P 2144.05 III. In particular, Miccoli et al. suggest that the distance can be optimized (see figures 3a-3I). It would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was made to optimize specific each unit-length, a specific distance between the side edges and sealing rings, specific distance between the stealth cleavage lane and the first sealing ring, the specific first, second and third distance, since it has been held that where the general conditions of a claim are disclosed in the prior art , discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955). Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was filed would provide specific each unit-length, a specific distance between the side edges and sealing rings, specific distance between the stealth cleavage lane and the first sealing ring, the specific first, second and third distance in Miccoli et al. as taught by Wong et al. because it is known in the semiconductor art to form very sharp chip sidewalls, virtually no cracks, virtually no chipping, virtually no pad corrosion, no wafer dust on chip surface, virtually no delamination of the top layers of the chip (see paragraph# 87). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pairdirect.uspto.gov. Should you have questions on access to thy Private PAIR system, contact the Electronic Business center (EBC) at 866-217-9197 (toll-free). /THANH T NGUYEN/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

May 31, 2023
Application Filed
Feb 20, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
97%
With Interview (+13.9%)
2y 10m
Median Time to Grant
Low
PTA Risk
Based on 1397 resolved cases by this examiner. Grant probability derived from career allow rate.

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