DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, claims 1-10, in the reply filed on February 27, 2026 is acknowledged. Claims 11-20 have been withdrawn. However, upon inspection, the Applicant neglected to elect between Species 1-5 which was required in the requirement for restriction filed on December 30, 2025. The Examiner reached out to the Applicant’s Representative, Nicholas P. Bell (#79,082), via telephone on September 25, 2026 in regards this issue.
Applicant’s further elected without traverse of Species 3, Fig. 2B, item 200B, claims 1 and 3-10, by telephone on September 25, 2026 is acknowledged. Claims 11-20 are still withdrawn. Action on the merits is as follows:
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 3-10 have been considered but are moot on grounds of new rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 3-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (Hung) (US 2017/0229426 A1) as evidenced by or in view of Lee et al. (Lee) (US 2012/0126421 A1) in view of Karnezos et al. (Karnezos) (US 7,372,141 B2).
In regards to claim 1, Hung (Fig. 1 and associated text) discloses a semiconductor package (item 100) comprising: a first side (top or bottom surface/side) of the semiconductor package (item 100) and a second side (top or bottom surface/side) of the semiconductor package (item 100), wherein the second side (top or bottom surface/side) of the semiconductor package (item 100) includes a plurality of terminals (item 190); a back-to-back (BTB) die (items 110 plus 120) comprised of a first die (items 110 or 120) electrically coupled to a second die (items 110 or 120); the first die (items 110 or 120) electrically coupled to a first portion of the plurality of terminals (items 150 or 160) through a first plurality of electrical traces (items 150 or 160) and a plurality of blocks (item 140); the second die (items 110 or 120) electrically coupled to a second portion of the plurality of terminals (item 190) through a second plurality of electrical traces (items 150 or 160); wherein the BTB die (items 110 plus 120) is configured to cease functioning if an electrical connection to one of the plurality of terminals is broken.
Examiner notes that the Applicant needs claim structurally how the BTB die is configured in order to cease functioning if an electrical connection to one of the plurality of terminals is broken”.
Hung does not specifically disclose Si blocks.
However, Hung (paragraph 18) disclose blocks (item 140) is made of a conductive material. Examiner notes that this encompasses metals, doped silicon, doped polysilicon, etc..
As evidenced by Lee (paragraph 27, Figs. 1A, 1B and associated text), conductive pillars (blocks) can be made of “a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), a transition metal (e.g., titanium, tantalum, etc.) or a conductive metal-semiconductor compound (e.g., metal silicide)”.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Lee for the purpose of an electrical connection, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
Hung as evidenced and/or modified by Lee (paragraph 27, Figs. 1A, 1B and associated text) does not specifically disclose further comprising a heat sink disposed on the first side of the semiconductor package, wherein the heat sink is coupled to one or more terminals of the plurality of terminals disposed on the second side of the semiconductor package.
Karnezos (Fig. 14 and associated text) discloses back-to-back (BTB) die (items 14, 114) comprised of a first die (items 14 or 114) electrically coupled to a second die (items 14 or 114); the first die (items 14 or 114) electrically coupled to a first portion of the plurality of terminals (items 21, 22, 23 or 121, 122, 123, 318) through a first plurality of electrical traces (items 21, 22, 23 or 121, 122, 123, 318);…the second die (items 14 or 114) electrically coupled to a second portion of the plurality of terminals (items 21, 22, 23 or 121, 122, 123, 318) through a second plurality of electrical traces (items 21, 22, 23 or 121, 122, 123, 318)…a heat sink (item 1400, heat spreader) disposed on the first side of the semiconductor package (item 140), wherein the heat sink is coupled to one or more terminals of the plurality of terminals (items 21, 22, 23 or 121, 122, 123, 318) disposed on the second side of the semiconductor package (item 140).
Therefore it would have been obvious to one ordinary skill in the art before the effective filing date to incorporate the teachings of Karnezos for the purpose of heat dissipation.
In regards to claim 3 Hung (Figs. 1, 4H, 4I and associated text) as evidenced and/or modified by Lee (paragraph 27, Figs. 1A, 1B and associated text) and Karnezos (Fig. 14 and associated text) discloses wherein the heat sink (item 1400, Karnezos) is coupled to the one or more terminals (item 190, Hung, items 21, 22, 23 or 121, 122, 123, 318, Karnezos) on the second side of the semiconductor package (item 100, Hung, item 140, Karnezos) by one or more Si blocks (item 140, Hung).
In regards to claim 4, Hung (Fig. 1 and associated text) discloses wherein the first die (items 110 or 120) is electrically coupled to the first plurality of electrical traces (items 150 or 160) with a plurality of vias (item 140) through a first lamination layer (item 130).
In regards to claim 5, Hung as evidenced and/or modified by Lee and Karnezos does not specifically disclose wherein the first lamination layer is comprised of ABF.
It would have been obvious to modify the invention to include a first lamination layer being comprised of ABF, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 6, Hung (Fig. 1 and associated text) as evidenced and/or modified by Lee (paragraph 27, Figs. 1A, 1B and associated text) discloses wherein at least one of the plurality of Si blocks (item 140, Hung, paragraph 27, item 115, Lee) is positioned on at least a first lateral side of the BTB die (items 110 plus 120) and at least a second of the plurality of Si blocks (item 140, Hung, paragraph 27, item 115, Lee) is positioned on at least a second lateral side of the BTB die (items 110 plus 120).
In regards to claim 7, Hung (Fig. 1 and associated text) as evidenced and/or modified by Lee (paragraph 27, Figs. 1A, 1B and associated text) discloses wherein each lateral side of the BTB die (items 110 plus 120, Hung) has at least one of the plurality of Si blocks (item 140, Hung, paragraph 27, item 115, Lee) are positioned on the respective lateral side.
In regards to claim 8, Hung (Fig. 1 and associated text) as evidenced and/or modified by Lee (paragraph 27, Figs. 1A, 1B and associated text) does not specifically disclose wherein a first Si block (item 140, Hung, paragraph 27, item 115, Lee) of the plurality of Si blocks (item 140, Hung, paragraph 27, item 115, Lee) is a different height than at least a second Si block (item 140, Hung, paragraph 27, item 115, Lee) of the plurality of Si blocks (item 140, Hung, paragraph 27, item 115, Lee).
It would have been obvious to modify the invention to include a first Si block of the plurality of Si blocks being a different height than at least a second Si block of the plurality of Si blocks, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 9, Hung (Fig. 1 and associated text) discloses wherein the plurality of electrical traces (items 150 or 160) are in a fan-out pattern.
In regards to claim 10, Hung (Figs. 1, 4H, 4I and associated text) discloses wherein the semiconductor package (item 100) is a first semiconductor package (item 100) in a plurality of semiconductor packages (item 100) in a panel.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Manusharow et al (KR 20130083933 A, Fig. 5, item 500), Bao et al (WO 2021253225 A1, Figs. 5-10, 20, 24, 25, 31, 33, 35, 37, 39, 40) and Vincent (US 2015/0108661 A1, Figs. 1, 12) all disclose back-to-back die configurations and could have possibly been used in place of Hung as the primary reference. Examiner suggests that the Applicant review these references and amend accordingly in order to promote compact prosecution.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 September 25, 2026
