Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claims 5 and 14 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Specifically, claim 5’s disclosure of “disposing the semiconductor chip such that a number of the cover insulating layer is one between the main portion of the second metal layer and the semiconductor chip” (emphasis added) is already disclosed in claim 1 upon which it depends: claim 1 discloses “forming a cover insulating layer on an upper surface of the main portion of the second metal layer; and disposing a semiconductor chip on an upper surface of the cover insulating layer” (emphasis added). Claim 14 is rejected for the same subject matter and reasoning, but in relation to its dependence on claim 11 (by way of claims 12 and 13). Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
Claim(s) 1-9 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Kaneko (PGPub No. 20130143062) in further view of and Lee (US Patent No. 10438884).
Regarding claim 1, Kaneko teaches a method of manufacturing a semiconductor package, the method comprising: applying a cutter to a boundary between a main portion of a second metal layer and an edge portion of the second metal layer that surrounds the main portion, the second metal layer being on an upper surface of a first metal layer disposed on an upper surface of a carrier substrate, and peeling the edge portion of the second metal layer from the first metal layer while retaining the main portion of the second metal layer such that the edge portion is removed from the first metal layer and the first metal layer remains on the carrier substrate after the peeling (Figs. 1A-1B point to a layered body 10/10A comprising a metal foil 13 (carrier substrate), a peeling layer 12 (first metal layer), and a metal foil 11 (second metal layer) made up of an edge part 11A (edge portion) that is removed and a metal foil 11B (main portion) that remains. [0035] further points to removing the edge part 11A by forming a cut line between a border between the edge part 11A and the metal foil 11B by using a laser (half cut), and peeling the edge part 11A from the metal foil 11.).
Kaneko fails to teach forming a cover insulating layer on an upper surface of the main portion of the second metal layer; and disposing a semiconductor chip on an upper surface of the cover insulating layer.
Lee teaches forming a cover insulating layer on an upper surface of the main portion of the second metal layer (Fig. 18 points to a semiconductor package comprising an interposer 210 including an insulating layer (cover insulating layer) and a unit pattern 110a (second metal layer).); and disposing a semiconductor chip on an upper surface of the cover insulating layer (Fig. 19 points to semiconductor chip(s) 220 formed on the interposer(s) 210 (cover insulating layer).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Kaneko and Lee, such that a cover insulating layer is formed between the existing second metal layer/carrier substrate and newly formed semiconductor chip in order to create a detachable carrier that is electrically separated from the semiconductor chip yet can still provide a physical base that allows for further manipulation of said chip and/or other fabrication processes.
Regarding claim 2, Kaneko teaches wherein the first metal layer is not divided into a plurality of portions by the cutter ([0035] points to removing the edge part 11A by forming a cut line between a border between the edge part 11A and the metal foil 11B.).
Regarding claim 3, Kaneko teaches wherein the cutter comprises a laser and the applying includes irradiating the laser onto the boundary ([0035] points to removing the edge part 11A by forming a cut line between a border between the edge part 11A and the metal foil 11B by using a laser.).
Regarding claim 4, Kaneko teaches wherein the peeling includes pulling the edge portion of the second metal layer from the first metal layer or applying a force to the edge portion of the second metal layer in a direction different from a direction facing the first metal layer ([0035] further points to peeling the edge part 11A from the metal foil 11.).
Regarding claim 5, Lee teaches wherein the disposing of the semiconductor chip includes disposing the semiconductor chip such that a number of the cover insulating layer is one between the main portion of the second metal layer and the semiconductor chip (Fig. 19 points to semiconductor chip(s) 220 formed on the interposer(s) 210 (cover insulating layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kaneko and Lee, such that a cover insulating layer is formed between the existing second metal layer/carrier substrate and newly formed semiconductor chip in order to create a detachable carrier that is electrically separated from the semiconductor chip yet can still provide a physical base that allows for further manipulation of said chip and/or other fabrication processes.
Regarding claim 6, Lee teaches wherein the disposing of the semiconductor chip includes disposing the semiconductor chip such that a first surface of the semiconductor chip is in contact with the cover insulating layer (Fig. 19 points to a semiconductor package using a carrier substrate comprising semiconductor chip(s) 220 formed such that one surface (first surface) is on the interposer(s) 210 (cover insulating layer).), and a second surface of the semiconductor chip opposite to a first surface of the semiconductor chip that is electrically connected to a redistribution layer (Fig. 7 points to an alternative embodiment comprising semiconductor chips 221’, 222’, and 223’ which are each formed such that one surface (second surface) is in contact with an organic interposer 210’ (redistribution layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kaneko and Lee, such that a redistribution layer is further formed and attached to the semiconductor chip and away from the cover insulating layer/carrier substrate in order to create multiple electrical pathways that connect to the semiconductor chip, a process which would be perfected by the use of the cover insulating layer/carrier substrate as a temporary base from which the semiconductor chip could be properly lined up with the redistribution layer.
Regarding claim 7, Lee teaches after the semiconductor chip is disposed, detaching the carrier substrate and the first metal layer from the main portion of the second metal layer and the cover insulating layer (Figs. 7-8 point to removing a core layer 101’ (carrier substrate) and a metal film 102’ (first metal layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kaneko and Lee, such that the carrier substrate and the first metal layer are detached in order to allow for the formation of an electrical connection structure.
Regarding claim 8, Lee teaches wherein the carrier substrate contains a prepreg (Col. 6, lines 20-23 point to the core layer 101’ (carrier substrate) which may be provided as, for example, a prepreg including an insulating resin, an inorganic filler, and a glass fiber, but is not limited thereto.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kaneko and Lee, such that the carrier substrate contains a prepreg in order provide adequate physical stability and/or electrical insulation.
Regarding claim 9, Lee teaches wherein each of the first metal layer and the second metal layer is a single metal layer containing copper (Col. 6, lines 24-25 point to each of the metal films 102′ (first metal layer) and 103′ (second metal layer) including a metal such as copper.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kaneko and Lee, such that each of the first metal layer and the second metal layer is a single metal layer containing copper in order to create a suitable interface between the carrier substrate and the components above that form the final semiconductor package.
Regarding claim 21, Kaneko teaches wherein the edge portion surrounds the main portion of the second metal layer in plan view (Figs. 1A-1B point to the edge part 11A (edge portion) and the metal foil 11B (main portion).).
Regarding claim 22, Kaneko teaches wherein the edge portion is an outermost portion of the second metal layer surrounding the main portion (Figs. 1A-1B point to the edge part 11A (edge portion) and the metal foil 11B (main portion).).
Claim(s) 10-15 and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Kaneko et al. in further view of Lee2 (PGPub No. 20060071303).
Regarding claim 10, Lee2 teaches wherein a thickness of the second metal layer is greater than 1 µm and less than 10 µm (Fig. 5C and [0044] point to a manufacturing process for a film substrate of semiconductor packages comprising a copper metal layer 23 (second metal layer) with a thickness t2 which is about 1-5 µm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kaneko et al. and Lee2, such that the second metal layer is provided an adequate thickness in order to obtain fine line widths and gaps following a machining/cutting process.
Regarding claim 11, Kaneko teaches a method of manufacturing a semiconductor package, the method comprising: exposing a portion of a first metal layer by removing an edge portion of a second metal layer that surrounds a main portion of the second metal layer, the second metal layer being on an upper surface of the first metal layer disposed on an upper surface of a carrier substrate, the edge portion of the second metal layer being removed while retaining the main portion of the second metal layer such that the edge portion is removed from the first metal layer and the first metal layer remains on the carrier substrate after the removal (Figs. 1A-1B point to a layered body 10/10A comprising a metal foil 13 (carrier substrate), a peeling layer 12 (first metal layer), and a metal foil 11 (second metal layer) made up of an edge part 11A (edge portion) that is removed and a metal foil 11B (main portion) that remains.).
Kaneko fails to teach forming a cover insulating layer on an upper surface of the main portion of the second metal layer; and disposing a semiconductor chip on an upper surface of the cover insulating layer, wherein a thickness of the second metal layer is greater than 1 pm and less than 10 pm.
Lee teaches forming a cover insulating layer on an upper surface of the main portion of the second metal layer (Fig. 18 points to a semiconductor package comprising an interposer 210 including an insulating layer (cover insulating layer) and a unit pattern 110a (second metal layer).); and disposing a semiconductor chip on an upper surface of the cover insulating layer (Fig. 19 points to semiconductor chip(s) 220 formed on the interposer(s) 210 (cover insulating layer).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Kaneko and Lee, such that a cover insulating layer is formed between the existing second metal layer/carrier substrate and newly formed semiconductor chip in order to create a detachable carrier that is electrically separated from the semiconductor chip yet can still provide a physical base that allows for further manipulation of said chip and/or other fabrication processes.
Kaneko et al. still fails to teach wherein a thickness of the second metal layer is greater than 1 µm and less than 10 µm.
Lee2 teaches wherein a thickness of the second metal layer is greater than 1 µm and less than 10 µm (Fig. 5C and [0044] point to a manufacturing process for a film substrate of semiconductor packages comprising a copper metal layer 23 (second metal layer) with a thickness t2 which is about 1-5 µm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kaneko et al. and Lee2, such that the second metal layer is provided an adequate thickness in order to obtain fine line widths and gaps following a machining/cutting process.
Regarding claim 12, Lee teaches wherein each of the first metal layer and the second metal layer is a single metal layer containing copper (Col. 6, lines 24-25 point to each of the metal films 102′ (first metal layer) and 103′ (second metal layer) including a metal such as copper.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kaneko and Lee, such that each of the first metal layer and the second metal layer is a single metal layer containing copper in order to create a suitable interface between the carrier substrate and the components above that form the final semiconductor package.
Regarding claim 13, Lee teaches wherein the carrier substrate contains a prepreg (Col. 6, lines 20-23 point to the core layer 101’ (carrier substrate) which may be provided as, for example, a prepreg including an insulating resin, an inorganic filler, and a glass fiber, but is not limited thereto.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kaneko and Lee, such that the carrier substrate contains a prepreg in order provide adequate physical stability and/or electrical insulation.
Regarding claim 14, Lee teaches wherein the disposing of the semiconductor chip includes disposing the semiconductor chip such that a number of the cover insulating layer is one between the main portion of the second metal layer and the semiconductor chip (Fig. 19 points to semiconductor chip(s) 220 formed on the interposer(s) 210 (cover insulating layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kaneko and Lee, such that a cover insulating layer is formed between the existing second metal layer/carrier substrate and newly formed semiconductor chip in order to create a detachable carrier that is electrically separated from the semiconductor chip yet can still provide a physical base that allows for further manipulation of said chip and/or other fabrication processes.
Regarding claim 15, Lee teaches wherein the disposing of the semiconductor chip includes disposing the semiconductor chip such that a first surface of the semiconductor chip is in contact with the cover insulating layer (Fig. 19 points to a semiconductor package using a carrier substrate comprising semiconductor chip(s) 220 formed such that one surface (first surface) is on the interposer(s) 210 (cover insulating layer).), and a second surface of the semiconductor chip opposite to a first surface of the semiconductor chip that is electrically connected to a redistribution layer (Fig. 7 points to an alternative embodiment comprising semiconductor chips 221’, 222’, and 223’ which are each formed such that one surface (second surface) is in contact with an organic interposer 210’ (redistribution layer). It is considered obvious that one of ordinary skill in the art could combine the structures taught in Figs. 19 and 7 respectively, such that one side of a semiconductor chip (first surface) is first attached to the interposer 210 (cover insulating layer) of a carrier substrate in order to create a temporary base to provide physical stability, followed by connecting the opposite side of the semiconductor chip (second surface) to the organic interposer 210’ (redistribution layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Kaneko and Lee, such that a redistribution layer is further formed and attached to the semiconductor chip and away from the cover insulating layer/carrier substrate in order to create multiple electrical pathways that connect to the semiconductor chip, a process which would be perfected by the use of the cover insulating layer/carrier substrate as a temporary base from which the semiconductor chip could be properly lined up with the redistribution layer.
Regarding claim 23, Kaneko teaches wherein the edge portion surrounds the main portion of the second metal layer in plan view (Figs. 1A-1B point to the edge part 11A (edge portion) and the metal foil 11B (main portion).).
Regarding claim 24, Kaneko teaches wherein the edge portion is an outermost portion of the second metal layer surrounding the main portion (Figs. 1A-1B point to the edge part 11A (edge portion) and the metal foil 11B (main portion).).
Response to Arguments
Applicant's arguments filed 04/27/2026 regarding the rejections of claims 5 and 14 under 35 U.S.C. §112(d) have been fully considered but they are not persuasive. Specifically, Applicant argues that the language of claims 1 and 11 do not preclude the presence of additional intervening layers between the main portion of the second metal layer and the semiconductor chip and that this interpretation is supported by the specification.
Regarding the language of the claims, Examiner argues that claims 1 and 11 do in fact preclude the presence of additional intervening layers by way of each claim’s wording as well as the final structure(s) disclosed. Specifically, both claims explicitly use the terms “a cover insulating layer” and “the cover insulating layer” (emphasis added), which only indicate the formation of one cover insulating layer. Additionally, each claim discloses “forming a cover insulating layer on an upper surface of the main portion of the second metal layer; and disposing a semiconductor chip on an upper surface of the cover insulating layer”, or in other words a specifically layered structure(s) wherein said cover insulating layer must be in direct contact with the underlying second metal layer and the overlying semiconductor chip. In light of this, it is interpreted that each claim discloses a final structure that only allows for the formation of a single cover insulating layer. Regarding Applicant’s reliance on the specification of the claimed invention, it is noted that the features upon which applicant relies (i.e., the presence of additional intervening layers) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Thus, Applicant’s argument(s) are considered unpersuasive and fail to overcome the rejections of claims 5 and 14 respectively.
Applicant’s arguments, see Remarks, filed 04/27/2026, with respect to the rejection(s) of claim(s) 1-15 under 35 U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kaneko (PGPub No. 20130143062) in further view of Lee and/or Lee2.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST.
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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