Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claims 5 and 14 are rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Specifically, claim 5’s disclosure of “disposing the semiconductor chip such that a number of the cover insulating layer is one between the main portion of the second metal layer and the semiconductor chip” (emphasis added) is already disclosed in claim 1 upon which it depends: claim 1 discloses “forming a cover insulating layer on an upper surface of the main portion of the second metal layer; and disposing a semiconductor chip on an upper surface of the cover insulating layer” (emphasis added). Claim 14 is rejected for the same subject matter and reasoning, but in relation to its dependence on claim 11 (by way of claims 12 and 13). Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
Claim(s) 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Wolter (PGPub No. 20200068711) in further view of Lee (US Patent No. 10438884).
Regarding claim 1, Wolter teaches a method of manufacturing a semiconductor package, the method comprising: applying a cutter to a boundary between a main portion of a second metal layer and an edge portion of the second metal layer that surrounds the main portion (Fig. 5B and [0056] point to a semiconductor package 501 comprising a metal foil layer 506 (second metal layer), positioned on a carrier layer 502, that is cut to form cuts/vias and/or trenches 507.), the second metal layer being on an upper surface of a first metal layer disposed on an upper surface of a carrier substrate (Fig. 2A points to an alternative structure 201b comprising a carrier layer 202 made up of a prepreg layer 210 (carrier substrate) and a metal carrier foil layer 212 (first metal layer), and a metal layer 206 (second metal layer).); and peeling the edge portion of the second metal layer from the first metal layer (Fig. 3E and [0043] point to another alternative embodiment 307 where the carrier layer 302 (first metal layer) is removed from the metal foil layer 306 (second metal layer) using a peeling off step. It is thus considered obvious that a similar process could be performed on the structure shown in Fig. 5B, specifically where the edge portions of the metal foil layer 506 (second metal layer) are removed from the carrier layer 502 (first metal layer), in order to remove unnecessary material while still retaining a carrier to support further processing.).
Wolter fails to teach forming a cover insulating layer on an upper surface of the main portion of the second metal layer; and disposing a semiconductor chip on an upper surface of the cover insulating layer.
Lee teaches forming a cover insulating layer on an upper surface of the main portion of the second metal layer (Fig. 18 points to a semiconductor package comprising an interposer 210 including an insulating layer (cover insulating layer) and a unit pattern 110a (second metal layer).); and disposing a semiconductor chip on an upper surface of the cover insulating layer (Fig. 19 points to semiconductor chip(s) 220 formed on the interposer(s) 210 (cover insulating layer).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Wolter and Lee, such that a cover insulating layer is formed between the existing second metal layer/carrier substrate and newly formed semiconductor chip in order to create a detachable carrier that is electrically separated from the semiconductor chip yet can still provide a physical base that allows for further manipulation of said chip and/or other fabrication processes.
Regarding claim 2, Wolter teaches wherein the first metal layer is not divided into a plurality of portions by the cutter (Fig. 5B and [0056] point to a semiconductor package 501 comprising the metal foil layer 506 (second metal layer), positioned on a carrier layer 502 (first metal layer), that is cut to form cuts/vias and/or trenches 507.).
Regarding claim 3, Wolter teaches wherein the cutter comprises a laser and the applying includes irradiating the laser onto the boundary ([0056] points to performing the cutting of the metal layer 506 by laser.).
Regarding claim 4, Wolter teaches wherein the peeling includes pulling the edge portion of the second metal layer from the first metal layer or applying a force to the edge portion of the second metal layer in a direction different from a direction facing the first metal layer (Fig. 3E and [0043] point to another alternative embodiment 307 where the carrier layer 302 (first metal layer) is removed from the metal foil layer 306 (second metal layer) using a peeling off step. It is thus considered obvious that a similar process could be performed on the structure shown in Fig. 5B, specifically where the edge portions of the metal foil layer 506 (second metal layer) are removed from the carrier layer 502 (first metal layer), in order to remove unnecessary material while still retaining a carrier to support further processing.).
Regarding claim 5, Lee teaches wherein the disposing of the semiconductor chip includes disposing the semiconductor chip such that a number of the cover insulating layer is one between the main portion of the second metal layer and the semiconductor chip (Fig. 19 points to semiconductor chip(s) 220 formed on the interposer(s) 210 (cover insulating layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wolter and Lee, such that a cover insulating layer is formed between the existing second metal layer/carrier substrate and newly formed semiconductor chip in order to create a detachable carrier that is electrically separated from the semiconductor chip yet can still provide a physical base that allows for further manipulation of said chip and/or other fabrication processes.
Regarding claim 6, Lee teaches wherein the disposing of the semiconductor chip includes disposing the semiconductor chip such that a first surface of the semiconductor chip is in contact with the cover insulating layer (Fig. 19 points to a semiconductor package using a carrier substrate comprising semiconductor chip(s) 220 formed such that one surface (first surface) is on the interposer(s) 210 (cover insulating layer).), and a second surface of the semiconductor chip opposite to a first surface of the semiconductor chip that is electrically connected to a redistribution layer (Fig. 7 points to an alternative embodiment comprising semiconductor chips 221’, 222’, and 223’ which are each formed such that one surface (second surface) is in contact with an organic interposer 210’ (redistribution layer). It is considered obvious that one of ordinary skill in the art could combine the structures taught in Figs. 19 and 7 respectively, such that one side of a semiconductor chip (first surface) is first attached to the interposer 210 (cover insulating layer) of a carrier substrate in order to create a temporary base to provide physical stability, followed by connecting the opposite side of the semiconductor chip (second surface) to the organic interposer 210’ (redistribution layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wolter and Lee, such that a redistribution layer is further formed and attached to the semiconductor chip and away from the cover insulating layer/carrier substrate in order to create multiple electrical pathways that connect to the semiconductor chip, a process which would be perfected by the use of the cover insulating layer/carrier substrate as a temporary base from which the semiconductor chip could be properly lined up with the redistribution layer.
Regarding claim 7, Wolter teaches further comprising, after the semiconductor chip is disposed, detaching the carrier substrate and the first metal layer from the main portion of the second metal layer and the cover insulating layer (Figs. 5C-5D point to the formation of a component 517 (semiconductor chip), followed by the removal of the carrier layer 502 (carrier substrate; first metal layer).).
Regarding claim 8, Wolter teaches wherein the carrier substrate contains a prepreg (Fig. 2A points to an alternative structure 201b comprising the prepreg layer 210 (carrier substrate).).
Regarding claim 9, Wolter teaches wherein each of the first metal layer and the second metal layer is a single metal layer containing copper ([0024] points to the metal carrier foil layer 212 (first metal layer) being made of, for example, Cu, and the metal layer 206 (second metal layer) being a Cu foil.).
Claim(s) 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over Wolter et al. in further view of Lee2 (PGPub No. 20060071303).
Regarding claim 10, Lee2 teaches wherein a thickness of the second metal layer is greater than 1 µm and less than 10 µm (Fig. 5C and [0044] point to a manufacturing process for a film substrate of semiconductor packages comprising a copper metal layer 23 (second metal layer) with a thickness t2 which is about 1-5 µm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wolter et al. and Lee2, such that the second metal layer is provided an adequate thickness in order to obtain fine line widths and gaps following a machining/cutting process.
Regarding claim 11, Wolter teaches a method of manufacturing a semiconductor package, the method comprising: exposing a portion of a first metal layer by removing an edge portion of a second metal layer that surrounds a main portion of the second metal layer (Fig. 5B and [0056] point to a semiconductor package 501 comprising a metal foil layer 506 (second metal layer), positioned on a carrier layer 502, that is cut to form cuts/vias and/or trenches 507.), the second metal layer being on an upper surface of the first metal layer disposed on an upper surface of a carrier substrate (Fig. 2A points to an alternative structure 201b comprising a carrier layer 202 made up of a prepreg layer 210 (carrier substrate) and a metal carrier foil layer 212 (first metal layer), and a metal layer 206 (second metal layer).).
Wolter fails to teach forming a cover insulating layer on an upper surface of the main portion of the second metal layer; and disposing a semiconductor chip on an upper surface of the cover insulating layer, wherein a thickness of the second metal layer is greater than 1 pm and less than 10 pm.
Lee teaches forming a cover insulating layer on an upper surface of the main portion of the second metal layer (Fig. 18 points to a semiconductor package comprising an interposer 210 including an insulating layer (cover insulating layer) and a unit pattern 110a (second metal layer).); and disposing a semiconductor chip on an upper surface of the cover insulating layer (Fig. 19 points to semiconductor chip(s) 220 formed on the interposer(s) 210 (cover insulating layer).). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Wolter and Lee, such that a cover insulating layer is formed between the existing second metal layer/carrier substrate and newly formed semiconductor chip in order to create a detachable carrier that is electrically separated from the semiconductor chip yet can still provide a physical base that allows for further manipulation of said chip and/or other fabrication processes.
Wolter et al. still fails to teach wherein a thickness of the second metal layer is greater than 1 µm and less than 10 µm.
Lee2 teaches wherein a thickness of the second metal layer is greater than 1 µm and less than 10 µm (Fig. 5C and [0044] point to a manufacturing process for a film substrate of semiconductor packages comprising a copper metal layer 23 (second metal layer) with a thickness t2 which is about 1-5 µm. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wolter et al. and Lee2, such that the second metal layer is provided an adequate thickness in order to obtain fine line widths and gaps following a machining/cutting process.
Regarding claim 12, Wolter teaches wherein each of the first metal layer and the second metal layer is a single metal layer containing copper ([0024] points to the metal carrier foil layer 212 (first metal layer) being made of, for example, Cu, and the metal layer 206 (second metal layer) being a Cu foil.).
Regarding claim 13, Wolter teaches wherein the carrier substrate contains a prepreg (Fig. 2A points to an alternative structure 201b comprising the prepreg layer 210 (carrier substrate).).
Regarding claim 14, Lee teaches wherein the disposing of the semiconductor chip includes disposing the semiconductor chip such that a number of the cover insulating layer is one between the main portion of the second metal layer and the semiconductor chip (Fig. 19 points to semiconductor chip(s) 220 formed on the interposer(s) 210 (cover insulating layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wolter and Lee, such that a cover insulating layer is formed between the existing second metal layer/carrier substrate and newly formed semiconductor chip in order to create a detachable carrier that is electrically separated from the semiconductor chip yet can still provide a physical base that allows for further manipulation of said chip and/or other fabrication processes.
Regarding claim 15, Lee teaches wherein the disposing of the semiconductor chip includes disposing the semiconductor chip such that a first surface of the semiconductor chip is in contact with the cover insulating layer (Fig. 19 points to a semiconductor package using a carrier substrate comprising semiconductor chip(s) 220 formed such that one surface (first surface) is on the interposer(s) 210 (cover insulating layer).), and a second surface of the semiconductor chip opposite to a first surface of the semiconductor chip that is electrically connected to a redistribution layer (Fig. 7 points to an alternative embodiment comprising semiconductor chips 221’, 222’, and 223’ which are each formed such that one surface (second surface) is in contact with an organic interposer 210’ (redistribution layer). It is considered obvious that one of ordinary skill in the art could combine the structures taught in Figs. 19 and 7 respectively, such that one side of a semiconductor chip (first surface) is first attached to the interposer 210 (cover insulating layer) of a carrier substrate in order to create a temporary base to provide physical stability, followed by connecting the opposite side of the semiconductor chip (second surface) to the organic interposer 210’ (redistribution layer).). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Wolter and Lee, such that a redistribution layer is further formed and attached to the semiconductor chip and away from the cover insulating layer/carrier substrate in order to create multiple electrical pathways that connect to the semiconductor chip, a process which would be perfected by the use of the cover insulating layer/carrier substrate as a temporary base from which the semiconductor chip could be properly lined up with the redistribution layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Patrick L Cullen whose telephone number is (703)756-1221. The examiner can normally be reached Monday - Friday, 8:30AM - 5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899