DETAILED ACTION
Claims 1-20 are presented for examination. Claims 13-20 are withdrawn from consideration.
Applicant's election with traverse of group 1 in the reply filed on 04/23/2026 is acknowledged. The traversal is on the ground(s) that no undue burden would exist for the examiner because a search for one invention would yield references for the others. This is not found persuasive because while there is certainly overlap in scope between the two inventions, specific and unique searches would be required for each that would not be encompassed by the others, thus leading to an undue burden on the examiner.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-12 are rejected under 35 U.S.C. 101 because the claimed invention recites a judicial exception, is directed to that judicial exception, an abstract idea, as it has not been integrated into practical application and the claims further do not recite significantly more than the judicial exception. Examiner has evaluated the claims under the framework provided in the 2019 Patent Eligibility Guidance published in the Federal Register 01/07/2019 and has provided such analysis below.
Step 1: Claims 1-12 are directed to apparatuses and fall within the statutory category of machines.
Therefore, “Are the claims to a process, machine, manufacture or composition of matter?” Yes.
In order to evaluate the Step 2A inquiry “Is the claim directed to a law of nature, a natural phenomenon or an abstract idea?” we must determine, at Step 2A Prong 1, whether the claim recites a law of nature, a natural phenomenon or an abstract idea and further whether the claim recites additional elements that integrate the judicial exception into a practical application.
Step 2A Prong 1:
Claim 1: The limitations of “…coupling the IRQs…to the plurality of processors” and “…selects one of the plurality of processors to process the IRQs…based on information…,” as drafted, is a process that, but for the recitation of generic computing components, under its broadest reasonable interpretation, covers performance of the limitation in the mind. For example, a person can examine data and from it select a particular element best suited to perform a task.
Therefore, Yes, claim 1 recites judicial exceptions.
The claims have been identified to recite judicial exceptions, Step 2A Prong 2 will evaluate whether the claims are directed to the judicial exception.
Step 2A Prong 2:
Claim 1: The judicial exception is not integrated into a practical application. In particular, the claims recite the following additional elements – “a smart interrupt controller,” “a plurality of peripherals,” and “a plurality of storage registers,” which are merely recitations of generic computing components and functions (see MPEP § 2106.05(b)) which do not integrate a judicial exception into practical application. Further, claim 1 recites the following additional elements – “storing information about the plurality of peripherals and the plurality of processors” which is merely a recitation of insignificant pre-solution data gathering activity (see MPEP § 2106.05(g)), which do not integrate a judicial exception into practical application and will also be addressed below in Step 2B as also being Well-Understood, Routine and Conventional.
Therefore, “Do the claims recite additional elements that integrate the judicial exception into a practical application? No, these additional elements do not integrate the abstract idea into a practical application and they do not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
After having evaluating the inquires set forth in Steps 2A Prong 1 and 2, it has been concluded that claim 1 not only recites a judicial exception but that the claim is directed to the judicial exception as the judicial exception has not been integrated into practical application.
Step 2B:
Claim 1: The claims do not include additional elements, alone or in combination, that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements amount to no more than generic computing components which do not amount to significantly more than the abstract idea. Further, to the extent that “storing information about the plurality of peripherals and the plurality of processors” is a positively recited step of storing data, this would be insignificant extra-solution data gathering which is also Well-Understood, Routine and Conventional (see MPEP § 2106.05(d)(II) “The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity. iv. Storing and retrieving information in memory,”).
Therefore, “Do the claims recite additional elements that amount to significantly more than the judicial exception? No, these additional elements, alone or in combination, do not amount to significantly more than the judicial exception.
Having concluded analysis within the provided framework, Claim 1 does not recite patent eligible subject matter under 35 U.S.C. § 101.
Claims 2-12 are rejected under 35 U.S.C. 101 as non-statutory for at least the reasons stated above. The claims are dependent on Claim 1, but do not add any feature or subject matter that would solve the non-statutory deficiencies of Claim 1. Specifically, each claim simply clarifies details of the various claimed elements or adds further mental processes that are similar to the steps in claim 1. Claims 2-12 do not add any steps or elements, when considered both individually and as a combination, that would convert claim 1 into patent-eligible subject matter.
Therefore, claims 1-12 do not recite patent eligible subject matter under 35 U.S.C. § 101.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over de Cesare et al (U.S. Pat. Pub. No. 2012/0144172 A1, hereinafter de Cesare) in view of Horiuchi et al (U.S. Pat. Pub. No. 2002/0169902 A1, hereinafter Horiuchi).
As per claim 1, de Cesare teaches the limitations substantially as claimed, including an apparatus, the apparatus comprising:
a smart interrupt controller (SIC) adapted for coupling to a plurality of peripherals for receiving interrupt requests (IRQs) therefrom and to a plurality of processors for directing the IRQs to selected ones of the plurality of processors (Paragraph [0028]; Figure 1 shows the plurality of peripherals all providing interrupt requests to the interrupt controller), the SIC comprising:
a plurality of storage registers for storing information about the plurality of processors (Paragraph [0027]); and
interrupt routing control logic adapted for coupling the IRQs from the plurality of peripherals to the plurality of processors (Paragraph [0028]; Figure 2);
wherein the SIC selects ones of the plurality of processors to process the IRQs from the plurality of peripherals based on information about the plurality of peripherals and the plurality of processors (Paragraph [0028]).
de Cesare does not expressly teach that the registers are for storing information about the plurality of peripherals.
However, Horiuchi teaches that the registers are for storing information about the plurality of peripherals (Paragraph [0039]).
It would have been obvious to one of ordinary skill in the art at the time of the filing of the application to combine the teachings of Horiuchi with those of de Cesare in order to allow for de Cesare’s apparatus to have access to a wider array of information on its various elements, which could lead to making more informed decisions on routing, thereby potentially leading to more approval from users.
As per claim 2, de Cesare teaches that the plurality of storage registers are selected from the group consisting of processor load registers for storing operating load information from each of the plurality of processors, processor power state registers for storing whether each of the plurality of processors is in an enabled mode or a disabled mode, IRQ number registers for storing interrupt numbers of each of the plurality of peripherals, and IRQ affinity registers for storing affinities of each one of the plurality of peripherals to respective ones of the plurality of processors (Paragraph [0027], “PState”) wherein when an IRQ is received from a peripheral the SIC will route the IRQ to an affined processor or to another one of the plurality of processors when the affined processor is not available (Paragraph [0006] teaches routing to an affined processor).
As per claim 3, de Cesare teaches that the affined processor is not available when its operating load is greater than a load threshold (Paragraph [0046] teaches processor availability based on workload).
As per claim 4, de Cesare teaches that the affined processor is not available when its power state is in a disabled mode (Paragraph [0030]).
As per claim 5, de Cesare teaches that the plurality of storage registers further comprises IRQ priority registers for determining in what order the IRQs will be serviced when more than one IRQ is received by the SIC at substantially the same time (Paragraph [0052]).
As per claim 6, de Cesare teaches that the plurality of storage registers further comprises mode select registers for determining operational characteristics of the SIC for each of the plurality of processors (Paragraph [0027] teaches states, where a state correlates to a mode).
As per claim 7, de Cesare teaches that the operational characteristics of the SIC are selected from the group consisting of manual selection of a processor to service the IRQ, automatic selection of the affined processor or another active processor to service the IRQ, automatic selection of the affined processor or a least loaded another active processor to service the IRQ, and automatic selection of a least loaded processor to service the IRQ (Paragraph [0006] teaches routing to an affined processor).
As per claim 8, de Cesare teaches that the manual selection of the processor to service the IRQ is done with external interrupt control (Paragraph [0006], the examiner would point out that claim 7 does not require manual selection of the processor, and in the case where automatic selection occurs this claim would be rejected for the same reasons as claim 7 with no further limitation).
As per claim 9, de Cesare teaches external interrupt control for routing the IRQs through the SIC (Figure 1).
As per claim 12, de Cesare teaches that IRQ routing to an affined processor is dynamically configurable (Paragraph [0006]).
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over de Cesare and Horiuchi, as applied to claim 1 above, and further in view of Shah et al (U.S. Pat. No. 5551044, hereinafter Shah).
As per claim 10, de Cesare and Horiuchi do not expressly teach that the IRQs from the plurality of peripherals are asynchronous.
However, Shah teaches that that the IRQs from the plurality of peripherals are asynchronous (Col. 7, Lines 1-4).
It would have been obvious to one of ordinary skill in the art at the time of the filing of the application to combine the teachings of Shah with those of de Cesare and Horiuchi in order to allow for de Cesare’s and Horiuchi’s apparatus to effectively process interrupt signals in an expected and understandable order, which could increase the reliability of the apparatus.
As per claim 11, de Cesare and Horiuchi do not expressly teach that IRQs raised by software are synchronous.
However, Shah teaches that IRQs raised by software are synchronous (Col. 7, Lines 1-4).
It would have been obvious to one of ordinary skill in the art at the time of the filing of the application to combine the teachings of Shah with those of de Cesare and Horiuchi in order to allow for de Cesare’s and Horiuchi’s apparatus to effectively process interrupt signals in an expected and understandable order, which could increase the reliability of the apparatus.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Gregory Kessler whose telephone number is (571)270-7762. The examiner can normally be reached M-Th 8:30 - 5, Alternate Fridays 8:30-4.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bradley Teets can be reached at (571)272-3338. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GREGORY A KESSLER/Primary Examiner, Art Unit 2197
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