DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 06/01/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
Sections [0061] on page 12; [0068] on page 14; and [0146] on page 32 recite “the present disclosure is limited thereto” which should be read “the present disclosure is not limited thereto”.
Section [0093] on page 20 recites “the first and second interlayer insulating films 140 and 240” which should be “the first and second interlayer insulating films 130 and 230” to maintain consistency with the rest of the specification and the drawings.
Section [0149] on page 32 recites “the sixth and ninth wirings 322 and 229” which should be “the sixth and ninth wirings 322 and 228” to maintain consistency with the rest of the specification and the drawings.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4 - 11, and 18 - 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Hashiguchi et al. (US20210217797A1; hereinafter Hashiguchi).
Regarding Claim 1, Hashiguchi discloses an image sensor (solid-state imaging device, [0008]) comprising:
a first substrate (110A, FIG. 7E reproduced below, [0221]) comprising a first surface (back side surface, [0223]) and a second surface (front side surface, [0223]) opposite to the first surface;
a first wiring structure provided on the second surface (front side surface) of the first substrate (110A), the first wiring structure comprising a first wiring (multi-layered wiring layer 105) and a first inter-wiring insulating film (insulating film 103), (FIG. 7E, [0225]);
a second substrate (110B) comprising a third surface (front side surface of 110B) facing the second surface of the first substrate (front side surface of 110A), and a fourth surface (back side surface of 110B) opposite to the third surface, [0223];
a second wiring structure provided on the third surface (frontside of 110B) of the second substrate (110B), the second wiring structure comprising a second wiring (multilayered wiring layer 125) and a second inter-wiring insulating film (insulating film 123), (FIG. 7E, [0228]);
a via trench (through hole for TSV 157a) penetrating the first substrate (110A) and the first wiring structure (103 and 105, FIG. 7E, [0229]);
a through via structure (TSV 157a) extending along the via trench and connected to the second wiring (125); (FIG. 7E, [0235]) and
a pad pattern (151) provided on the through via (TSV157a) and filling at least a portion of the via trench, (FIG. 7E, [0333]).
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Hashiguchi: FIG. 7E
Regarding Claim 4, Hashiguchi discloses the image sensor of claim 1, further comprising pixel isolation patterns (the pixel separation unit 20030 includes a groove 20031, a fixed-charge film 20032, and an insulating film 20033, FIG. 27A, [0556]) provided in the first substrate (20018, [0550]), extending from the second surface (front side surface with wiring) of the first substrate (20018) to the first surface (back side surface) of the first substrate (FIG. 27A, [0557]), and defining a plurality of unit pixels (20010, FIG. 27A, [0545]),
wherein the pixel isolation patterns (20030) do not overlap the through via structure (157a) in a direction from the second surface (frontside surface) of the first substrate (110A) to the first surface (backside surface) of the first substrate. Hashiguchi (FIG. 2A, [0259]) discloses the substrate 110A is provided with the pixel unit 206 in the middle of the chip and the coupling structures 201 included in the I/O unit are disposed around the pixel unit 206 along the periphery of the chip, indicating the pixel isolation patterns are located in the pixel unit 206 and do not overlap the through via structure.
Regarding Claim 5, Hashiguchi discloses the image sensor of claim 1, further comprising:
isolation trenches (groove 20031 located in pixel unit 206, FIG. 27A) provided on at least one side of the via trench (TSV 157a located in coupling structures 201, FIG. 7E) and extending from the first surface (backside) of the first substrate (20018, [0557]);
and insulating patterns filling the isolation trenches (fixed charge film 20032 and insulating film 20033, FIG. 27A, [0556])
Regarding Claim 6, Hashiguchi discloses the image sensor of claim 5, wherein the isolation trenches (groove 20031) extend from the first surface (back side surface) of the first substrate (20018) to the second surface (front side surface) of the first substrate, (FIG. 27A, [0557], [0558]).
Regarding Claim 7, Hashiguchi discloses the image sensor of claim 1, wherein the second inter-wiring insulating film (123, FIG. 3A) comprises a plurality of wirings (multi-layered wiring layer 125, FIG. 3A), and wherein the second wiring (topmost wiring of 125, FIG. 3A, [0228]) is closest to the second surface (frontside surface) of the first substrate (110A) from among the second wiring and the plurality of wirings of the second inter-wiring insulating film (123).
Regarding Claim 8, Hashiguchi discloses the image sensor of claim 1, wherein the second wiring structure (125 and 123) comprises a third wiring (wirings in layer 125 excluding the topmost wire), and
wherein the image sensor further comprises: a connecting trench (TSV 157, FIG. 6C) penetrating the first substrate (110A) and the first inter-wiring insulating film (105) such that at least a portion of the first wiring and at least a portion of the third wiring are exposed [0235], and
a connecting structure (conductive fill in TSV 157) extending along the connecting trench (TSV 157) and connecting the first wiring (105) and the third wiring (125), [0235].
Regarding Claim 9, Hashiguchi discloses the image sensor of claim 8, further comprising a filling insulating film (a film of an insulating material may be formed on the inner walls of the through holes, [0248]) provided on the connecting structure (conductive fill in TSV 157) and filling the connecting trench (TSV 157).
Regarding Claim 10, Hashiguchi discloses the image sensor of claim 8, wherein the connecting trench comprises (TSV 157):
a first connecting trench exposing at least a portion of the first wiring (a first through hole reaching the coupling surface of the wiring line in the multi-layered wiring layer 105 of the first substrate 110A, FIG. 6C, [0235]), and
a second connecting trench spaced apart from the first connecting trench and exposing at least a portion of the third wiring (a second through hole reaching the coupling surface of the wiring line in the multi-layered wiring layer 125 of the second substrate 110B, FIG. 6C, [0235]).
Regarding Claim 11, Hashiguchi discloses the image sensor of claim 1, wherein the first wiring structure (105) further comprises first bonding patterns connected to the first wiring (electrodes formed on bonding surfaces of the first substrate 110A, [0244]),
wherein the second wiring structure further comprises second bonding patterns connected to the second wiring (electrodes formed on bonding surfaces of the second substrate 110B, [0244]), and
wherein the first bonding patterns and the second bonding patterns are connected (electrode junction structure electrically couples the respective wiring lines to each other which are provided in the substrates, [0244]).
Regarding Claim 18, Hashiguchi discloses an image sensor (solid-state imaging device, [0008]) comprising a pixel array area (pixel unit 206, FIG. 2A, [0259]), a light-blocking area around the pixel array area (light shielding film 20014, FIG. 27A, [0552]), and pad regions around the pixel array area (coupling structure 201, FIG. 2A, [0259]), the image sensor comprising:
a first substrate (110A) comprising a first surface (back side surface) and a second surface (front side surface) opposite to the first surface, (FIG. 7E, [0221], [0223]);
pixel isolation patterns (the pixel separation unit 20030 includes a groove 20031, a fixed-charge film 20032, and an insulating film 20033, FIG. 27A, [0556]) provided in the first substrate (20018, [0550]), extending from the second surface (front side surface with wiring) of the first substrate (20018) to the first surface (back side surface) of the first substrate (FIG. 27A, [0557]), and defining a plurality of unit pixels (20010, FIG. 27A, [0545]),
a plurality of microlenses provided on the first surface of the first substrate (microlens array ML 113 formed on the backside surface of 110A, FIG. 7E, [0238]) and respectively corresponding to the plurality of unit pixels (micro lens array ML113 is configured that microlens corresponds to respective pixels, FIG. 7E, [0239]);
a first wiring structure provided on the second surface (front side surface) of the first substrate (110A), the first wiring structure comprising a first wiring (multi-layered wiring layer 105) and a first inter-wiring insulating film (insulating film 103), (FIG. 7E, [0225]);
a second substrate (110B) comprising a third surface (front side surface of 110B) facing the second surface of the first substrate (front side surface of 110A), and a fourth surface (back side surface of 110B) opposite to the third surface, [0223];
a second wiring structure provided on the third surface (frontside of 110B) of the second substrate (110B), the second wiring structure comprising a second wiring (multilayered wiring layer 125) and a second inter-wiring insulating film (insulating film 123), (FIG. 7E, [0228]);
a via trench (through hole for TSV 157a) provided in the pad regions (coupling structure region 201, [0259]) and penetrating the first substrate (110A) and the first wiring structure (105 and 103), in the pad regions such that at least a portion of the second wiring is exposed ([0235], FIG. 7E);
a through via structure (TSV 157a) extending along the via trench [0235];
a pad pattern (151) provided in the via trench (through hole for TSV 157a) and on through via structure (TSV157a), FIG. 7E, [0332]; and
insulating patterns provided in the pad regions (109) spaced apart from the through via structure (TSV 157), and extending from the first surface of the first substrate (backside surface of first substrate 110A, FIG. 6A, [0238]).
Regarding Claim 19, Hashiguchi discloses the image sensor of claim 18, further comprising:
a contact pattern provided in the light-blocking area (light-shielding film 20014, [0551]), and extending from the first surface (backside) of the first substrate (20018), the contact pattern (20014) configured to be connected to the pixel isolation patterns (pixel separation unit 20030, [0552]);
a connecting region (coupling structure 201) around the pixel array area (pixel unit 206, FIG. 2A, [0259]); and
a connecting structure (TSV 157) in the connecting region (coupling structure 201) and penetrating the first substrate (110A) and the first wiring structure (103 and 105), connecting the first wiring (105) and the second wiring (125) (FIG. 6C, [0235]).
Regarding Claim 20, Hashiguchi discloses the image sensor of claim 18, further comprising: color filters (CF layer 111) provide on the first surface (backside surface) of the first substrate (110A, [0238]) in the pixel array area [0240]; and organic photoelectric conversion layers provided on the color filters [0224].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 3, and 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Hashiguchi in view of Park et al. (US20200350354A1; hereinafter Park).
Regarding Claim 2, Hashiguchi discloses the image sensor of claim 1.
Hashiguchi does not disclose “wherein the via trench comprises: a first via trench having a first width, and a second via trench, on the first via trench, having a second width greater than the first width.”
In a similar art, Park discloses a semiconductor device [0005],
wherein the via trench comprises:
a first via trench having a first width (first trench T1, FIG. 2 reproduced below, [0029]);
a second via trench (second trench T2, FIG. 2, [0033]), on the first via trench (T1), having a second width greater than the first width, [0058]
Park discloses that a device as taught prevents cracks from emerging in the device [0005]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to add Park’s disclosure to Hashiguchi’s image sensor to prevent crack formation and damage to the device as disclosed by Park [0005].
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Park: FIG. 2
Regarding Claim 3, The combination of Hashiguchi and Park disclose the image sensor of claim 2.
Park further discloses: wherein the second via trench (T2) is provided in the first substrate (upper substrate 210), FIG. 2, [0033].
Park discloses that a device as taught prevents cracks from emerging in the device [0005]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to add Park’s disclosure to Hashiguchi’s image sensor to prevent crack formation and damage to the device as disclosed by Park [0005].
Regarding Claim 12, Hashiguchi discloses an image sensor (solid-state imaging device, [0008]) comprising:
a first substrate (110A) comprising a first surface (back side surface) and a second surface (front side surface) opposite to the first surface, (FIG. 7E, [0221], [0223]);
a first wiring structure provided on the second surface (front side surface) of the first substrate (110A), the first wiring structure comprising a first wiring (multi-layered wiring layer 105) and a first inter-wiring insulating film (insulating film 103), (FIG. 7E, [0225]);
a second substrate (110B) comprising a third surface (front side surface of 110B) facing the second surface of the first substrate (front side surface of 110A), and a fourth surface (back side surface of 110B) opposite to the third surface, [0223];
a second wiring structure provided on the third surface (frontside of 110B) of the second substrate (110B), the second wiring structure comprising a second wiring (multilayered wiring layer 125) and a second inter-wiring insulating film (insulating film 123), (FIG. 7E, [0228]);
a pad pattern (151) provided on the through via (TSV157a) and filling at least a portion of the via trench, FIG. 7E, [0332].
Hashiguchi does not disclose “a pad pattern comprising: a first portion provided in the first wiring structure and the first substrate, and a second portion provided in the first substrate on the first portion, the second portion having a width greater than a width of the first portion; and a through via structure extending from the first surface of the first substrate along at least a portion of the pad pattern and connected to the second wiring.”
In a similar art, Park discloses a semiconductor device [0005],
a pad pattern (264, FIG. 15, [0036]) comprising:
a first portion (bottom portion of 264 in T2, [0057]) provided in the first wiring structure (220, FIG. 15, [0036]) and the first substrate (210), (FIG. 15, [0033]) and
a second portion (upper portion of 264 in T2) provided in the first substrate (220) on the first portion (bottom portion of 264 in T2), the second portion having a width greater than a width of the first portion (FIG. 15, [0057]); and
a through via structure (250 with via core 254, FIG.1, [0035]) extending from the first surface of the first substrate (upper surface of upper substrate 210, [0034]) along at least a portion of the pad pattern (the pad pattern 264 may be materially continuous with the via core 254, [0036]) and connected to the second wiring (120, FIG.15, [0068]).
Park discloses that a device as taught prevents cracks from emerging in the device [0005]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to add Park’s disclosure to Hashiguchi’s image sensor to prevent crack formation and damage to the device as disclosed by Park [0005].
Regarding Claim 13, The combination of Hashiguchi and Park disclose the image sensor of claim 12.
Park further discloses: wherein the through via structure (250 with via core 254) extends along a bottom surface and sides of the pad pattern (the pad pattern 264 may be materially continuous with the via core 254, [0036], FIG. 15).
Park discloses that a device as taught prevents cracks from emerging in the device [0005]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to add Park’s disclosure to Hashiguchi’s image sensor to prevent crack formation and damage to the device as disclosed by Park [0005].
Regarding Claim 14, The combination of Hashiguchi and Park disclose the image sensor of claim 12.
Park further discloses: wherein the second wiring structure (lower circuit 120 and insulating layer 125) further comprises a third wiring (the bottommost interconnect 121, FIG. 2, [0022]), and
wherein the image sensor (semiconductor device 10) further comprises a connecting structure (250) extending from the first surface of the first substrate (upper surface of the upper substrate 210, [0034]) and connecting the first wiring (221) and the third wiring (bottommost 121, FIG. 15, [0058]).
Park discloses that a device as taught prevents cracks from emerging in the device [0005]. Therefore, it would have been obvious to one having an ordinary skill in the art before the effective filing date of the claimed invention to add Park’s disclosure to Hashiguchi’s image sensor to prevent crack formation and damage to the device as disclosed by Park [0005].
Regarding Claim 15, The combination of Hashiguchi and Park disclose the image sensor of claim 12.
Hashiguchi further discloses: further comprising: pixel isolation patterns (the pixel separation unit 20030 includes a groove 20031, a fixed-charge film 20032, and an insulating film 20033, FIG. 27A, [0556]) provided in the first substrate (20018, [0550]), extending from the second surface (front side surface with wiring) of the first substrate (20018) to the first surface (backside surface) of the first substrate (groove 20031 extends through the first substrate, FIG. 27A, [0557]), and defining a plurality of unit pixels (20010, FIG. 27A, [0545]),
wherein the pixel isolation patterns (20030) do not overlap the through via structure (157a) in a direction from the second surface (frontside surface) of the first substrate (110A) to the first surface (backside surface) of the first substrate. Hashiguchi (FIG. 2A, [0259]) discloses the substrate 110A is provided with the pixel unit 206 in the middle of the chip and the coupling structures 201 included in the I/O unit are disposed around the pixel unit 206, indicating the pixel isolation patterns 20030 do not overlap the through via structure 157a.
Regarding Claim 16, The combination of Hashiguchi and Park disclose the image sensor of claim 12.
Hashiguchi further discloses: wherein the first wiring structure (105) further comprises first bonding patterns connected to the first wiring (electrodes formed on bonding surfaces of the first substrate 110A, [0244]),
wherein the second wiring structure further comprises second bonding patterns connected to the second wiring (electrodes formed on bonding surfaces of the second substrate 110B, [0244]), and
wherein the first bonding patterns and the second bonding patterns are connected (electrode junction structure electrically couples the respective wiring lines to each other which are provided in the substrates, [0244]).
Regarding Claim 17, The combination of Hashiguchi and Park disclose the image sensor of claim 12.
Hashiguchi further discloses: further comprising insulating patterns (fixed charge film 20032 and insulating film 20033) spaced apart from the through via structure (TSV 157, [0259]), and extending from the first surface of the first substrate (backside surface of first substrate 20018, FIG. 27A, [0556]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Krishna Palaniswamy whose telephone number is (571)272-6239. The examiner can normally be reached Monday - Friday 8:30AM - 5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
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supervisor, Brent Fairbanks can be reached on 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KRISHNA J PALANISWAMY/Examiner, Art Unit 2899
/WILLIAM A HARRISTON/Primary Examiner, Art Unit 2899