DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 13 is objected to because of the following informalities:
In claim 13, line 2, substitute “the” with --a-- before “position.”
In claim 13, line 3, substitute “first” with --second-- before “width at the second position.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-14 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US Pub. 2024/0203879; hereinafter “Xie”).
Regarding Claim 1, Xie discloses an apparatus, comprising: a transistor comprising one or more semiconductor structures 210 (nanosheet; page 2, paragraph 28) extending between a source structure 220 and a drain structure 220 (page 2, paragraph 28; see AA view in fig. 2), and a gate structure 218 adjacent to one or more channel regions of the one or more semiconductor structures 210 (page 2, paragraph 28; see view CC in fig. 2); a via 1202 (page 4, paragraph 49) extending from a frontside metallization (704, 706) (BEOL; page 4, paragraph 43) over the transistor to a backside metallization (1302, 1304) (page 4, paragraph 50; page 5, paragraph 51) below the transistor (see fig. 13), wherein the via 1202 has a first width (top width) adjacent the frontside metallization (704, 706) (see view CC in fig. 13); and an insulative liner layer 214 (page 3, paragraph 34) on a sidewall of the via 1202 (see fig. 13), wherein the insulative liner layer 214 has a second width (top width) adjacent the first width (see view CC in fig. 13)
Xie fails to disclose explicitly wherein the insulative liner layer has the second width that is not more than one fifth of the first width.
However, the instant specification does not demonstrate that the claimed limitation requiring the second width to be not more than one fifth of the first width yields any unexpected results or represents a critical relationship as compared to other relative widths. In the absence of evidence that the claimed numerical relationship achieves a result that is unexpected or critical, selecting the claimed ratio amounts to no more than routine optimization of a known result-effective variable, and does not patentably distinguish the claimed invention from the prior art. Accordingly, the claim is prima facie obvious unless the claimed variable produces unexpected results (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select the relative widths of the via and the insulative liner, including a liner width that is not more than one fifth of the via width, through routine experimentation, in order to achieve a desired balance between providing sufficient electrical insulation and maximizing the conductive cross-sectional area of the via while maintaining manufacturability and structural reliability.
Regarding Claim 2, Xie fails to disclose explicitly wherein the second width is not more than 10% of the first width. However, limiting the second width to not more than 10% of the first width merely represents a further optimization of the relative dimensions of the insulative liner and the via. Selecting a particular percentage within an otherwise obvious range would have been an obvious matter of routine experimentation to achieve the desired balance between electrical insulation, via conductivity, and manufacturability. The instant specification likewise does not demonstrate that the claimed limitation of 10% produces any unexpected result or is critical.
Regarding Claim 3, Xie fails to disclose explicitly wherein the second width is not more than 5 nm. However, limiting the send width to not more than 5 nm constitutes the selection of a particular dimension for the insulative liner based on the routine optimization, including fabrication capability, electrical insulation requirements, and preservations of the conductive cross-sectional area of the via. Moreover, the instant specification does not establish that a liner width of not more than 5 nm yields any unexpected result or is critical relative to other suitable liner widths.
Regarding Claim 4, Xie discloses wherein the second width is on a first lateral side (left lateral side) of the via 1202 (see view CC in fig. 13) and wherein the insulative liner layer 214 has a third width on a second lateral side (right lateral side) of the via 1202 opposite the first lateral side (left lateral side) (see view CC in fig. 13)
Xie fails to disclose explicitly wherein the third width that is within 5% of the second width.
However, the instant specification does not demonstrate that maintaining the liner widths on opposite sidewalls within 5% of one another yields any unexpected result or represents a critical limitation over other substantially uniform liner thicknesses. In the absence of evidence of criticality or unexpected results attributable to the claimed numerical relationship, the claimed limitation merely reflects an obvious optimization of a known result-effective variable, and does not patentably distinguish the claimed invention from the prior art. Accordingly, the claim is prima facie obvious unless the claimed variable produces unexpected results (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide substantially uniform liner thicknesses on opposing sidewalls of the via, including thicknesses differing by no more than 5%, in order to promote consistent electrical insulation, mechanical reliability, stress distribution, and process uniformity while maximizing the conductive cross-sectional area of the via.
Regarding Claim 5, Xie discloses wherein the insulative liner layer 214 is on a component of the transistor, the component of the transistor comprising one of a gate electrode of the gate structure 218 (page 3, paragraph 33), a source contact (602, 604), or a drain contact (602, 604) (see fig. 13).
Regarding Claim 6, Xie discloses wherein the via 1202 comprises a taper (see view CC in fig. 13), the via 1202 has a third width (bottom width) at a position below the first width (top width) that is less than the first width (see view CC in fig. 13), and the insulative liner layer 214 has the second width (top width) at the position of the third width (uniform width from top to bottom; see view CC in fig. 13).
Regarding Claim 7, Xie discloses wherein the insulative liner layer 214 comprises silicon and nitrogen (silicon nitride; page 3, paragraph 34).
Regarding Claim 8, Xie discloses wherein the insulative liner layer 214 comprises a continuous monolithic material (page 3, paragraph 34; see view CC in fig. 13) in contact with the via 1202 and a component of the transistor (gate electrode or source/drain contacts 602, 604; see fig. 13).
Regarding Claim 9, Xie discloses an apparatus, comprising: an integrated circuit (IC) die (page 5, paragraph 61) comprising: a transistor comprising one or more semiconductor structures 210 (nanosheet; page 2, paragraph 28) extending between a source 220 and a drain 220 (page 2, paragraph 28; see AA view in fig. 2), and a gate 218 adjacent to the semiconductor structures 210 (page 2, paragraph 28; see view CC in fig. 2); a bridge via 1202 (page 4, paragraph 49) extending from a frontside metal (704, 706) (BEOL; page 4, paragraph 43) over the transistor to a backside metal (1302, 1304) (page 4, paragraph 50; page 5, paragraph 51) below the transistor (see fig. 13), wherein the bridge via 1202 has a first width (top width) adjacent the frontside metal (704, 706) (see view CC in fig. 13); and an insulative liner 214 (page 3, paragraph 34) on a sidewall of the bridge via 1202 (see fig. 13), wherein the insulative liner 214 has a second width (top width) adjacent the first width (see view CC in fig. 13); and a power supply coupled to the IC die (the backside power distribution network 1304 for supplying voltages; see fig. 13).
Xie fails to disclose explicitly wherein the insulative liner has the second width that is not more than one fifth of the first width.
However, the instant specification does not demonstrate that the claimed limitation requiring the second width to be not more than one fifth of the first width yields any unexpected results or represents a critical relationship as compared to other relative widths. In the absence of evidence that the claimed numerical relationship achieves a result that is unexpected or critical, selecting the claimed ratio amounts to no more than routine optimization of a known result-effective variable, and does not patentably distinguish the claimed invention from the prior art. Accordingly, the claim is prima facie obvious unless the claimed variable produces unexpected results (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to select the relative widths of the via and the insulative liner, including a liner width that is not more than one fifth of the via width, through routine experimentation, in order to achieve a desired balance between providing sufficient electrical insulation and maximizing the conductive cross-sectional area of the via while maintaining manufacturability and structural reliability.
Regarding Claim 11, Xie fails to disclose explicitly wherein the second width is not more than 2 nm. However, limiting the send width to not more than 2 nm constitutes the selection of a particular dimension for the insulative liner based on the routine optimization, including fabrication capability, electrical insulation requirements, and preservations of the conductive cross-sectional area of the via. Moreover, the instant specification does not establish that a liner width of not more than 2 nm yields any unexpected result or is critical relative to other suitable liner widths.
Regarding Claim 12, Xie discloses wherein the second width is on a first lateral side (left lateral side) of the bridge via 1202 (see view CC in fig. 13) and wherein the insulative liner 214 has a third width on a second lateral side (right lateral side) of the bridge via 1202 opposite the first lateral side (left lateral side) (see view CC in fig. 13)
Xie fails to disclose explicitly wherein the third width that is within 5% of the second width.
However, the instant specification does not demonstrate that maintaining the liner widths on opposite sidewalls within 5% of one another yields any unexpected result or represents a critical limitation over other substantially uniform liner thicknesses. In the absence of evidence of criticality or unexpected results attributable to the claimed numerical relationship, the claimed limitation merely reflects an obvious optimization of a known result-effective variable, and does not patentably distinguish the claimed invention from the prior art. Accordingly, the claim is prima facie obvious unless the claimed variable produces unexpected results (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955); Peterson, 315 F.3d at 1330, 65 USPQ2d at 1382; In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to provide substantially uniform liner thicknesses on opposing sidewalls of the via, including thicknesses differing by no more than 5%, in order to promote consistent electrical insulation, mechanical reliability, stress distribution, and process uniformity while maximizing the conductive cross-sectional area of the via.
Regarding Claim 13, Xie discloses wherein the bridge via 1202 comprises a taper (see view CC in fig. 13), the via 1202 has a third width (bottom width) at a second position (bottom position) below a position (top position), the third width is less than the first width (see view CC in fig. 13), and the insulative liner 214 has the second width (top width) at the second position (uniform width from top to bottom; see view CC in fig. 13).
Regarding Claim 14, Xie discloses wherein the insulative liner 214 comprises silicon and nitrogen (silicon nitride; page 3, paragraph 34), wherein the insulative liner 214 comprises a continuous monolithic material (page 3, paragraph 34; see view CC in fig. 13) in contact with the bridge via 1202 and a component of the transistor (see fig. 13), the component of the transistor comprising one of a gate electrode of the gate 218 (page 3, paragraph 33), a source contact (602, 604), or a drain contact (602, 604), and wherein the bridge via 1202 comprises tungsten (page 4, paragraphs 41 and 49).
Allowable Subject Matter
Claims 15-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claim 15 recites the material stack comprising an etch stop layer and one or more patterned layers comprising a pattern over the etch stop layer; filling the deep via opening with a hardmask material; removing the one or more patterned layers and the etch stop layer; removing the hardmask material to expose the deep via opening.
These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 16-20 depend from claim 15, so they are allowed for the same reason.
Conclusion
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/CHEUNG LEE/Primary Examiner, Art Unit 2812 July 16, 2026
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