DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 16, 2026 has been entered.
Response to Arguments
The Applicant’s remarks with respect to claims #17, 18, 20, 21, 23, and 25 in the reply filed on June 16, 2026 have been carefully considered, but are moot in view of the new grounds of rejection. Claim 19 remains indicated as being allowable.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. § 102(b)(2)(C) for any potential 35 U.S.C. § 102(a)(2) prior art against the later invention.
Claims 17, 18, 20, 21, 23, and 25 are rejected under 35 U.S.C. § 103 as being unpatentable over Cho (U.S. Patent Publication No. 2021/0193717 A1), and further in view of Oh (U.S. Patent Publication No. 2023/0129129 A1), hereafter “Oh”.
As to claim 17, Cho teaches:
A chip scale package assembly, comprising a glass substrate 500. Cho teaches an optical detection module comprising a chip scale package assembly. See Cho, FIG. 1.
A detection chip 200 located above the glass substrate.
An isolation layer 600b disposed on a surface of the detection chip opposite to the glass substrate.
A plurality of redistribution layers 154+140 disposed on the isolation layer and spaced from each other, and having a plurality of conductive units 140.
A plurality of conductive contacts 156 respectively disposed on the plurality of conductive units.
However, Cho does not teach a light sheltering layer directly attached to and extending along a lateral surface of the glass substrate, and adapted to block lateral light transmission and provide a covering protection function.
On the other hand, Oh teaches a light sheltering layer 400 directly attached to and extending along a lateral surface of the glass substrate (300, corresponding to Oh’s 500) and adapted to block lateral light transmission and provide a covering protection function. See Oh, FIG. 1.
It would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the light sheltering layer as taught by Oh into the overall package detection structure as taught by Cho in order to yield the predictable benefit of blocking the intrusion of foreign materials. Id. at ¶ [0069].
As to claim 18, the combination of Cho and Oh teaches a chip scale package detector IS and the light sheltering layer is vertically stacked and attached to a lateral surface of the glass substrate. See Cho, FIG. 1; Oh, FIG. 1.
As to claim 20, Cho teaches an isolation layer 630 located on the surface of the detection chip opposite to the imaging area, a part of the plurality of redistribution layers 154+140 stretches to another surface (bottom surface of 200) of the detection chip whereon the imaging area is located, the chip scale package assembly further comprises a protection layer 120 disposed on the plurality of redistribution layers to expose the plurality of conductive units 140, and is filled between two adjacent redistribution layers of the plurality of redistribution layers to connect the isolation layer. See Cho, FIG. 1.
As to claim 21, neither Cho nor Oh teaches a vertical height of the light sheltering layer is equal to or greater than a thickness of the glass substrate of the chip scale package assembly.
On the other hand, shape, size, and dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious. Note In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
As to claim 23, Cho teaches the detection chip 200 is glued to the glass substrate via an adhesion layer 600b, and Oh teaches the light sheltering layer 400 covers lateral surfaces of the glass substrate and the adhesion layer. See Cho, FIG. 1; Oh, FIG. 1.
As to claim 25, neither Cho nor Oh teaches a thickness or optical density of the light sheltering layer.
On the other hand, shape, size, and dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious. Note In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
On the other hand, it would have been obvious to one having ordinary skill in the art before the effective filing date to utilize a light sheltering material layer with the claimed optical density range, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claims Allowable If Rewritten in Independent Form
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 19, Cho teaches a wafer level lens ML and the light sheltering layer attached to the lateral surface of the glass substrate, but does not teach the light sheltering layer attached to a lateral surface of the wafer level lens because a cavity separates the light sheltering layer 610 and the wafer level lens.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBERR CHI whose telephone number is (571)270-3955. The examiner can normally be reached 10am to 6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SUBERR L CHI/Primary Examiner, Art Unit 2893
Prosecution Insights