Prosecution Insights
Last updated: April 19, 2026
Application No. 18/204,959

OPTICAL DETECTION MODULE AND RELATED MANUFACTURING METHOD

Final Rejection §102§103
Filed
Jun 02, 2023
Examiner
CHI, SUBERR L
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Pixart Imaging Inc.
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
2y 10m
To Grant
87%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
538 granted / 640 resolved
+16.1% vs TC avg
Minimal +3% lift
Without
With
+2.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
22 currently pending
Career history
662
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
49.8%
+9.8% vs TC avg
§102
11.1%
-28.9% vs TC avg
§112
33.2%
-6.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 640 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments The previously issued specification objection is hereby withdrawn in view of the amended title. The previously issued 35 U.S.C. § 112(b) rejection is hereby withdrawn in view of amended claim 20. The Applicant’s arguments with respect to claims #17, 18, 20, 21, 23, and 25 in the reply filed on January 14, 2026 have been carefully considered, but are not persuasive and the previous rejection maintained. The manner in which amended claim 17 is presently written does not require direct contact between a lateral surface of the glass substrate and a light sheltering layer. As such, “on” is interpreted as merely requiring proximity. Thus the previous prior art to Cho (U.S. Patent Publication No. 2021/0193717 A1), hereafter “Cho”, is maintained. This Final Rejection replaces the Final Rejection previously dated March 27, 2026 which inadvertently did not include a conclusory statement of Finality. Claim Rejections 35 U.S.C. § 102(a)(1) The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 17, 18, 20, and 23 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Cho. As to claim 17, Cho teaches: A chip scale package assembly, comprising a glass substrate 500. Cho teaches an optical detection module comprising a chip scale package assembly. See Cho, FIG. 1. A detection chip 200 located above the glass substrate. An isolation layer 600b disposed on a surface of the detection chip opposite to the glass substrate. A plurality of redistribution layers 154+140 disposed on the isolation layer and spaced from each other, and having a plurality of conductive units 140. A plurality of conductive contacts 156 respectively disposed on the plurality of conductive units. A light sheltering layer 610 disposed on a lateral surface of the glass substrate, and adapted to block light transmission and provide a covering protection function. Cho teaches the light sheltering layer 610 comprises silicon, a non-light permeable material. Id. at ¶ [0039]. The Examiner interprets “on” as merely requiring proximity. The manner in which the claim is written does not require “directly on” or “direct contact”. As to claim 18, Cho teaches a chip scale package detector IS and the light sheltering layer is vertically stacked and attached to a lateral surface of the glass substrate. Id. at FIG. 1. As to claim 20, Cho teaches an isolation layer 630 located on the surface of the detection chip opposite to the imaging area, a part of the plurality of redistribution layers 154+140 stretches to another surface (bottom surface of 200) of the detection chip whereon the imaging area is located, the chip scale package assembly further comprises a protection layer 120 disposed on the plurality of redistribution layers to expose the plurality of conductive units 140, and is filled between two adjacent redistribution layers of the plurality of redistribution layers to connect the isolation layer. Id. As to claim 23, Cho teaches the detection chip 200 is glued to the glass substrate via an adhesion layer 600b, the light sheltering layer 610 covers, by lying on top of/beneath, lateral surfaces of the glass substrate and the adhesion layer. Id. Claim Rejections - 35 U.S.C. § 103 The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. § 102(b)(2)(C) for any potential 35 U.S.C. § 102(a)(2) prior art against the later invention. Claims 21 and 25 are rejected under 35 U.S.C. § 103 as being unpatentable over Cho as applied to claim 17. As to claim 21, Cho does not teach a vertical height of the light sheltering layer is equal to or greater than a thickness of the glass substrate of the chip scale package assembly. On the other hand, shape, size, and dimension differences are considered obvious design choices and are not patentable unless unobvious or unexpected results are obtained from these changes. It appears that these changes produce no functional differences and therefore would have been obvious. Note In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). As to claim 25, Cho teaches a thickness of the light sheltering layer is 300 to 500 mm. See Cho, ¶ [0034]. However Cho does not teach an optical density of the light sheltering layer is ranged between 1 and 5. On the other hand, it would have been obvious to one having ordinary skill in the art before the effective filing date to utilize a light sheltering material layer with the claimed optical density range, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Claims Allowable If Rewritten in Independent Form Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. As to claim 19, Cho teaches a wafer level lens ML and the light sheltering layer attached to the lateral surface of the glass substrate, but does not teach the light sheltering layer attached to a lateral surface of the wafer level lens because a cavity separates the light sheltering layer 610 and the wafer level lens. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBERR CHI whose telephone number is (571)270-3955. The examiner can normally be reached 10am to 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SUBERR L CHI/Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jun 02, 2023
Application Filed
Nov 01, 2025
Non-Final Rejection — §102, §103
Jan 14, 2026
Response Filed
Mar 26, 2026
Final Rejection — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603479
METHOD OF MANUFACTURING VERTICAL-CAVITY SURFACE-EMITTING LASER ELEMENT
2y 5m to grant Granted Apr 14, 2026
Patent 12598766
Contact Interface Engineering for Reducing Contact Resistance
2y 5m to grant Granted Apr 07, 2026
Patent 12593676
SEMICONDUCTOR DEVICE WITH METAL SPACERS AND METHOD FOR FABRICATING THE SAME
2y 5m to grant Granted Mar 31, 2026
Patent 12581662
SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME
2y 5m to grant Granted Mar 17, 2026
Patent 12568828
METHOD AND SYSTEM FOR FABRICATING REGROWN FIDUCIALS FOR SEMICONDUCTOR DEVICES
2y 5m to grant Granted Mar 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
87%
With Interview (+2.9%)
2y 10m
Median Time to Grant
Moderate
PTA Risk
Based on 640 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month