DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an applications filed
in Korea, KR 10-2022-0131669 on October 13, 2022. Receipt is acknowledged of certified copies of
papers required by 37 CFR 1.55.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 07/17/2026 has been entered.
Response to Amendment
An amendment filed on 07/17/2026 in response to the Office Action mailed on 04/20/2026 is
being acknowledged and entered into the record. The present Non-Final rejection is made by taking into fully consideration all the amendments.
Response to Arguments
On pages 3-8 of the remarks filed on 07/17/2026, with respect to the rejection of Claim 1 and Claim 18, Applicant argues that unlike Pan’s through dielectric via 101 of Pan that penetrates through the dielectric encapsulating layer E2, the pillars 115b of Liao do not penetrate through an encapsulant Applicant further argues that even though Liao’s pillars 115b are periodically arranged in 2D, Liao does not disclose that the encapsulant encapsulates the second semiconductor chip, and that the first conductive posts pass through the encapsulant, and thus the combination of the cited references does not disclose “ a plurality of first conductive posts electrically connecting the first redistribution structure and the first semiconductor chip with each other, penetrating through the encapsulant in a first direction perpendicular to the upper surface of the first redistribution structure, and periodically and two-dimensionally arranged on the upper surface of the first redistribution structure when viewed in a plan view ,” These arguments are fully considered but are moot as Liao is no longer relied upon to cure the above highlighted deficiencies of Pan. As outlined in the rejection below, the newly found secondary reference of Jang teaches a 2D periodic array of conductive posts with a structure similar to that of Pan and hence cures the deficiency of Pan. Therefore, previously applied primary reference of Pan and Jang are relied upon to teach some of the limitations of Claim 1, Claim 18 and their dependents.
On page 9 of the remarks filed on 07/17/2026, with respect to the rejection of Claim 1 and Claim 18, Applicant argues that while in the previous rejection the Examiner appears to pick only the pillars 115b out of the pair of pillars 115a and 115b of Liao and then place them around the left-side chip 100 of Pan to arrive at the claimed invention, such a modification would amount to an improper hindsight reconstruction as the pair of pillars 115a and 115b have different heights. Applicant further argues that if the through-dielectric via 101 of Pan were modified to have a periodic arrangement in view of the teaching of Liao in which the pair of pillars 115a and 115b are periodically and two-dimensionally arranged when viewed in a plan view, such modification would necessarily reduce the stacking density of Pan. These arguments are fully considered but are moot for the same reasons indicated in the above paragraph. Therefore, previously applied primary reference of Pan and Jang are relied upon to teach some of the limitations of Claim 1, Claim 18 and their dependents.
On page 10 of the remarks filed on 07/17/2026, with respect to the rejection of Claim 1 and Claim 18, Applicant argues that the proposed modification of Pan in view of Liao would require additional through-dielectric vias to be formed in the space between the second package PK2 and the redistribution layer structure 102, originally occupied by the right-side chip 100a of the first package PK1 and thus, to accommodate the additional vias, the chip 100a would need to be removed, thereby decreasing the overall stacking density of Pan leading to a less compact structure contrary to Pan’s design objective of high integration. These arguments are fully considered but are not persuasive. In fact, a 2D periodic arrangement of conductive posts uses available area more efficiently enabling more vertical conductive posts per unit footprint and therefore would only increase the stacking density (i.e., no of conductive posts per unit area). Further, Pan teaches the dimensions of the die 100a can be varied (see paragraph 0013) and thus, the die 100a can be shrunk in size and the conductive posts can be periodically arranged locally in regions not occupied by the die, as shown in the newly found prior art reference of Jang (see annotated Fig. 1 and Fig. 2 of Jang below), without requiring the die 100a of Pan to be removed and significantly impacting the stacking density. Note that while Liao is not relied upon to teach the limitation of Claims 1 and 18, this argument is fully addressed for completeness and future references.
On pages 11-13 of the remarks filed on 07/17/2026, with respect to the rejection of Claim 1 and Claim 18, Applicant argues that Pan does not disclose the features of claim 1 that 1) the first conductive posts 155P are periodically arranged in two dimensions on the upper surface of the first redistribution structure in a plan view; and that 2) each of the UBM structures 164 is in contact with the corresponding second bump 145C and first conductive post 155P. These arguments are fully considered and are persuasive. Therefore, the rejection of Claims 1, 18 and their dependents has been withdrawn. However, upon further consideration, a new ground of 103 rejection is made for Claims 1, 18 and their dependents in view of previously applied reference of Pan and newly found references of Jang and Darmawikarta. As outlined in the rejection below, the combination of Pan, Jang and Darmawikarta teaches all of the above limitations.
On pages 14-15 of the remarks filed on 07/17/2026, with respect to the rejection of Claim 1 and Claim 18, Applicant argues that Liao and other cited references do not disclose the feature that 1) the first conductive posts 155P are periodically arranged in two dimensions on the upper surface of the first redistribution structure in a plan view and penetrate through the encapsulant 160 encapsulating the second semiconductor chip 120, 2) the second bumps 145C and the UBM structures 164 electrically connect the first conductive posts to the first semiconductor chip 250, each of the UBM structure being in contact with the corresponding second bump and first conductive post, and 3) upper surfaces of the first conductive posts 155P are coplanar with an upper surface of the encapsulant 160. These arguments are fully considered but are moot as Liao is no longer relied upon to teach any of the above limitations. As outlined in the rejection below, the combination of previously applied reference of Pan, and newly found references of Jang and Darmawikarta teaches all of the above limitations.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection note: Italicized claim limitations are limitations not explicitly disclosed in the primary
reference but disclosed in the secondary references.
Claims 1, 4 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20220344304 A1), in view of Jang et al. (US 20200091215 A1) and Darmawikarta et al. (US 20230197661 A1).
Regarding Claim 1, Pan et al. discloses a semiconductor package 11 comprising:
a first redistribution structure 102 in which at least one first redistribution layer 103 and at least one first insulating layer 104 are alternately stacked (see annotated Fig. 2: 102, 103, 104, paragraph 0010);
a first semiconductor chip 200’ disposed on an upper surface S1 of the first redistribution structure 102 (see annotated Fig. 2: 200’, S1, 102, paragraph 0022);
Note that the entire device structure PK2 of Fig. 2, including the two semiconductor chips 200, interposer substrate 202 and the encapsulant E2 is interpreted as the first semiconductor chip 200’ as highlighted by the rectangle in annotated Fig. 2.
an encapsulant E1 disposed between the first redistribution structure 102 and the first semiconductor chip 200’ (see annotated Fig. 2: E1, 102, 200, paragraph 0017);
a plurality of first conductive posts 101 electrically connecting the first redistribution structure 102 and the first semiconductor chip 200’ with each other, and penetrating through the encapsulant E1 in a first direction Z perpendicular to the upper surface S1 of the first redistribution structure 102, and periodically and two-dimensionally arranged on the upper surface of the first redistribution 102 structure when viewed in a plan view (see annotated Fig. 2: 101, 102, 200, E1, Z, paragraph 0011);
a heat dissipation member 304 having at least a portion that overlaps the first semiconductor chip 200’ in a second direction X that is perpendicular to the first direction Z (see annotated Fig. 2: 304, X, Z, paragraph 0030);
a second semiconductor chip 100 (right chip of the two chips 100) disposed between the first redistribution structure 102 and the heat dissipation member 304, and encapsulated by the encapsulant E1 (see annotated Fig. 2: 100, 102, 304, E1, paragraph 0012),
a plurality of UBM structures disposed between the encapsulant E1 and the first semiconductor chip 200’;
and a plurality of second bumps B2 disposed between the UBM structures and the first semiconductor chip 200’ (see annotated Fig. 2: B2, paragraph 0047),
wherein the plurality of UBM structures and the plurality of second bumps B2 electrically connect the plurality of first conductive posts 101 to the first semiconductor chip 200’ (see annotated Fig. 2: B2, 101, 200’, paragraph 0047),
wherein the first semiconductor chip 200’ overlaps the plurality of first conductive posts 101 in the first direction Z (see annotated Fig. 2: 200’, 101),
wherein the first semiconductor chip 200’ does not overlap the second semiconductor chip 100 in the first direction Z (see annotated Fig. 2: 100, 200’),
wherein upper surfaces of the plurality of first conductive posts 101 are coplanar with an upper surface of the encapsulant E1 (see annotated Fig. 2: 101, E1),
and wherein each UBM structure of the plurality of UBM structures is both in contact with a corresponding first conductive post among the plurality of first conductive posts and a corresponding second bump among the plurality of second bumps.
Jang et al. teaches a semiconductor package comprising the following limitations not explicitly disclosed in Pan et al.:
a plurality of first conductive posts 125 periodically and two-dimensionally arranged on the upper surface of the first redistribution structure 110 when viewed in a plan view (see Fig. 1: 125, Fig. 2: 110, 125, paragraph 0027, 0028)
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of Pan et al. and Jang et al. in order to have the plurality of first conductive posts periodically and two-dimensionally arranged on the upper surface of the first redistribution structure when viewed in a plan view. Doing so would allow for more efficient routing of signals enabled by the 2D array of conductive posts as well as improve the structural stability of the semiconductor package.
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Annotated Fig. 2 of Pan et al. (US 20220344304 A1)
Further, Darmawikarta et al. teaches a semiconductor package comprising the following limitations not explicitly disclosed in Pan et al.:
a plurality of UBM structures 172 disposed between the encapsulant 148 and the first semiconductor chip 114-2 (Fig. 4I: 172, 148, 114-2, paragraph 0051, 0052);
Note that RDL layer 148 will inherently comprise an insulating layer surrounding the conductive structures 196, 194 of Fig. 4I and hence is interpreted as the encapsulant.
and a plurality of second bumps 130 disposed between the UBM structures 172 and the first semiconductor chip 114-2 (see annotated Fig. 4I: 130, 114-2, 172, paragraph 0053),
wherein the plurality of UBM structures 172 and the plurality of second bumps 130 electrically connect the plurality of first conductive posts 194 to the first semiconductor chip 114-2 (see Fig. 4I: 172, 130, 194, 114-2, paragraph 0051-0053),
and wherein each UBM structure 172 of the plurality of UBM structures 172 is both in contact with a corresponding first conductive post 194 among the plurality of first conductive posts 194 and a corresponding second bump 130 among the plurality of second bumps 130 (Fig. 4I: 172, 130, 194).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of Pan et al. and Darmawikarta et al. in order to have a plurality of UBM structures disposed between the encapsulant and the first semiconductor chip such that the plurality of second bumps is disposed between the UBM structures and the first semiconductor chip, wherein the plurality of UBM structures and the plurality of second bumps electrically connect the plurality of first conductive posts to the first semiconductor chip, and wherein each UBM structure of the plurality of UBM structures is both in contact with a corresponding first conductive post among the plurality of first conductive posts and a corresponding second bump among the plurality of second bumps. By doing so, the UBM structures would improve adhesion and distribute electrical and mechanical stress and thereby enhance the reliability of the connection between the plurality of first conductive posts to the first semiconductor chip.
Regarding Claim 4, Pan et al. discloses the semiconductor package of Claim 1, wherein the plurality of first conductive posts 101 are disposed on a first region R1 of the upper surface S1 of the first redistribution structure 102, the first region R1 being adjacent to a first sidewall of the first redistribution structure 102, and wherein the second semiconductor chip 100 is disposed on a second region R2 of the upper surface S1 of the first redistribution structure 102, the second region R2 being adjacent to a second sidewall, opposite to the first sidewall, of the first redistribution structure 102 (see annotated Fig. 2).
Regarding Claim 5, Pan et al. discloses the semiconductor package of Claim 1, further comprising: a plurality of first bumps B1 disposed on a lower surface S2 of the first redistribution structure 102, and electrically connected to at least one of the first and second semiconductor chips 200’, 100, wherein the first and second semiconductor chips 200’, 100 are electrically connected with each other through the first redistribution structure 102 (see annotated Fig.2: B1, S2, 102, 100, 200’, paragraph 0025, 0046).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20220344304 A1), in view of Jang et al. (US 20200091215 A1) and Darmawikarta et al. (US 20230197661 A1), as applied to Claim 1 above, further in view of Choi et al. (US 20210005527 A1).
Regarding Claim 2, the combination of Pan et al., Jang et al. and Darmawikarta et al. fails to disclose the semiconductor package of claim 1, further comprising: a third semiconductor chip disposed between the second semiconductor chip and the heat dissipation member, and encapsulated by the encapsulant.
However, Choi et al. discloses a semiconductor package comprising a third semiconductor chip 200b disposed between a second semiconductor chip 200a and a heat dissipation member 170, and encapsulated by an encapsulant 148 (Fig. 1: 200a, 200b, 170, 148, paragraph 0026, 0029, 0040).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of Pan et al. and Choi et al. in order to have a third semiconductor chip disposed between the second semiconductor chip and the heat dissipation member, and encapsulated by the encapsulant. Doing so would enable a semiconductor packaging structure with vertically stacked die having a smaller footprint.
Regarding Claim 3, Choi et al. teaches the semiconductor package of claim 2, wherein the encapsulant 148 covers a sidewall of the third semiconductor chip 200b without covering an upper surface 200bS1 of the third semiconductor chip 200b, and wherein the upper surface 200bS1 of the third semiconductor chip 200b is adjacent to the heat dissipation member 170, and a lower surface 200bS2 of the third semiconductor chip 200b is adjacent to an upper surface 200aS1 of the second semiconductor chip 200a (see Fig. 1: 200bS1, 200bS2, 200aS1, 148, 200b, 170, 200a).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20220344304 A1), in view of Jang et al. (US 20200091215 A1) and Darmawikarta et al. (US 20230197661 A1), as applied to Claim 1 above, further in view of Refai-Ahmed et al. (US 20210193620 A1).
Regarding Claim 7, the combination of Pan et al., Jang et al. and Darmawikarta et al. fails to disclose the semiconductor package of claim 1, further comprising: a plurality of second conductive posts disposed between the second semiconductor chip and the heat dissipation member, wherein the plurality of second conductive posts extend from the heat dissipation member toward the second semiconductor chip in the first direction, and wherein the plurality of second conductive posts thermally connect the second semiconductor chip to the heat dissipation member.
However, Refai-Ahmed et al. discloses a semiconductor package comprising a plurality of second conductive posts 110 disposed between the second semiconductor chip 106 and the heat dissipation member 102, wherein the plurality of second conductive posts 110 extend from the heat dissipation 102 member toward the second semiconductor chip 106 in the first direction (vertical direction Z), and wherein the plurality of second conductive posts 110 thermally connect the second semiconductor chip 106 to the heat dissipation member 102 (Fig. 1: 110, 106, 102, paragraph 0019, 0020, 0024).
Therefore, a person of ordinary skill in the art, using the combined the teachings of Pan et al. and Refai-Ahmed et al. would have disposed the plurality of second conductive posts of Refai-Ahmed et al. in the semiconductor package of Pan et al. in order to come up with the claimed invention. Doing so would provide efficient heat transfer paths that facilitate the extraction of heat out of the semiconductor package, as recognized by Refai-Ahmed et al. (paragraph 0024).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20220344304 A1), in view of Jang et al. (US 20200091215 A1) and Darmawikarta et al. (US 20230197661 A1), as applied to Claim 1 above, further in view of Chen et al. (US 20190103386 A1).
Regarding Claim 8, the combination of Pan et al., Jang et al. and Darmawikarta et al. fails to disclose the semiconductor package of claim 1, further comprising: a second redistribution structure disposed between the second semiconductor chip and the heat dissipation member, wherein the second redistribution structure includes at least one second redistribution layer and at least one second insulating layer that are alternately stacked on each other.
However, Chen et al. discloses a semiconductor package comprising a second redistribution structure 16, 20 disposed between the second semiconductor chip 24 and an electronic device 46, wherein the second redistribution structure 16, 20 includes at least one second redistribution layer 16 and at least one second insulating layer 20 that are alternately stacked on each other (Fig. 1A: 16, 20, 24, 46, paragraph 0069, 0070, 0071).
Therefore, a person of ordinary skill in the art, using the combined the teachings of Pan et al. and Chen et al. would have disposed the second redistribution structure of Chen et al. in the semiconductor package of Pan et al. in order to come up with the claimed invention. Doing so, would enable design flexibility allowing for more elements such as the heat dissipation member to be integrated efficiently into the semiconductor package.
While the combination of Chen et al. and Pan et al. does not explicitly teach the second redistribution structure is disposed between the second semiconductor chip and a heat dissipation member, a person of ordinary skill in the art would have recognized that when the second redistribution structure of Chen et al. is disposed in the semiconductor package of Pan et al., the second redistribution structure will be disposed between the second semiconductor chip and the heat dissipation member of Pan et al.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20220344304 A1), in view of Jang et al. (US 20200091215 A1), Darmawikarta et al. (US 20230197661 A1) and Choi et al. (US 20210005527 A1).
Regarding Claim 18, Pan et al. teaches a semiconductor package comprising:
a first redistribution structure 102 in which at least one first redistribution layer 103 and at least one first insulating layer 104 are alternately stacked (see annotated Fig. 2: 102, 103, 104, paragraph 0010);
a first semiconductor chip 200’ disposed on an upper surface S1 of the first redistribution structure 102 (see annotated Fig. 2: 200’, S1, 102, paragraph 0022);
Note that the entire device structure PK2 of Fig. 2, including the two semiconductor chips 200, interposer substrate 202 and the encapsulant E2 is interpreted as the first semiconductor chip 200’ as highlighted by the rectangle in annotated Fig. 2.
an encapsulant E1 disposed between the first redistribution structure 102 and the first semiconductor chip 200’ (see annotated Fig. 2: E1, 102, 200, paragraph 0017);
a plurality of first conductive posts 101 electrically connecting the first redistribution structure 102 and the first semiconductor chip 200’ with each other, and penetrating through the encapsulant E1 in a first direction Z perpendicular to the upper surface S1 of the first redistribution structure 102 (see annotated Fig. 2: 101, 102, 200, E1, Z, paragraph 0011);
a heat dissipation member 304 having at least a portion that overlaps the first semiconductor chip 200’ in a second direction X that is perpendicular to the first direction Z and is parallel to the upper surface S1 of the first redistribution structure 102 (see annotated Fig. 2: 304, X, Z, paragraph 0030);
a second semiconductor chip 100 (right chip of the two chips 100) having at least a portion disposed between the first redistribution structure 102 and the heat dissipation member 304, and encapsulated by the encapsulant E1 (see annotated Fig. 2: 100, 102, 304, E1, paragraph 0012);
a third semiconductor chip disposed between the second semiconductor chip and the heat dissipation member, and encapsulated by the encapsulant;
and a plurality of first bumps B1 disposed on a lower surface S2 of the first redistribution structure 102, and electrically connected to at least one of the first and second semiconductor chips 200’, 100 (see annotated Fig.2: B1, S2, 102, 100, 200’, paragraph 0025, 0046);
a plurality of UBM structures disposed between the encapsulant E1 and the first semiconductor chip 200’;
and a plurality of second bumps B2 disposed between the UBM structures and the first semiconductor chip 200’ (see annotated Fig. 2: B2, paragraph 0047),
wherein the plurality of UBM structures and the plurality of second bumps B2 electrically connect the plurality of first conductive posts 101 to the first semiconductor chip 200’ (see annotated Fig. 2: B2, 101, 200’, paragraph 0047),
wherein the first and second semiconductor chips 200’, 100 are electrically connected with each other through the first redistribution structure 102 (see annotated Fig.2: B1, S2, 102, 100, 200’, paragraph 0025, 0046).
wherein the plurality of first conductive posts 101 are disposed on a first region R1 of the upper surface S1 of the first redistribution structure 102 in the second direction X and a third direction when viewed in a plan view, the first region R1 being adjacent to a first sidewall of the first redistribution structure 102 and the third direction being parallel to the upper surface of the first redistribution structure and perpendicular to the second direction, wherein the second semiconductor chip 100 is disposed on a second region R2 of the upper surface S1 of the first redistribution structure 102, the second region R2 being adjacent to a second sidewall, opposite to the first sidewall, of the first redistribution structure 102 (see annotated Fig. 2).
wherein upper surfaces of the plurality of first conductive posts 101 are coplanar with an upper surface of the encapsulant E1 (see annotated Fig. 2: 101, E1),
and wherein each UBM structure of the plurality of UBM structures is both in contact with a corresponding first conductive post among the plurality of first conductive posts and a corresponding second bump among the plurality of second bumps.
Choi et al. discloses a semiconductor package comprising the following limitations not explicitly disclosed in Pan et al.:
a third semiconductor chip 200b disposed between a second semiconductor chip 200a and a heat dissipation member 170, and encapsulated by an encapsulant 148 (Fig. 1: 200a, 200b, 170, 148, paragraph 0026, 0029, 0040).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of Pan et al. and Choi et al. in order to have a third semiconductor chip disposed between the second semiconductor chip and the heat dissipation member, and encapsulated by the encapsulant. Doing so would enable a semiconductor packaging structure with vertically stacked die having a smaller footprint.
Further, Darmawikarta et al. teaches a semiconductor package comprising the following limitations not explicitly disclosed in Pan et al.:
a plurality of UBM structures 172 disposed between the encapsulant 148 and the first semiconductor chip 114-2 (Fig. 4I: 172, 148, 114-2, paragraph 0051, 0052);
Note that RDL layer 148 will inherently comprise an insulating layer surrounding the conductive structures 196, 194 of Fig. 4I and hence is interpreted as the encapsulant.
and a plurality of second bumps 130 disposed between the UBM structures 172 and the first semiconductor chip 114-2 (see annotated Fig. 4I: 130, 114-2, 172, paragraph 0053),
wherein the plurality of UBM structures 172 and the plurality of second bumps 130 electrically connect the plurality of first conductive posts 194 to the first semiconductor chip 114-2 (see Fig. 4I: 172, 130, 194, 114-2, paragraph 0051-0053),
and wherein each UBM structure 172 of the plurality of UBM structures 172 is both in contact with a corresponding first conductive post 194 among the plurality of first conductive posts 194 and a corresponding second bump 130 among the plurality of second bumps 130 (Fig. 4I: 172, 130, 194).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of Pan et al. and Darmawikarta et al. in order to have a plurality of UBM structures disposed between the encapsulant and the first semiconductor chip such that the plurality of second bumps is disposed between the UBM structures and the first semiconductor chip, wherein the plurality of UBM structures and the plurality of second bumps electrically connect the plurality of first conductive posts to the first semiconductor chip, and wherein each UBM structure of the plurality of UBM structures is both in contact with a corresponding first conductive post among the plurality of first conductive posts and a corresponding second bump among the plurality of second bumps. By doing so, the UBM structures would improve adhesion and distribute electrical and mechanical stress and thereby enhance the reliability of the connection between the plurality of first conductive posts to the first semiconductor chip.
Furthermore, Jang et al. teaches a semiconductor package comprising the following limitations not explicitly disclosed in Pan et al.:
a plurality of conductive posts 125, wherein the plurality of first conductive posts 125 are periodically disposed on a first region R1 of the upper surface of the first redistribution structure 110 in the second direction Y and a third direction X when viewed in a plan view, the third direction X being parallel to the upper surface of the first redistribution structure 110 and perpendicular to the second direction Y (see annotated Fig. 1: X, Y, 125, 110, R1, Fig. 2: X, Y, 125, 110, R1, paragraph 0027, 0028).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of Pan et al. and Jang et al. in order to have the plurality of first conductive posts periodically disposed, and disposed in a third direction when viewed in a plan view, the third direction being parallel to the upper surface of the first redistribution structure and perpendicular to the second direction. Doing so would allow for more efficient routing of signals enabled by the 2D array of conductive posts as well as improve the structural stability of the semiconductor package.
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Annotated Fig. 1 and Fig. 2 of Jang et al. (US 20200091215 A1)
Regarding Claim 19, the combination of Pan et al. and Choi et al teaches the semiconductor package of claim 18,
wherein the first semiconductor chip 200’ overlaps the plurality of first conductive posts 101 in the first direction Z (as taught by Pan et al., see annotated Fig. 2), wherein the first semiconductor chip 200’ does not overlap the second semiconductor chip 100 in the first direction Z (as taught by Pan et al., see annotated Fig. 2),
wherein the encapsulant 148 covers a sidewall of the third semiconductor chip 200b without covering an upper surface 200bS1 of the third semiconductor chip 200b, and wherein the upper surface 200bS1 of the third semiconductor chip 200b is adjacent to the heat dissipation member 170, and a lower surface 200bS2 of the third semiconductor chip 200b is adjacent to an upper surface 200aS1 of the second semiconductor chip 200a (as taught by Choi et al., see Fig. 1: 200bS1, 200bS2, 200aS1, 148, 200b, 170, 200a).
Furthermore, a person of ordinary skill in the art would have recognized that when the third semiconductor chip of Choi et al. is disposed in the semiconductor package of Pan et al., the first semiconductor chip 200’ of Pan et al. will not overlap the third semiconductor chip of Choi et al. in the first direction Z.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 07/22/2026
/Kretelia Graham/ Supervisory Patent Examiner, Art Unit 2817
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