DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/28/2026 is being considered by the
examiner.
Response to Amendment
An amendment filed on 11/20/2025 in response to the Office Action mailed on 09/02/2025 is
being acknowledged and entered into the record. The present Final rejection is made by taking into fully
consideration all the amendments.
Response to Arguments
On pages 4-6 of the remarks filed on 11/20/2025, with respect to the rejection of Claim 18, Applicant argues that Pan does not disclose “wherein the plurality of first conductive posts are periodically disposed on a first region of an upper surface of the first redistribution structure in the second direction and a third direction when viewed in a plan view.” This argument is fully considered and is persuasive. Therefore, the rejection of Claim 18 in view of Pan is withdrawn. However, upon further consideration, a new ground of 103 rejection is made in view of previously applied prior art references of Pan/Choi and newly found prior art reference of Liao et al. Liao et al. teaches the newly added limitation of claim 18. i.e., Liao et al. teaches a semiconductor package comprising a plurality of conductive posts 115b, wherein the plurality of first conductive posts 115b are periodically disposed on a first region of the upper surface 104 of the first redistribution structure 103 in the second direction hd1 and a third direction hd2 when viewed in a plan view, the third direction hd2 being parallel to the upper surface 104 of the first redistribution structure 103 and perpendicular to the second direction hd1 (see Fig. 7A: 103, 104, 115b, Fig. 7B: 115b, hd1, hd2, 104, paragraph 0053, 0097). A new ground of rejection is also made for Claim 19, which is dependent on Claim 18.
On pages 6-8 of the remarks filed on 11/20/2025, with respect to the rejection of Claim 18, Applicant argues that the Examiner’s proposed modification of Pan with the teachings of Choi, in particular the periodic and two-dimension arrangement of conductive element 310, suggested during the interview conducted on October 15th 2025, lacks any articulated reasoning with rational underpinning that would have prompted a person of ordinary skill in the art to modify the through-dielectric via 101 of Pan to be periodically arranged as there is no correspondence between Choi’s periodic and two-dimension arrangement of conductive element 310 (Fig. 1 and Fig. 3 of Choi) and Pan’s dielectric via 101 (Fig. 2 of Pan). This argument is fully considered but is moot as Choi is not relied upon to teach the newly added limitation of amended Claim 18.
On pages 9-10 of the remarks filed on 11/20/2025, with respect to the rejection of Claim 18, Applicant argues that the modification of the through-dielectric vias of Pan to have a periodic arrangement in view of the teachings of Choi would reduce the stacking density of Pan. Applicant further argues that in order to accommodate the additional vias in the 2D arrangement, the chip 100a of Pan would have to be removed and therefore would decrease the overall stacking density. This argument is fully considered but is not persuasive. In fact, a 2D periodic arrangement of conductive posts uses available area more efficiently enabling more vertical conductive posts per unit footprint and therefore would only increase the stacking density (i.e., no of conductive posts per unit area). Further, the conductive posts can be periodically arranged locally in regions not occupied by the die and thus not requiring the die 100a of Pan to be removed. Newly found prior art reference of Liao et al. teaches such a structure in which conductive posts 115b are periodically and locally arranged in 2D around features 115b (See Fig. 7A-7B: 115b, 115a). Note that while Choi is not relied upon to teach the above limitation of Claim 18, this argument is fully addressed for completeness and future references.
On pages 10-14 of the remarks filed on 11/20/2025, with respect to the rejection of Claim 1, Applicant argues that the Examiner’s claim mapping of Pan is inconsistent in that only the right-hand chip 100 of PK1 is mapped as the claimed “second semiconductor chip,” while both chips 200 of PK2 are mapped as the claimed “first semiconductor chip”, and therefore, Pan does not teach or suggest “wherein the first semiconductor chip overlaps the plurality of first conductive posts in the first direction, and wherein the first semiconductor chip does not overlap the second semiconductor chip in the first direction.” This argument is fully considered but is not persuasive. MPEP § 2111 discusses proper claim interpretation, including giving claims their broadest reasonable interpretation in light of the specification during examination. Under broadest reasonable interpretation (BRI), the words of a claim must be given their plain meaning unless such meaning is inconsistent with the specification, and it is improper to import claim limitations from the specification into the claim. As such, under the BRI, “first semiconductor die” is not limited to a single die and therefore the two die 200 in PK2 of Pan can be reasonably interpreted as a single die as they have the same function and are physically adjacent and electrically connected together via the bond wire 201 (see annotated Fig. 2 : PK2, 200, paragraph 0022 of Pan). Similarly, under the BRI, “second semiconductor die” is defined broadly and does not require all dies in a package to be included (see annotated Fig. 2 : PK1, 100, paragraph 0022 of Pan). Further, according to an embodiment of Pan et al., the semiconductor die 100 can serve different functions with one of them being an active die and the other being a dummy die (see paragraph 0013 of Pan). Thus, a single die 100 of PK1 in Pan meets the claim limitation of Claim 1. Therefore, Pan is still relied upon to teach the limitations of Claim 1 and all claims dependent on Claim 1.
On pages 14-15 of the remarks filed on 11/20/2025, with respect to the rejection of Claim 9, Applicant argues that the prior art of record fails to teach “a plurality of first conductive posts … and periodically and two-dimensionally arranged on an upper surface of the first redistribution structure when viewed in a plan view.” This argument is fully considered and is persuasive. Therefore, the rejection of Claim 1 in view of Pan/Chen is withdrawn. However, upon further consideration, a new ground of 103 rejection is made in view of previously applied prior art references of Pan/Chen and newly found prior art reference of Liao et al. Liao et al. teaches the newly added limitation of claim 9. i.e., Liao et al. teaches a semiconductor package comprising a plurality of conductive posts 115b … and periodically and two-dimensionally arranged on an upper surface 104 of the first redistribution structure 103 when viewed in a plan view, (see Fig. 7A: 103, 104, 115b, Fig. 7B: 115b, 104, paragraph 0053, 0097). A new ground of rejection is also made for all claims dependent on Claim 9.
On pages 15-18 of the remarks filed on 11/20/2025, with respect to the rejection of Claim 10, Applicant argues that modifying Pan in view of Jang requires shifting the right chip 100 toward vias 101 which would necessarily reduce its overlap with heat spreader 304, frustrating Pan’s fundamental principle of operation and thus, Pan in view of Jang does not disclose “wherein a portion of the first semiconductor chip overlaps the second semiconductor chip in the first direction.” This argument is fully considered but is not persuasive. Pan teaches that the width W1 of the right-most die 100 is a variable that can be adjusted to improve heat dissipation (see Fig. 2, paragraph 0028). Therefore, the width of the die 100 can be increased instead of shifting the die towards the conductive posts 101. Such a modification is a matter of design choice and is executable by a person of ordinary skill in the art to create an overlap between the first die 200’ and second die 100, while also maintaining the overlap between the heat spreader and the right-most die 100. Thus, Pan/Jang is still relied upon to teach the above limitation.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, and 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20220344304 A1), in view of Liao et al. (US 20230386988 A1).
Regarding Claim 1, Pan et al. discloses a semiconductor package 11 comprising:
a first redistribution structure 102 in which at least one first redistribution layer 103 and at least one first insulating layer 104 are alternately stacked (see annotated Fig. 2: 102, 103, 104, paragraph 0010);
a first semiconductor chip 200’ disposed on an upper surface S1 of the first redistribution structure 102 (see annotated Fig. 2: 200’, S1, 102, paragraph 0022);
Note that the entire device structure PK2 of Fig. 2, including the two semiconductor chips 200, interposer substrate 202 and the encapsulant E2 is interpreted as the first semiconductor chip 200’ as highlighted by the rectangle in annotated Fig. 2.
an encapsulant E1 disposed between the first redistribution structure 102 and the first semiconductor chip 200’ (see annotated Fig. 2: E1, 102, 200, paragraph 0017);
a plurality of first conductive posts 101 electrically connecting the first redistribution structure 102 and the first semiconductor chip 200’ with each other, and penetrating through the encapsulant E1 in a first direction Z perpendicular to the upper surface S1 of the first redistribution structure 102 (see annotated Fig. 2: 101, 102, 200, E1, Z, paragraph 0011);
a heat dissipation member 304 having at least a portion that overlaps the first semiconductor chip 200’ in a second direction X that is perpendicular to the first direction Z (see annotated Fig. 2: 304, X, Z, paragraph 0030);
and a second semiconductor chip 100 (right chip of the two chips 100) disposed between the first redistribution structure 102 and the heat dissipation member 304, and encapsulated by the encapsulant E1 (see annotated Fig. 2: 100, 102, 304, E1, paragraph 0012),
wherein the first semiconductor chip 200’ overlaps the plurality of first conductive posts 101 in the first direction Z (see annotated Fig. 2: 200’, 101),
and wherein the first semiconductor chip 200’ does not overlap the second semiconductor chip 100 in the first direction Z (see annotated Fig. 2: 100, 200’).
Pan et al. fails to explicitly teach the plurality of first conductive posts 101 are periodically and two-dimensionally arranged on the upper surface of the first redistribution structure 102 when viewed in a plan view.
However, Liao et al. teaches a semiconductor package comprising a plurality of first conductive posts 115b periodically and two-dimensionally arranged on the upper surface 104 of the first redistribution structure 103 when viewed in a plan view (see Fig. 7A: 103, 104, 115b, Fig. 7B: 115b, 104, paragraph 0053, 0097).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of Pan et al. and Choi et al. in order to have the plurality of first conductive posts periodically and two-dimensionally arranged on the upper surface of the first redistribution structure when viewed in a plan view. Doing so would allow for more efficient routing of signals enabled by the 2D array of conductive posts as well as improve the structural stability of the semiconductor package.
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Annotated Fig. 2 of Pan et al. (US 20220344304 A1)
Regarding Claim 4, Pan et al. discloses the semiconductor package of Claim 1, wherein the plurality of first conductive posts 101 are disposed on a first region R1 of the upper surface S1 of the first redistribution structure 102, the first region R1 being adjacent to a first sidewall of the first redistribution structure 102, and wherein the second semiconductor chip 100 is disposed on a second region R2 of the upper surface S1 of the first redistribution structure 102, the second region R2 being adjacent to a second sidewall, opposite to the first sidewall, of the first redistribution structure 102 (see annotated Fig. 2).
Regarding Claim 5, Pan et al. discloses the semiconductor package of Claim 1, further comprising: a plurality of first bumps B1 disposed on a lower surface S2 of the first redistribution structure 102, and electrically connected to at least one of the first and second semiconductor chips 200’, 100, wherein the first and second semiconductor chips 200’, 100 are electrically connected with each other through the first redistribution structure 102 (see annotated Fig.2: B1, S2, 102, 100, 200’, paragraph 0025, 0046).
Regarding Claim 6, Pan et al. discloses the semiconductor package of claim 1, further comprising: a plurality of second bumps B2 electrically connecting the plurality of first conductive posts 101 to the first semiconductor chip 200’, wherein each second bump B2 of the plurality of second bumps B2 overlaps a corresponding first conductive post 101 among the plurality of first conductive posts 101 in the first direction Z (Fig. 2: B2, 101, 200’, paragraph 0025).
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20220344304 A1), in view of Liao et al. (US 20230386988 A1), as applied to Claim 1 above, further in view of Choi et al. (US 20210005527 A1).
Regarding Claim 2, the combination of Pan et al. and Liao et al. fails to disclose the semiconductor package of claim 1, further comprising: a third semiconductor chip disposed between the second semiconductor chip and the heat dissipation member, and encapsulated by the encapsulant.
However, Choi et al. discloses a semiconductor package comprising a third semiconductor chip 200b disposed between a second semiconductor chip 200a and a heat dissipation member 170, and encapsulated by an encapsulant 148 (Fig. 1: 200a, 200b, 170, 148, paragraph 0026, 0029, 0040).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of Pan et al. and Choi et al. in order to have a third semiconductor chip disposed between the second semiconductor chip and the heat dissipation member, and encapsulated by the encapsulant. Doing so would enable a semiconductor packaging structure with vertically stacked die having a smaller footprint.
Regarding Claim 3, Choi et al. teaches the semiconductor package of claim 2, wherein the encapsulant 148 covers a sidewall of the third semiconductor chip 200b without covering an upper surface 200bS1 of the third semiconductor chip 200b, and wherein the upper surface 200bS1 of the third semiconductor chip 200b is adjacent to the heat dissipation member 170, and a lower surface 200bS2 of the third semiconductor chip 200b is adjacent to an upper surface 200aS1 of the second semiconductor chip 200a (see Fig. 1: 200bS1, 200bS2, 200aS1, 148, 200b, 170, 200a).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20220344304 A1), in view of Liao et al. (US 20230386988 A1), as applied to Claim 1 above, further in view of Refai-Ahmed et al. (US 20210193620 A1).
Regarding Claim 7, the combination of Pan et al. and Liao et al. fails to disclose the semiconductor package of claim 1, further comprising: a plurality of second conductive posts disposed between the second semiconductor chip and the heat dissipation member, wherein the plurality of second conductive posts extend from the heat dissipation member toward the second semiconductor chip in the first direction, and wherein the plurality of second conductive posts thermally connect the second semiconductor chip to the heat dissipation member.
However, Refai-Ahmed et al. discloses a semiconductor package comprising a plurality of second conductive posts 110 disposed between the second semiconductor chip 106 and the heat dissipation member 102, wherein the plurality of second conductive posts 110 extend from the heat dissipation 102 member toward the second semiconductor chip 106 in the first direction (vertical direction Z), and wherein the plurality of second conductive posts 110 thermally connect the second semiconductor chip 106 to the heat dissipation member 102 (Fig. 1: 110, 106, 102, paragraph 0019, 0020, 0024).
Therefore, a person of ordinary skill in the art, using the combined the teachings of Pan et al. and Refai-Ahmed et al. would have disposed the plurality of second conductive posts of Refai-Ahmed et al. in the semiconductor package of Pan et al. in order to come up with the claimed invention. Doing so would provide efficient heat transfer paths that facilitate the extraction of heat out of the semiconductor package, as recognized by Refai-Ahmed et al. (paragraph 0024).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20220344304 A1), in view of Liao et al. (US 20230386988 A1), as applied to Claim 1 above, further in view of Chen et al. (US 20190103386 A1).
Regarding Claim 8, the combination of Pan et al. and Liao et al. fails to disclose the semiconductor package of claim 1, further comprising: a second redistribution structure disposed between the second semiconductor chip and the heat dissipation member, wherein the second redistribution structure includes at least one second redistribution layer and at least one second insulating layer that are alternately stacked on each other.
However, Chen et al. discloses a semiconductor package comprising a second redistribution structure 16, 20 disposed between the second semiconductor chip 24 and an electronic device 46, wherein the second redistribution structure 16, 20 includes at least one second redistribution layer 16 and at least one second insulating layer 20 that are alternately stacked on each other (Fig. 1A: 16, 20, 24, 46, paragraph 0069, 0070, 0071).
Therefore, a person of ordinary skill in the art, using the combined the teachings of Pan et al. and Chen et al. would have disposed the second redistribution structure of Chen et al. in the semiconductor package of Pan et al. in order to come up with the claimed invention. Doing so, would enable design flexibility allowing for more elements such as the heat dissipation member to be integrated efficiently into the semiconductor package.
While the combination of Chen et al. and Pan et al. does not explicitly teach the second redistribution structure is disposed between the second semiconductor chip and a heat dissipation member, a person of ordinary skill in the art would have recognized that when the second redistribution structure of Chen et al. is disposed in the semiconductor package of Pan et al., the second redistribution structure will be disposed between the second semiconductor chip and the heat dissipation member of Pan et al.
Claims 9, 11, 12, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20220344304 A1), in view of Liao et al. (US 20230386988 A1) and Chen et al. (US 20190103386 A1).
Regarding Claim 9, Pan et al. teaches a semiconductor package comprising:
a first redistribution structure 102 in which at least one first redistribution layer 103 and at least one first insulating layer 104 are alternately stacked (see annotated Fig. 2: 102, 103, 104, paragraph 0010);
a first semiconductor chip 200’ disposed on an upper surface S1 of the first redistribution structure 102 (see annotated Fig. 2: 200’, S1, 102, paragraph 0022);
Note that the entire device structure PK2 of Fig. 2, including the two semiconductor chips 200, interposer substrate 202 and the encapsulant E2 is interpreted as the first semiconductor chip 200’ as highlighted by the rectangle in annotated Fig. 2.
an encapsulant E1 disposed between the first redistribution structure 102 and the first semiconductor chip 200’ (see annotated Fig. 2: E1, 102, 200, paragraph 0017);
a plurality of first conductive posts 101 electrically connecting the first redistribution structure 102 and the first semiconductor chip 200’ with each other, penetrating through the encapsulant E1 in a first direction Z perpendicular to the upper surface S1 of the first redistribution structure 102 (see annotated Fig. 2: 101, 102, 200, E1, Z, S1, 102 paragraph 0011);
a heat dissipation member 304 having at least a portion that overlaps the first semiconductor chip 200’ in a second direction X that is perpendicular to the first direction Z (see annotated Fig. 2: 304, X, Z, paragraph 0030);
a second semiconductor chip 100 (right chip of the two chips 100) having at least a portion disposed between the first redistribution structure 102 and the heat dissipation member 304, and encapsulated by the encapsulant E1 (see annotated Fig. 2: 100, 102, 304, E1, paragraph 0012);
Pan et al. fails to explicitly teach the plurality of first conductive posts 101 are periodically and two-dimensionally arranged on the upper surface of the first redistribution structure 102 when viewed in a plan view, a second redistribution structure disposed between the second semiconductor chip and the heat dissipation member, wherein the second redistribution structure includes at least one second redistribution layer and at least one second insulating layer that are alternately stacked on each other.
However, Liao et al. teaches a semiconductor package comprising a plurality of first conductive posts 115b periodically and two-dimensionally arranged on the upper surface 104 of the first redistribution structure 103 when viewed in a plan view (see Fig. 7A: 103, 104, 115b, Fig. 7B: 115b, 104, paragraph 0053, 0097).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of Pan et al. and Choi et al. in order to have the plurality of first conductive posts periodically and two-dimensionally arranged on the upper surface of the first redistribution structure when viewed in a plan view. Doing so would allow for more efficient routing of signals enabled by the 2D array of conductive posts as well as improve the structural stability of the semiconductor package.
Furthermore, Chen et al. discloses a semiconductor package comprising a second redistribution structure 16, 20 disposed between the second semiconductor chip 24 and an electronic device 46, wherein the second redistribution structure 16, 20 includes at least one second redistribution layer 16 and at least one second insulating layer 20 that are alternately stacked on each other (Fig. 1A: 16, 20, 24, 46, paragraph 0069, 0070, 0071).
Therefore, a person of ordinary skill in the art, using the combined the teachings of Pan et al. and Chen et al. would have disposed the second redistribution structure of Chen et al. in the semiconductor package of Pan et al. in order to come up with the claimed invention. Doing so, would enable design flexibility allowing for more elements such as the heat dissipation member to be integrated efficiently into the semiconductor package.
While the combination of Chen et al. and Pan et al. does not explicitly teach the second redistribution structure is disposed between the second semiconductor chip and a heat dissipation member, a person of ordinary skill in the art would have recognized that when the second redistribution structure of Chen et al. is disposed in the semiconductor package of Pan et al., the second redistribution structure will be disposed between the second semiconductor chip and the heat dissipation member of Pan et al.
Regarding Claim 11, Pan et al. teaches the semiconductor package of claim 9, wherein a size W3 of a lower surface of the heat dissipation member 304 adjacent to the second semiconductor chip 100 is smaller than a size W4 of a lower surface of the first semiconductor chip 200’ adjacent to the plurality of first conductive posts 101 (see annotated Fig. 2: W3, W4).
Regarding Claim 12, Chen et al. teaches the semiconductor package of claim 9, wherein the at least one second redistribution layer 16 has a first number of layers (one layer 16), and wherein the at least one first redistribution layer 38, 40 has a second number of layers (two layers 38 and 40), the first number (one) being smaller than the second number (two) (See Fig. 1A).
Regarding Claim 15, Pan et al. teaches the semiconductor package of claim 9, wherein the plurality of first conductive posts 101 are disposed on a first region R1 of the upper surface S1 of the first redistribution structure 102, the first region R1 being adjacent to a first sidewall of the first redistribution structure 102, and wherein the second semiconductor chip 100 is disposed on a second region R2 of the upper surface S1 of the first redistribution structure 102, the second region R2 being adjacent to a second sidewall, opposite to the first sidewall, of the first redistribution structure 102 (see annotated Fig. 2).
Regarding Claim 16, Pan et al. teaches the semiconductor package of claim 9, further comprising: a plurality of first bumps B1 disposed on a lower surface S2 of the first redistribution structure 102, and electrically connected to at least one of the first and second semiconductor chips 200’, 100, wherein the first and second semiconductor chips 200’, 100 are electrically connected with each other through the first redistribution structure 102 (see annotated Fig.2: B1, S2, 102, 100, 200’, paragraph 0025, 0046).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20220344304 A1), in view of Liao et al. (US 20230386988 A1) and Chen et al. (US 20190103386 A1), as applied to Claim 9 above, further in view of Jang (US 20160118366 A1).
The combination of Pan et al., Liao et al. and Chen et al. fails to teach the semiconductor package of claim 9, wherein a portion of the first semiconductor chip 200’ overlaps the second semiconductor chip 100 in the first direction Z.
However, Jang teaches a semiconductor package, wherein a portion of the first semiconductor chip 200 overlaps the second semiconductor chip 100 in the first direction Z (vertical direction Z) (Fig. 1B: 200, 100, paragraph 0050).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of Pan et al. and Jang in order to have a portion of the first semiconductor chip overlap a portion of the second semiconductor chip in the first direction. Doing so would minimize the semiconductor package footprint as overlapping dies can reduce the area of the package.
Claims 13 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20220344304 A1), in view of Liao et al. (US 20230386988 A1) and Chen et al. (US 20190103386 A1), as applied to Claim 9 above, further in view of Choi et al. (US 20210005527 A1).
The combination of Pan et al., Liao et al. and Chen et al. fails to teach the semiconductor package of claim 9, further comprising: a third semiconductor chip disposed between the second semiconductor chip and the second redistribution structure, and encapsulated by the encapsulant.
However, Choi et al. discloses a semiconductor package comprising a third semiconductor chip 200b disposed on a second semiconductor chip 200a, and encapsulated by an encapsulant 148 (Fig. 1: 200a, 200b, 148, paragraph 0026, 0029, 0040).
Therefore, a person of ordinary skill in the art, using the combined the teachings of Pan et al., Chen et al. and Choi et al. would have disposed the third semiconductor chip of Choi et al. in the semiconductor package of Pan et al./Chen et al. in order to come up with the claimed invention. Doing so would enable a semiconductor packaging structure with vertically stacked die having a smaller footprint.
Furthermore, a person of ordinary skill in the art would have recognized that when the third semiconductor chip of Choi et al. is disposed in the semiconductor package of Pan et al./Chen et al., the third semiconductor chip will be disposed between the second semiconductor chip and the second redistribution structure of Pan et al./Chen et al.
Regarding Claim 14, Choi et al. teaches the semiconductor package of claim 13, wherein the encapsulant 148 covers a sidewall of the third semiconductor chip 200b without covering an upper surface 200bS1 of the third semiconductor chip 200b, and wherein the upper surface 200bS1 of the third semiconductor chip 200b is adjacent to the heat dissipation member 170, and a lower surface 200bS2 of the third semiconductor chip 200b is adjacent to an upper surface 200aS1 of the second semiconductor chip 200a (see Fig. 1: 200bS1, 200bS2, 200aS1, 148, 200b, 170, 200a).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20220344304 A1), in view of Liao et al. (US 20230386988 A1) and Chen et al. (US 20190103386 A1), as applied to Claim 9 above, further in view of Refai-Ahmed et al. (US 20210193620 A1).
The combination of Pan et al., Liao et al. and Chen et al. fails to disclose the semiconductor package of claim 9, further comprising: a plurality of second conductive posts disposed between the second semiconductor chip and the second redistribution structure, wherein the plurality of second conductive posts extend from the second semiconductor chip to the second redistribution structure in the first direction, and wherein the plurality of second conductive posts thermally connect the second semiconductor chip to the heat dissipation member.
However, Refai-Ahmed et al. discloses a semiconductor package comprising a plurality of second conductive posts 110 disposed between the second semiconductor chip 106 and the heat dissipation member 102, wherein the plurality of second conductive posts 110 extend from the heat dissipation 102 member toward the second semiconductor chip 106 in the first direction (vertical direction Z), and wherein the plurality of second conductive posts 110 thermally connect the second semiconductor chip 106 to the heat dissipation member 102 (Fig. 1: 110, 106, 102, paragraph 0019, 0020, 0024).
Therefore, a person of ordinary skill in the art, using the combined the teachings of Pan et al., Chen et al. and Refai-Ahmed et al. would have disposed plurality of second conductive posts of Refai-Ahmed et al. in the semiconductor package of Pan et al. in order to come up with the claimed invention. Doing so would provide efficient heat transfer paths that facilitate the extraction of heat out of the semiconductor package, as recognized by Refai-Ahmed et al. (paragraph 0024).
Refai-Ahmed et al. fails to explicitly teach the plurality of second conductive posts are disposed between the second semiconductor chip and a second redistribution structure, wherein the plurality of second conductive posts extend from the second semiconductor chip to the second redistribution structure in the first direction.
However, a person of ordinary skill in the art would have recognized that when the plurality of second conductive posts of Refai-Ahmed et al. is disposed in the semiconductor package of Pan et al./Chen et al., the plurality of second conductive posts will be disposed between the second semiconductor chip and the second redistribution structure of Pan et al./Chen et al., wherein the plurality of second conductive posts would extend from the second semiconductor chip to the second redistribution structure in the first direction.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20220344304 A1), in view of Liao et al. (US 20230386988 A1) and Choi et al. (US 20210005527 A1).
Regarding Claim 18, Pan et al. teaches a semiconductor package comprising:
a first redistribution structure 102 in which at least one first redistribution layer 103 and at least one first insulating layer 104 are alternately stacked (see annotated Fig. 2: 102, 103, 104, paragraph 0010);
a first semiconductor chip 200’ disposed on an upper surface S1 of the first redistribution structure 102 (see annotated Fig. 2: 200’, S1, 102, paragraph 0022);
Note that the entire device structure PK2 of Fig. 2, including the two semiconductor chips 200, interposer substrate 202 and the encapsulant E2 is interpreted as the first semiconductor chip 200’ as highlighted by the rectangle in annotated Fig. 2.
an encapsulant E1 disposed between the first redistribution structure 102 and the first semiconductor chip 200’ (see annotated Fig. 2: E1, 102, 200, paragraph 0017);
a plurality of first conductive posts 101 electrically connecting the first redistribution structure 102 and the first semiconductor chip 200’ with each other, and penetrating through the encapsulant E1 in a first direction Z perpendicular to the upper surface S1 of the first redistribution structure 102 (see annotated Fig. 2: 101, 102, 200, E1, Z, paragraph 0011);
a heat dissipation member 304 having at least a portion that overlaps the first semiconductor chip 200’ in a second direction X that is perpendicular to the first direction Z and is parallel to the upper surface S1 of the first redistribution structure 102 (see annotated Fig. 2: 304, X, Z, paragraph 0030);
a second semiconductor chip 100 (right chip of the two chips 100) having at least a portion disposed between the first redistribution structure 102 and the heat dissipation member 304, and encapsulated by the encapsulant E1 (see annotated Fig. 2: 100, 102, 304, E1, paragraph 0012);
and a plurality of first bumps B1 disposed on a lower surface S2 of the first redistribution structure 102, and electrically connected to at least one of the first and second semiconductor chips 200’, 100, wherein the first and second semiconductor chips 200’, 100 are electrically connected with each other through the first redistribution structure 102 (see annotated Fig.2: B1, S2, 102, 100, 200’, paragraph 0025, 0046).
wherein the plurality of first conductive posts 101 are disposed on a first region R1 of the upper surface S1 of the first redistribution structure 102 in the second direction X when viewed in a plan view, the first region R1 being adjacent to a first sidewall of the first redistribution structure 102, and wherein the second semiconductor chip 100 is disposed on a second region R2 of the upper surface S1 of the first redistribution structure 102, the second region R2 being adjacent to a second sidewall, opposite to the first sidewall, of the first redistribution structure 102 (see annotated Fig. 2).
Pan et al. fails to teach the plurality of first conductive posts 102 are periodically disposed, and disposed in a third direction when viewed in a plan view, the third direction being parallel to the upper surface of the first redistribution structure and perpendicular to the second direction, a third semiconductor chip disposed between the second semiconductor chip and the heat dissipation member, and encapsulated by the encapsulant.
However, Liao et al. teaches a semiconductor package comprising a plurality of conductive posts 115b, wherein the plurality of first conductive posts 115b are periodically disposed on a first region of the upper surface 104 of the first redistribution structure 103 in the second direction hd1 and a third direction hd2 when viewed in a plan view, the third direction hd2 being parallel to the upper surface 104 of the first redistribution structure 103 and perpendicular to the second direction hd1 (see Fig. 7A: 103, 104, 115b, Fig. 7B: 115b, hd1, hd2, 104, paragraph 0053, 0097).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of Pan et al. and Liao et al. in order to have the plurality of first conductive posts periodically disposed, and disposed in a third direction when viewed in a plan view, the third direction being parallel to the upper surface of the first redistribution structure and perpendicular to the second direction. Doing so would allow for more efficient routing of signals enabled by the 2D array of conductive posts as well as improve the structural stability of the semiconductor package.
Furthermore, Choi et al. discloses a semiconductor package comprising a third semiconductor chip 200b disposed between a second semiconductor chip 200a and a heat dissipation member 170, and encapsulated by an encapsulant 148 (Fig. 1: 200a, 200b, 170, 148, paragraph 0026, 0029, 0040).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of Pan et al. and Choi et al. in order to have a third semiconductor chip disposed between the second semiconductor chip and the heat dissipation member, and encapsulated by the encapsulant. Doing so would enable a semiconductor packaging structure with vertically stacked die having a smaller footprint.
Regarding Claim 19, the combination of Pan et al. and Choi et al teaches the semiconductor package of claim 18,
wherein the first semiconductor chip 200’ overlaps the plurality of first conductive posts 101 in the first direction Z (as taught by Pan et al., see annotated Fig. 2), wherein the first semiconductor chip 200’ does not overlap the second semiconductor chip 100 in the first direction Z (as taught by Pan et al., see annotated Fig. 2),
wherein the encapsulant 148 covers a sidewall of the third semiconductor chip 200b without covering an upper surface 200bS1 of the third semiconductor chip 200b, and wherein the upper surface 200bS1 of the third semiconductor chip 200b is adjacent to the heat dissipation member 170, and a lower surface 200bS2 of the third semiconductor chip 200b is adjacent to an upper surface 200aS1 of the second semiconductor chip 200a (as taught by Choi et al., see Fig. 1: 200bS1, 200bS2, 200aS1, 148, 200b, 170, 200a).
Furthermore, a person of ordinary skill in the art would have recognized that when the third semiconductor chip of Choi et al. is disposed in the semiconductor package of Pan et al., the first semiconductor chip 200’ of Pan et al. will not overlap the third semiconductor chip of Choi et al. in the first direction Z.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (US 20220344304 A1), in view of Liao et al. (US 20230386988 A1) and Choi et al. (US 20210005527 A1), as applied to Claim 18 above, further in view of Chen et al. (US 20190103386 A1) and Jang (US 20160118366 A1).
Pan et al. teaches the semiconductor package of claim 18, wherein a size W3 of a lower surface of the heat dissipation member 304 adjacent to the second semiconductor chip 100 is smaller than a size W4 of a lower surface of the first semiconductor chip 200’ adjacent to the plurality of first conductive posts 101 (see annotated Fig. 2: W3, W4).
The combination of Pan et al., Liao et al. and Choi et al fails to teach the semiconductor package of claim 18, further comprising: a second redistribution structure disposed between the second semiconductor chip and the heat dissipation member, wherein the second redistribution structure includes at least one second redistribution layer and at least one second insulating layer that are alternately stacked on each other, wherein a portion of the first semiconductor chip overlaps a portion of the second semiconductor chip in the first direction.
However, Chen et al. discloses a semiconductor package comprising a first redistribution structure 38, 40, 42 includes at least one first redistribution layer 38, 40 and at least one first insulating layer 42 that are alternately stacked on each other, and a second redistribution structure 16, 20 disposed between the second semiconductor chip 24 and an electronic device 46, wherein the second redistribution structure 16, 20 includes at least one second redistribution layer 16 and at least one second insulating layer 20 that are alternately stacked on each other (Fig. 1A: 38, 40, 42, 16, 20, 24, 46, paragraph 0069, 0070, 0071).
Therefore, a person of ordinary skill in the art, using the combined the teachings of Pan et al., Chen et al. and Choi et al., would have disposed the second redistribution structure of Chen et al. in the semiconductor package of Pan et al./Choi et al. in order to come up with the claimed invention. Doing so, would enable design flexibility allowing for more elements such as the heat dissipation member to be integrated efficiently into the semiconductor package.
Furthermore, a person of ordinary skill in the art would have recognized that when the second redistribution structure of Chen et al. is disposed in the semiconductor package of Pan et al., the second redistribution structure will be disposed between the second semiconductor chip and the heat dissipation member of Pan et al.
Jang teaches a semiconductor package, wherein a portion of the first semiconductor chip 200 overlaps a portion of the second semiconductor chip 100 in the first direction Z (vertical direction Z) (Fig. 1B: 200, 100, paragraph 0050).
Therefore, a person of ordinary skill in the art, before the effective filing date of the claimed invention, would have combined the teachings of Pan et al. and Jang in order to have a portion of the first semiconductor chip overlap a portion of the second semiconductor chip in the first direction. Doing so would minimize the semiconductor package footprint as overlapping dies can reduce the area of the package.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817 04/09/2026
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 April 15, 2026
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