DETAILED ACTION
Examiner’s Note
The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Election/Restrictions
Applicant’s election without traverse of species A/figs. 2A-2B, 3, reflected in claims 68-79 and 81-89 in the reply filed on 03/03/2026 is acknowledged. Claim 80 is cancelled.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 72-73 and 78 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 72 recites, “The monolithic multi-FET transistor of claim 71, wherein (i) the two of the plurality of FETs comprises the common drain and the common drain extends over a common isolation structure separating the separate FET portions, (ii) the two of the plurality of FETs comprises the common source and the common source extends over a common isolation structure separating the separate FET portions, or both (i) and (ii)”. The two alternatives linked by “or” are same i.e., both (i) and (ii). For examination, the claim will be considered as below:
72. The monolithic multi-FET transistor of claim 71, wherein at least one of (i) the two of the plurality of FETs comprises the common drain and the common drain extends over a common isolation structure separating the separate FET portions, (ii) the two of the plurality of FETs comprises the common source and the common source extends over a common isolation structure separating the separate FET portions, or both (i) and (ii).
Claim 73 recites, “the gates are electrically connected by a gate conductor, the drains are electrically connected by a drain conductor, and the sources are electrically connected by a source conductor”. This is not understood, from the claim language, to which element, the gates, the drains and the sources are connected to by a gate conductor, a drain conductor and a source conductor respectively. For examination purpose, the claim will be considered as below:
73. The monolithic multi-FET transistor of claim 71, wherein each of the plurality of FETs comprises a gate, a drain, and a source and the gates are electrically connected to a gate conductor, the drains are electrically connected to a drain conductor, and the sources are electrically connected to a source conductor.
Claim 78 recites the limitation "the dielectric" in line 3. There is insufficient antecedent basis for this limitation in the claim. For examination purpose, the limitation will be replaced by, “the gate dielectric”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 68-79 and 81-84 are rejected under 35 U.S.C. 103 as being unpatentable over Horiuchi (US 20020195623 A1, hereinafter Horiuchi‘623) in view of Campbell et al. (US 20020185684 A1, hereinafter campbell‘684).
Regarding independent claim 68, Horiuchi‘623 teaches, “A monolithic multi-FET transistor (fig. 1-43; ¶ [0081] - ¶ [0233]), comprising:
a substrate (1, 2, 3, fig. 16) comprising a patterned single-crystalline semiconductor ((epitaxial)) layer (3, 31, ‘SOI layer’, ‘single crystalline Si layer’, ¶ [0141], ¶ [0173]) defining separate FET portions (separated by isolation structure 4); and
a plurality of FETs (see annotation) disposed on the substrate, wherein each of the plurality of FETs comprises one of the separate FET portions”.
But Horiuchi‘623 is silent upon the provision of wherein the device layer is an epitaxial layer.
However, campbell‘684 teaches a similar device (fig. 4E), wherein the device layer (403) is an epitaxial single-crystalline layer (¶ [0067]).
Horiuchi‘623 and campbell‘684 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Horiuchi‘623 with the features of campbell‘684 because they are from the same field of endeavor.
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It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Horiuchi‘623 and campbell‘684 to prepare device layer as epitaxial layer according to the teachings of campbell‘684 with a motivation of exploiting the advantages of the epitaxial layer e.g., controllable thickness and uniformity, precise doping control, superior crystal quality etc.
Regarding claim 69, Horiuchi‘623 modified with campbell‘684 further teaches, “The monolithic multi-FET transistor of claim 68, wherein the separate FET portions of the epitaxial layer (3, 31, Horiuchi‘623) are isolated by a common isolation structure (4)”.
Regarding claim 70, Horiuchi‘623 modified with campbell‘684 further teaches, “The monolithic multi-FET transistor of claim 69, wherein the isolation structure (4, Horiuchi‘623) is a patterned isolation structure extending through the epitaxial layer (3, 31)”.
Regarding claim 71, Horiuchi‘623 modified with campbell‘684 further teaches, “The monolithic multi-FET transistor of claim 68, wherein at least one of (i) two of the plurality of FETs comprise a common drain (22, fig. 16, Horiuchi‘623), and (ii) two of the plurality of FETs comprise a common source”.
Regarding claim 72, Horiuchi‘623 modified with campbell‘684 further teaches, “The monolithic multi-FET transistor of claim 71, wherein at least one of (i) the two of the plurality of FETs comprises the common drain (22, fig. 16, Horiuchi‘623) and the common drain extends over a common isolation structure separating the separate FET portions, (ii) the two of the plurality of FETs comprises the common source and the common source extends over a common isolation structure separating the separate FET portions, or both (i) and (ii)”
Regarding claim 73, Horiuchi‘623 modified with campbell‘684 further teaches, “The monolithic multi-FET transistor of claim 71, wherein each of the plurality of FETs comprises a gate (61, fig. 16, Horiuchi‘623), a drain (101), and a source (102) and the gates (61, fig. 26) are electrically connected to a gate conductor (172), the drains (101, fig. 16) are electrically connected to a drain conductor (161), and the sources (102) are electrically connected to a source conductor (15)”.
Regarding claim 74, Horiuchi‘623 modified with campbell‘684 further teaches, “The monolithic multi-FET transistor of claim 68, wherein the substrate (1, 2, 3, fig. 16, Horiuchi‘623) comprises an insulating layer (2) and the patterned epitaxial layer (3) is disposed on the insulating layer (2)”.
Regarding claim 75, Horiuchi‘623 modified with campbell‘684 further teaches, “The monolithic multi-FET transistor of claim 74, wherein the substrate (1, 2, 3, fig. 16, Horiuchi‘623) comprises a bulk semiconductor layer (1) and the insulating layer (2) is disposed on the bulk semiconductor layer (1)”.
Regarding claim 76, Horiuchi‘623 modified with campbell‘684 further teaches, “The monolithic multi-FET transistor of claim 68, wherein the substrate (1, 2, 3, fig. 16, Horiuchi‘623) is a silicon-on-insulator (SOI) substrate (¶ [0173])”.
Regarding claim 77, Horiuchi‘623 modified with campbell‘684 further teaches, “The monolithic multi-FET transistor of claim 68, wherein each of the plurality of FETs comprises a gate (61, fig. 16, Horiuchi‘623), a gate dielectric (between gate 61 and channel 3/31), a source (9, 102), a drain (10, 101) and the one of the separate FET portions”.
Regarding claim 78, Horiuchi‘623 modified with campbell‘684 further teaches, “The monolithic multi-FET transistor of claim 77, wherein the gate dielectric (fig. 16, Horiuchi‘623) spans the one of the separate FET portions and the source (9, 102) is disposed on a first side of the gate dielectric and the drain (10, 101) is disposed on an opposing second side of the gate dielectric”.
Regarding claim 79, Horiuchi‘623 modified with campbell‘684 further teaches, “The monolithic multi-FET transistor of claim 78, wherein ends of the gate dielectric (fig. 16, Horiuchi‘623) are disposed on (see note below) an isolation structure (4) surrounding (at least partially) the one of the separate FET portions”.
Note: the term “ON” in the instant claim is explained using broadest reasonable interpretation. “ON” is a directional phrase, meaning an object can be above or bottom or left or right of another object with or without other objects in between. Also, the object can be in direct contact with or near or next to or adjacent to or covering the another object.
Regarding claim 81, Horiuchi‘623 modified with campbell‘684 further teaches, “A monolithic multi-FET transistor system, comprising a first monolithic multi-FET transistor of claim 68 and a second monolithic multi-FET transistor of claim 68, wherein each of the FETs of the first monolithic multi-FET transistor and each of the FETs of the second monolithic multi-FET transistor comprises a respective gate (61, fig, 16, Horiuchi‘623), a respective source (9, 102), and a respective drain (10, 101)”.
Regarding claim 82, Horiuchi‘623 modified with campbell‘684 further teaches, “A monolithic multi-FET transistor 82. The monolithic multi-FET transistor system of claim 81, wherein the substrate (1, 2, 3, fig. 16, Horiuchi‘623) of the first monolithic multi-FET transistor is separate from the substrate (1, 2, 31) of the second monolithic multi-FET transistor”.
Regarding claim 83, Horiuchi‘623 modified with campbell‘684 further teaches, “The monolithic multi-FET transistor system of claim 81, wherein the second monolithic multi-FET transistor is non-native (distinct) to the first monolithic multi-FET transistor (fig. 16, Horiuchi‘623)”.
Regarding claim 84, Horiuchi‘623 modified with campbell‘684 further teaches, “The monolithic multi-FET transistor system of claim 81, wherein one or more of (i) the respective sources of two of the FETs of the first monolithic multi-FET transistor are a common source, (ii) the respective drains of two of the FETs of the first monolithic multi-FET transistor are a common drain (22, fig. 16, Horiuchi‘623), (iii) the respective sources of two of the FETs of the second monolithic multi-FET transistor are a common source, and (iv) the respective drains of two of the FETs of the second monolithic multi-FET transistor are a common drain”.
Claims 85-89 are rejected under 35 U.S.C. 103 as being unpatentable over Horiuchi (US 20020195623 A1, hereinafter Horiuchi‘623) and campbell‘684 as applied to claim 68 as above, and further in view of Huang (US 7362081 B1, hereinafter Huang‘081).
Regarding claim 85, Horiuchi‘623 modified with campbell‘684 teaches all the limitations described in claim 68.
But Horiuchi‘623 modified with campbell‘684 is silent upon the provision of wherein a monolithic multi-FET transistor system, comprising: a monolithic multi-FET transistor according to claim 68; a multi-FET controller disposed on the monolithic multi-FET transistor; and one or more electrical conductors electrically connecting the multi-FET controller to the monolithic multi-FET transistor, the multi-FET controller operable to control the multi-FET transistor.
However, Huang‘081 teaches a device, wherein a monolithic multi-FET transistor system, comprising: a monolithic multi-FET transistor according to claim 68; a multi-FET controller (120, fig. 2) disposed on the monolithic multi-FET transistor (122, 136); and one or more electrical conductors electrically connecting the multi-FET controller to the monolithic multi-FET transistor, the multi-FET controller operable to control the multi-FET transistor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Horiuchi‘623 modified with campbell‘684 and Huang‘081 to include control circuits according to the teachings of Huang‘081 with a general motivation to control the FETs to guide those to function as expected.
Regarding claim 86, Horiuchi‘623 modified with campbell‘684 and Huang‘081 further teaches, “The monolithic multi-FET transistor system of claim 85, wherein the multi-FET controller comprises a substrate comprising a semiconductor material that is different from a semiconductor material in the substrate of the monolithic multi-FET transistor (per fig. 2 of Huang‘081, multi-FET controller 120 and the multi-FETs 122, 136 etc. are distinct)”.
Regarding claim 87, Horiuchi‘623 modified with campbell‘684 and Huang‘081 further teaches, “The monolithic multi-FET transistor system of claim 86, wherein the semiconductor material in the substrate (1, silicon, fig. 16, Horiuchi‘623) of the monolithic multi-FET transistor is a semiconductor material of the epitaxial layer (3, 31)”.
Regarding claim 88, Horiuchi‘623 modified with campbell‘684 and Huang‘081 further teaches, “ The monolithic multi-FET transistor system of claim 85, wherein the substrate of the monolithic multi-FET transistor comprises a bulk semiconductor layer and the semiconductor material in the substrate of the monolithic multi-FET transistor is a semiconductor material of a bulk semiconductor layer (1, 3, 31, silicon, fig. 16, Horiuchi‘623)”.
Regarding claim 89, Horiuchi‘623 modified with campbell‘684 and Huang‘081 further teaches, “The monolithic multi-FET transistor system of claim 85, wherein the multi-FET controller is non-native to the monolithic multi-FET transistor (per fig. 2 of Huang‘081, multi-FET controller 120 and the multi-FETs 122, 136 etc. are distinct)”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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