Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
Claim(s) 1-14 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zhu (PGPub No. 20180175060) in further view of Morrow (PGPub No. 20220028779).
Regarding claim 1, Zhu teaches a semiconductor device, comprising a plurality of logic cells, wherein each logic cell of the plurality of logic cells includes: a plurality of first conductive lines and a plurality of first power lines (Fig. 2A points to a standard cell circuit 202 comprising routing lines/tracks 224/226 (first conductive lines) and voltage lines 204 and 206 (first power lines).), a plurality of second conductive lines on the plurality of first conductive lines and the plurality of first power lines (Id. points to metal lines 212 (second conductive lines).), and a plurality of third conductive lines and a plurality of second power lines on the plurality of second conductive lines (Figs. 2B-2C and [0005] point to a third metal layer M2 comprising metal shunts 208 and 210 (second power lines) and additional metal lines (third conductive lines) which can be dedicated to interconnecting the gates of the active devices.), wherein: the plurality of first conductive lines, the plurality of first power lines, the plurality of third conductive lines, and the plurality of second power lines extend in a first direction, the plurality of second conductive lines extend in a second direction crossing the first direction (Figs. 2A-2C point to metal layers M0, M1, and M2.), locations at which the plurality of first conductive lines and the plurality of second conductive lines overlap are first hit points, and each first hit point is a location at which one of the plurality of first conductive lines and one of the plurality of second conductive lines are able to be connected, except that one or more of locations of overlap between the plurality of first conductive lines and the plurality of second conductive lines that are adjacent to one of the plurality of separation areas are not hit points (Figs. 2B-2C point to vias 232 and 240 (first hit points) which only connect specific metal lines (second conductive lines) 212(3) and 212(7). It is considered obvious that the vias/hit points would not be adjacent to any separation area in order to avoid damaging the component.).
Zhu fails to teach a plurality of separation areas separate adjacent second conductive lines of the plurality of second conductive lines in the second direction, each separation area located adjacent to a boundary of two adjacent logic cells in the second direction, for the boundary between two adjacent logic cells in the second direction, a corresponding set of separation areas of the plurality of separation areas are alternately positioned at a lower side and an upper side relative to the boundary so as to be disposed in a zigzag form.
Morrow teaches a plurality of separation areas separate adjacent second conductive lines of the plurality of second conductive lines in the second direction, each separation area located adjacent to a boundary of two adjacent logic cells in the second direction, for the boundary between two adjacent logic cells in the second direction, a corresponding set of separation areas of the plurality of separation areas are alternately positioned at a lower side and an upper side relative to the boundary so as to be disposed in a zigzag form (Figs. 5A-6B and [0042] point to various layouts of cells 301 and/or 302 comprising laterally offset (zigzag) tracks 170.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Zhu and Morrow, such that a plurality of separation areas is disposed in a zigzag form in order to employ complementary standard cell layouts which can replicate a netlist with different block-level layouts, assuming the cells are netlist equivalents.
Regarding claim 2, Zhu teaches wherein: locations at which the plurality of second conductive lines and the plurality of third conductive lines overlap are second hit points, each second hit point being a location at which one of the plurality of second conductive lines and one of the plurality of third conductive lines are connected, except one or more locations of overlap between the plurality of second conductive lines and the plurality of third conductive lines that are adjacent to one of the separation areas are not hit points (Fig. 2B-2C point to vias 234 and 242 (second hit points) which only connect specific metal lines (second conductive lines) 212(3) and 212(7).).
Regarding claim 3, Zhu in combination with Morrow teaches wherein: each of the plurality of first power lines coincides with a respective boundary between two adjacent logic cells in the second direction (Fig. 2A of Zhu points to voltage rails 204 and 206 (plurality of first power lines) and a total height HCELL (boundary).), and separation areas of the plurality of separation areas alternately overlap a lower edge and an upper edge of one of the plurality of first power lines to be disposed in a zigzag form (Figs. 5A-6B and [0042] point to various layouts of cells 301 and/or 302 comprising laterally offset (zigzag) tracks 170.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Zhu and Morrow, such that each of the plurality of separation areas coincides with the plurality of first power lines in order to maintain a degree of separation between adjacent cells while still providing a common voltage.
Regarding claim 4, Zhu teaches wherein: a width of each of the plurality of first power lines is greater than a width of each of the plurality of first conductive lines (Fig. 1 points to an alternative embodiment of a standard cell circuit 102 comprising widths WRAIL and WLINE.).
Regarding claim 5, Zhu in combination with Morrow teaches wherein: each second power line of the plurality of second power lines coincides with a respective boundary between two adjacent logic cells in the second direction (Fig. 2A of Zhu points to metal shunts 208 and 210 (plurality of second power lines) and a total height HCELL (boundary).), and a set of separation areas of the plurality of separation areas are alternately positioned on opposite sides of the boundary and partially overlap a respective second power line at a lower side and an upper side, so the set of separation areas is disposed in a zigzag form (Figs. 5A-6B and [0042] point to various layouts of cells 301 and/or 302 comprising laterally offset (zigzag) tracks 170.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Zhu and Morrow, such that each of the plurality of separation areas coincides with the plurality of second power lines in order to maintain a degree of separation between adjacent cells while still providing a common voltage.
Regarding claim 6, Zhu teaches wherein: a width of each of the plurality of second power lines is substantially the same as a width of each of the plurality of third conductive lines (Fig. 2A points to metal shunts 208 and 210 (plurality of second power lines) and width(s) WLINE.).
Regarding claim 7, Morrow teaches wherein: for each logic cell: a disposition form of a first set of separation areas of the plurality of separation areas adjacent to an upper edge of the logic cell and a disposition form of a second set of separation areas of the plurality of separation areas adjacent to a lower edge of the logic cell are substantially the same (Figs. 5A-6B and [0042] point to various layouts of cells 301 and/or 302 comprising laterally offset (zigzag) tracks 170. It is considered obvious that the separation areas adjacent to the upper edge would be disposed in the same form as the areas adjacent to the lower edge in order to better complement the layouts of adjacent cells and allow for any combination of said cells.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Zhu and Morrow, such that the plurality of separation areas is disposed substantially the same along the upper and lower edges of the logic cell in order to employ complementary standard cell layouts which can replicate a netlist with different block-level layouts, assuming the cells are netlist equivalents.
Regarding claim 8, Zhu teaches wherein: the plurality of second conductive lines comprises a second conductive line positioned at and along a first column and a second conductive line positioned at and along a second column, the number of the first hit points overlapping the second conductive line positioned at the first column is the same as the number of the first hit points overlapping the second conductive line positioned at the second column, and the number of second hit points overlapping the second conductive line positioned at the first column is the same as the number of second hit points overlapping the second conductive line positioned at the second column (Figs. 2A-2C point to metal lines 212(3) (first column) and 212(7) (second column).).
Regarding claim 9, Zhu teaches wherein: within each logic cell, each of the plurality of second conductive lines overlaps five first conductive lines and five third conductive lines, and each of the plurality of second conductive lines has four first hit points and four second hit points (Figs. 2A-2C point to metal lines 212 (second conductive lines). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the number of overlaps, first hit points, and second hit points to be a result effective variable affecting the interconnect density of the logic cell. Thus, it would have been obvious to modify the device of Zhu to have the total number of overlaps, first hit points, and second hit points within the claimed range(s) in order to increase the number of interconnects while still maintaining control over the specific paths formed, and since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05(II)(B) and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.).
Regarding claim 10, Morrow teaches wherein for each logic cell: a disposition form of a first set of the separation areas of the plurality of separation areas arranged adjacent to an upper edge of the logic cell of the plurality of logic cells and a disposition form of a second set of the separation areas of the plurality of separation areas second conductive line arranged adjacent to a lower edge of the logic cell are symmetrical to each other (Figs. 5A-6B and [0042] point to various layouts of cells 301 and/or 302 comprising laterally offset (zigzag) tracks 170. It is considered obvious that the separation areas adjacent to the upper edge would be disposed symmetrically to the areas adjacent to the lower edge in order to better complement the layouts of adjacent cells and allow for any combination of said cells.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Zhu and Morrow, such that the plurality of separation areas is disposed symmetrically according to the upper and lower edges of the logic cell in order to employ complementary standard cell layouts which can replicate a netlist with different block-level layouts, assuming the cells are netlist equivalents.
Regarding claim 11, Zhu teaches wherein: the plurality of second conductive lines comprises a second conductive line positioned at and along a first column and a second conductive line positioned at and along a second column, the number of the first hit points overlapping the second conductive line positioned at the first column is different from the number of first hit points overlapping the second conductive line positioned at the second column, and the number of the second hit points overlapping the second conductive line positioned at the first column is different from the number of second hit points overlapping the second conductive line positioned at the second column (Figs. 2A-2C point to metal lines 212(3) (first column) and 212(7) (second column). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the number first hit points and second hit points corresponding to the first and second columns to be a result effective variable affecting the interconnect density of the logic cell. Thus, it would have been obvious to modify the device of Zhu to have the total number first hit points and second hit points within the claimed range(s) in order to maintain control over signal communication by establishing specific paths that correspond to the first and/or second columns, and since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05(II)(B) and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.).
Regarding claim 12, Zhu teaches wherein: within each logic cell, each of the plurality of second conductive lines overlaps five first conductive lines and five third conductive lines, each second conductive line of some of the plurality of second conductive lines overlap three first hit points and three second hit points, and each second conductive line of a remainder of the plurality of second conductive lines overlap five first hit points and five second hit points (Figs. 2A-2C point to metal lines 212 (second conductive lines). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized the number of overlaps, first hit points, and second hit points to be a result effective variable affecting the interconnect density of the logic cell. Thus, it would have been obvious to modify the device of Zhu to have the total number of overlaps, first hit points, and second hit points within the claimed range(s) in order to increase the number of interconnects while still maintaining control over the specific paths formed, and since optimum or workable ranges of such variables are discoverable through routine experimentation. See MPEP 2144.05(II)(B) and 2143. Furthermore, it has also been held that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936, (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.).
Regarding claim 13, Zhu teaches wherein: for each logic cell: a primary first power line of the plurality of first power lines is positioned along an upper side of the boundary and a secondary first power line of the plurality of first power lines is positioned along a lower side of the boundary of the logic cell, a primary second power line of the plurality of second power lines is positioned along the upper side of the boundary and a secondary second power line of the plurality of second power lines is positioned along the lower side of the boundary of the logic cell (Fig. 2A points to the first voltage rail 204 (primary first power line), second voltage rail 206 (secondary first power line), first metal shunt 208 (primary second power line), and second metal shunt 210 (secondary second power line).).
Zhu fails to teach a first set of separation areas of the plurality of separation areas alternately overlaps the primary and secondary first power lines so as to be disposed in a zigzag shape and a second set of separation areas of the plurality of separation areas alternately overlaps the primary and secondary second power lines so as to be disposed in a zigzag shape (Figs. 5A-6B and [0042] point to various layouts of cells 301 and/or 302 comprising laterally offset (zigzag) tracks 170. It is considered obvious that this offset is also created in any underlying layer(s) (first set of separation areas) and overlying layer(s) (second set of separation areas) so as to create a full disconnect that clearly separates adjacent cells.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Zhu and Morrow, such that a plurality of separation areas is disposed in a zigzag form in order to employ complementary standard cell layouts which can replicate a netlist with different block-level layouts, assuming the cells are netlist equivalents.
Regarding claim 14, Zhu teaches wherein: at least one of the plurality of second conductive lines is a single wire connected along the second direction (Fig. 2A points to metal lines 212 (second conductive lines). It is considered obvious that “wire” and “conductive line” are interchangeable terms referring to an electrical path between two components.).
Regarding claim 16, Zhu teaches a semiconductor device, comprising a plurality of logic cells, wherein each logic cell of the plurality of logic cells includes: a plurality of first conductive lines and a plurality of first power lines (Fig. 2A points to a standard cell circuit 202 comprising routing lines/tracks 224/226 (first conductive lines) and voltage lines 204 and 206 (first power lines).), a plurality of second conductive lines disposed on the plurality of first conductive lines and on the plurality of first power lines (Id. points to metal lines 212 (second conductive lines).), and a plurality of third conductive lines and a plurality of second power lines disposed on the plurality of second conductive lines(Figs. 2B-2C and [0005] point to a third metal layer M2 comprising metal shunts 208 and 210 (second power lines) and additional metal lines (third conductive lines) which can be dedicated to interconnecting the gates of the active devices), wherein: the plurality of first conductive lines, the plurality of first power lines, the plurality of third conductive lines, and the plurality of second power lines extend in a first direction, the plurality of second conductive line extend in a second direction crossing the first direction (Figs. 2A-2C point to metal layers M0, M1, and M2.), and locations at which the plurality of second conductive lines and the plurality of third conductive lines overlap have hit points to which one of the plurality of second conductive lines and one of the plurality of third conductive lines are connected, but no hit points are included at locations adjacent to the separation area of the plurality of second conductive lines (Figs. 2B-2C point to vias 234 and 242 (hit points). It is considered obvious that the vias/hit points would not be adjacent to any separation area in order to avoid damaging the component.).
Zhu fails to teach a plurality of separation areas separating adjacent second conductive lines of the plurality of second conductive lines, each of the plurality of separation areas is disposed adjacent to a boundary of between two adjacent logic cells in the second direction, and for each boundary between two adjacent cells, separation areas of the plurality of separation areas are alternately positioned at a lower side and an upper side of the boundary so as to be disposed in a zigzag form.
Morrow teaches a plurality of separation areas separating adjacent second conductive lines of the plurality of second conductive lines, each of the plurality of separation areas is disposed adjacent to a boundary of between two adjacent logic cells in the second direction, and for each boundary between two adjacent cells, separation areas of the plurality of separation areas are alternately positioned at a lower side and an upper side of the boundary so as to be disposed in a zigzag form (Figs. 5A-6B and [0042] point to various layouts of cells 301 and/or 302 comprising laterally offset (zigzag) tracks 170.). Thus, it would have been obvious to a person of ordinary skill in the art (POSITA) prior to the filing date of the claimed invention to combine the teachings of Zhu and Morrow, such that a plurality of separation areas is disposed in a zigzag form in order to employ complementary standard cell layouts which can replicate a netlist with different block-level layouts, assuming the cells are netlist equivalents.
Regarding claim 17, Zhu teaches wherein: a disposition form of the plurality of separation areas adjacent to an upper edge of the respective logic cell of the plurality of logic cells and a disposition form of the plurality of separation areas adjacent to a lower edge of the respective logic cell are substantially the same or symmetrical (Figs. 5A-6B and [0042] point to various layouts of cells 301 and/or 302 comprising laterally offset (zigzag) tracks 170. It is considered obvious that the separation areas adjacent to the upper edge would be disposed in the same form as the areas adjacent to the lower edge in order to better complement the layouts of adjacent cells and allow for any combination of said cells.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Zhu and Morrow, such that the plurality of separation areas is disposed substantially the same or symmetrical along the upper and lower edges of the logic cell in order to employ complementary standard cell layouts which can replicate a netlist with different block-level layouts, assuming the cells are netlist equivalents.
Regarding claim 18, Zhu teaches A semiconductor device, comprising a plurality of logic cells, wherein each logic cell of the plurality of logic cells includes: a primary first power line and a secondary first power line respectively positioned at two opposing edges of the logic cell (Fig. 2A points to the first voltage rail 204 (primary first power line) and the second voltage rail 206 (secondary first power line).), a first conductive line positioned between the primary and secondary first power lines (Id. points to routing lines/tracks 224/226 (first conductive line(s)). In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).), a plurality of second conductive lines crossing the primary and secondary first power lines and the first conductive line (Id. points to metal lines 212 (second conductive lines).), a plurality of second power lines crossing the plurality of second conductive lines, the plurality of second power lines comprising a primary second power line and a secondary second power line respectively and is positioned at the two opposing edges of the logic cell, a third conductive line positioned between the primary and secondary second power lines (Figs. 2B-2C and [0005] point to a third metal layer M2 comprising metal shunt 208 (primary second power line), metal shunt 210 (secondary second power line) and additional metal lines (third conductive lines) which can be dedicated to interconnecting the gates of the active devices.), locations at which the first conductive line and the plurality of second conductive lines overlap are first hit points, each first hit point being a location at which the first conductive line and one of the plurality of second conductive lines are connected, except for a location adjacent to the separation areas of the plurality of second conductive lines (Figs. 2B-2C point to vias 232 and 240 (first hit points) which only connect specific metal lines (second conductive lines) 212(3) and 212(7). It is considered obvious that the vias/hit points would not be adjacent to any separation area in order to avoid damaging the component.), and locations at which the plurality of second conductive lines and the third conductive line overlap are second hit points, each second hit point being a location at which one of the plurality of second conductive lines and the third conductive line are connected, except for locations adjacent to the separation areas of the plurality of second conductive lines (Figs. 2B-2C point to vias 234 and 242 (second hit points) which only connect specific metal lines (second conductive lines) 212(3) and 212(7). It is considered obvious that the vias/hit points would not be adjacent to any separation area in order to avoid damaging the component.).
Zhu fails to teach a plurality of separation areas separating adjacent second conductive lines of the plurality of second conductive lines, each of the plurality of separation areas disposed adjacent to a boundary of the logic cell, wherein: separation areas of the plurality of separation areas are alternately positioned at a lower side and an upper side of the boundary of the logic cell so as to be disposed in a zigzag form.
Morrow teaches a plurality of separation areas separating adjacent second conductive lines of the plurality of second conductive lines, each of the plurality of separation areas disposed adjacent to a boundary of the logic cell, wherein: separation areas of the plurality of separation areas are alternately positioned at a lower side and an upper side of the boundary of the logic cell so as to be disposed in a zigzag form (Figs. 5A-6B and [0042] point to various layouts of cells 301 and/or 302 comprising laterally offset (zigzag) tracks 170.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Zhu and Morrow, such that a plurality of separation areas is disposed in a zigzag form in order to employ complementary standard cell layouts which can replicate a netlist with different block-level layouts, assuming the cells are netlist equivalents.
Regarding claim 19, Morrow teaches wherein: a first set of the plurality of separation areas alternately overlaps a lower edge and an upper edge of the primary or secondary first power line so as to be disposed in a zigzag form, and a second set of the plurality of separation areas is alternately positioned at a lower side and an upper side of the primary or secondary second power line so as to be disposed in a zigzag form (Figs. 5A-6B and [0042] point to various layouts of cells 301 and/or 302 comprising laterally offset (zigzag) tracks 170. It is considered obvious that this offset is also created in any underlying layer(s) (first set) and overlying layer(s) (second set) so as to create a full disconnect that clearly separates adjacent cells.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Zhu and Morrow, such that a plurality of separation areas is disposed in a zigzag form in order to employ complementary standard cell layouts which can replicate a netlist with different block-level layouts, assuming the cells are netlist equivalents.
Regarding claim 20, Zhu teaches wherein for each logic cell: a disposition form of the separation areas of the plurality of separation areas adjacent to an upper edge of the logic cell and a disposition form of the separation areas of the plurality of separation areas adjacent to a lower edge of the logic cell are substantially the same or symmetrical (Figs. 5A-6B and [0042] point to various layouts of cells 301 and/or 302 comprising laterally offset (zigzag) tracks 170. It is considered obvious that the separation areas adjacent to the upper edge would be disposed in the same form as the areas adjacent to the lower edge in order to better complement the layouts of adjacent cells and allow for any combination of said cells.). Thus, it would have been obvious to a POSITA prior to the filing date of the claimed invention to combine the teachings of Zhu and Morrow, such that the plurality of separation areas is disposed substantially the same or symmetrical along the upper and lower edges of the logic cell in order to employ complementary standard cell layouts which can replicate a netlist with different block-level layouts, assuming the cells are netlist equivalents.
Response to Arguments
Applicant’s arguments, see Remarks, filed 01/30/2026, with respect to the previous election requirement have been fully considered and are persuasive. The election of said claims has been withdrawn, and the now remaining claims 1-14 and 16-20 will be analyzed.
Conclusion
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/PATRICK CULLEN/ Assistant Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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