DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 1, 2, 4 through 9, 18 through 28 rejected
Present action: claims 1, 2, 4 through 9, 18, 19, 20 and 22 through 28 rejected
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 1, 2, 4, 5, 6, 7, 8, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2009/0218669) in view of Ekkels (US 2018/0158712) in view of Yu (US 2018/0158749)
Regarding claim 1
A method, comprising: providing a structure (fig 2b:200-220; [para 0029])comprising a carrier wafer (fig 2b:220,222,210; [para 0030]), and a first device wafer (fig 2b:200; [para 0029]) on the carrier wafer, wherein the carrier wafer (fig 2b:220,222,210; [para 0030]) comprises material, wherein the first device wafer (fig 2b:200; [para 0029]) comprises a first side (fig 2b:204; [para 0029]) and a second side (fig 2b:202; [para 0029]) opposite to the first side (fig 2b:204; [para 0029]), the first side (fig 2b:204; [para 0029]) of the first device wafer (fig 2b:200; [para 0029]) being in contact with the carrier wafer (fig 2b:220,222,210; [para 0030]);
forming first bonding contacts (fig 2f:240; [para 0029]) on the second side (fig 2b:202; [para 0029]) of the first device wafer (fig 2b:200; [para 0029]); forming the first bonding contacts (fig 2f:240; [para 0032]), forming first ablation structures (fig 2d,3a:C; [para 0031,0033]) in the structure (fig 2b:200-220; [para 0029]), the first ablation structures (fig 2d,3a:C; [para 0031,0033])extending through the first device wafer (fig 2b,d:200; [para 0029]) and a portion (fig 2b:222,210; [para 0030]) of the carrier wafer (fig 2b:220,222,210; [para 0030]);
and after forming the first ablation structures (fig 2d,3a:C; [para 0031,0033]), bonding a second device wafer (fig 3a:300; [para 0038,0039])on the first device wafer (fig 2b:200; [para 0029]) having the first ablation structures (fig 2d,3a:C; [para 0031,0033]).
Wang does not teach forming ablation structures after forming bonding contacts.
Ekkels teaches:
After forming first bonding contacts (fig 1a:3[0026])forming first ablation structures (fig 1b:4[0027])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the ablation structures after forming the bonding contacts in order to improve alignment of the processing by providing additional alignment identifies on the surface and to prevent potential contamination of the substrate surface under the contact material.
Wang does not teach the carrier wafer comprises semiconductor material.
Yu teaches:
the carrier wafer (fig 2:205; [para 0033]) comprises semiconductor material (silicon; [para 0033])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the carrier to comprise semiconductor material, silicon, because silicon is thermally compatible with devices and minimizes the risk of contamination.
Regarding claim 2
Wang in view of Ekkels in view of Yu teaches the method of claim 1,
Wang teaches:
forming an adhesion layer (fig 2b:212; [para 0030]);
between the carrier wafer (fig 2b:220,222,210; [para 0030]);
and the first device wafer (fig 2b:200; [para 0030]).
Regarding claim 4
Wang in view of Ekkels in view of Yu teaches the method of claim 1,
Wang teaches:
the first device wafer (fig 2b:200; [para 0029]) comprises first dies (fig 2b:202; [para 0029]), each pair of adjacent first dies (fig 2b:202; [para 0029]) being separated by one of the first ablation structures (fig 2d,3a:C; [para 0031,0033]).
Regarding claim 5.
Wang in view of Ekkels in view of Yu the method of claim 2,
Wang teaches:
the first bonding contacts (fig 2f:240; [para 0032]) are configured to be bonded to the second device wafer (fig 3a:300; [para 0038,0039]).
Regarding claim 6.
Wang in view of Ekkels in view of Yu the method of claim 5,
Yu teaches:
thinning the first device wafer (fig 2,3:110; [para 0037]);
and forming the first bonding contacts (fig 4:125; [para 0040]) on the second side of the first device wafer (fig 3:111; [para 0040]) after the first device wafer (fig 3:111; [para 0040]) is thinned.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to thin the device wafer before forming device contacts in order to enable through silicon vias and hybrid bonding thereby permitting denser interconnection of die.
Regarding claim 7.
Wang in view of Ekkels in view of Yu the method of claim 6, further
Wang teaches:
bonding the second device wafer (fig 3a:300; [para 0038,0039]) to the first device wafer (fig 2b:200; [para 0029]) in a face-to-face manner through (fig 3a,3b; [para 0035]) the first bonding contacts (fig 2f:240; [para 0032]).
Regarding claim 8.
Wang in view of Ekkels in view of Yu teaches the method of claim 5, further
Yu teaches:
forming second ablation structures (fig 9:227; [para 0048,0049]) in the second device wafer (fig 9:231; [para 0048,0049]) according to the first ablation structures (fig 9:217; [para 0048,0049]), the second ablation structures (fig 9:227; [para 0048,0049])extending through a portion of the second device wafer (fig 9:231; [para 0048,0049]), wherein at least a majority of a cross-section of the second ablation structures (fig 9:227; [para 0048,0049])overlaps with a cross-section of the first ablation structures (fig 9:217; [para 0048,0049]), when overlaying a cross-section of the carrier wafer (fig 2,9:205; [para 0033]) having the cross-section of the first ablation structures (fig 9:217; [para 0048,0049]), and a cross-section of the second device wafer (fig 9:231; [para 0048,0049])having the cross-section of the second ablation structures (fig 9:227; [para 0048,0049])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form second ablation structures in the second device wafer in order provide an additional layer for subsequent division and packaging.
Regarding claim 9.
Wang in view of Ekkels in view of Yu teaches the method of claim 8, further
Wang teaches
providing separated bonded semiconductor devices (fig 3g:400; [para 0037]) by dicing (fig 3G; [para 0040]) , the first device wafer (fig 2b,3g:200; [para 0029]) and the second device wafer (fig 2b,3g:300; [para 0035]) along at least the first ablation structures (fig 2d,3a:C; [para 0031,0033]) , wherein each of the separated bonded semiconductor devices (fig 3g:400; [para 0037]) comprises a die (fig 3g:200’,300’; [para 0040]) from each of the first device wafer (fig 2b,3g:200; [para 0029]) and the second device wafer (fig 2b,3g:300; [para 0035]).
Yu teaches:
dicing (fig 10,160; [para 0050]) through at least the carrier wafer (fig 10:205; [para 0050]),
the first device wafer (fig 9:221; [para 0048,0049]) and the second device wafer (fig 9:231; [para 0048,0049]) along at least the first ablation structures (fig 9:217; [para 0048,0049]),and the second ablation structures (fig 9:227; [para 0048,0049])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to dice through the wafer and ablation regions in order that the wafer can continue to provide support during the dicing process.
Claim(s) 22 and 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2009/0218669) in view of Ekkels (US 2018/0158712) in view of Yu (US 2018/0158749) as applied to claim 6 and further in view of Said (US 2021/0028136)
Regarding claim 22.
Wang in view of Ekkels in view of Yu teaches the method of claim 6, above.
Wang in view of Ekkels in view of Yu does not teach how the bond contacts are formed.
Said teaches:
forming the first bonding contacts (fig 4:788; [para 0098]) on the second side of the first device wafer (fig 4:708; [para 0096]), comprises: forming a dielectric layer (fig 4:760; [para 0096]) on the second side of the first device wafer (fig 4:708; [para 0096]);
forming the first bonding contacts (fig 4:788; [para 0098]) on the dielectric layer (fig 4:760; [para 0096]);
and forming a protective layer (fig 4:792; [para 0101]) on the first bonding contacts (fig 4:788; [para 0098]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide bonding contacts having a protective layer in order to prevent oxidation of the contact (paragraph 101)
Regarding claim 23.
Wang in view of Ekkels in view of Yu in view of Said teaches the method of claim 22, above.
Wang teaches:
forming the first ablation structures (fig 2d,3a:C; [para 0031,0033]) in the structure, comprises: forming the first ablation structures (fig 2d,3a:C; [para 0031,0033]) extending through the protective layer (fig 2d:230; [para 0031]), the dielectric layer (fig 2d:208; [para 0029]), the adhesion layer (fig 2d:212; [para 0029]), and the portion (fig 2d:222,210; [para 0030]) of the carrier wafer (fig 2b:220,222,210; [para 0030]).
Claim(s) 18, 19, 20, 24, 25, 26, 27, and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 2009/0218669) in view of Ekkels (US 2018/0158712) in view of Nakamura (US 2010/0099221)
Regarding claim 18.
Wang teaches:
A method, comprising: providing a carrier wafer (fig 2b:220,222,210,212; [para 0030]) , wherein the carrier wafer (fig 2b:222,210,220,212; [para 0030]) comprises material;
providing a first device wafer (fig 2b:200; [para 0029]) on the carrier wafer (fig 2b:222,210,220,212; [para 0030]), wherein the first device wafer (fig 2b:200; [para 0029]) comprises a first side (fig 2b:204; [para 0029]) and a second side (fig 2b:206; [para 0029]) opposite to the first side (fig 2b:204; [para 0029]), the first side (fig 2b:204; [para 0029]) of the first device wafer (fig 2b:200; [para 0029]) being in contact with the carrier wafer (fig 2b:220,222,210,212; [para 0030]);
forming first bonding contacts (fig 2f:240; [para 0032]) on the second side (fig 2b:206; [para 0029]) of the first device wafer (fig 2b:200; [para 0029]);
forming the first bonding contacts (fig 2f:240; [para 0032]), forming first ablation structures (fig 2e,2g:c; [para 0033]) extending in the first device wafer (fig 2b:200; [para 0029]);
and bonding a second device wafer (fig 3a,3b:300; [para 0035]) to the first device wafer (fig 2b:200; [para 0029]) in face-to-face manner.
Wang does not teach forming ablation structures after forming bonding contacts.
Ekkels teaches:
After forming first bonding contacts (fig 1a:3[0026])forming first ablation structures (fig 1b:4[0027])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the ablation structures after forming the bonding contacts in order to improve alignment of the processing by providing additional alignment identifies on the surface and to prevent potential contamination of the substrate surface under the contact material.
Wang does not teach the carrier wafer comprises semiconductor material.
Nakamura teaches
the carrier wafer (fig 1b:2; [para 0069])
having innate ablation structures (fig 1b:210; [para 0069]) extending in a portion of the carrier wafer (fig 1b:2; [para 0069])comprises semiconductor material ([para 0069])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the carrier to comprise semiconductor material, silicon, because silicon is thermally compatible with devices and minimizes the risk of contamination.
Regarding claim 19.
Wang in view of Ekkels in view of Nakumura teaches the method of claim 18, further
Wang teaches:
forming an adhesion layer (fig 2b:212; [para 0029]) between the carrier wafer (fig 2b:220,222,210,212; [para 0030]) and the first device wafer (fig 2b:200; [para 0029]), .
Nakumura teaches:
the first ablation structures (fig 3c:210; [para 0069])overlap the innate ablation structures (fig 1b:210; [para 0076])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the ablation structures to overlap in order to facilitate singulation of the chips (paragraph 99)
Regarding claim 20.
Wang in view of Ekkels in view of Nakumura teaches the method of claim 18,
Wang teaches
The first device wafer (fig 2a:200[0029])comprises first dies (fig 2a:202[0029])each pair of adjacent first dies (fig 2a:202[0029])being separated by one of the first ablation structures (fig 2d:c[0031])
Regarding claim 24.
Wang in view of Ekkels in view of Nakumura teaches the method of claim 18,
Wang teaches:
forming the first ablation structures (fig 2e,2g:c; [para 0033]) extending in the first device wafer (fig 2b:200; [para 0029]), comprises: forming the first ablation structures (fig 2e,2g:c; [para 0033]) extending through the first device wafer (fig 2b:200; [para 0029]).
Regarding claim 25.
Wang in view of Ekkels in view of Nakumura teaches the method of claim 18,
Wang teaches:
forming the first ablation structures (fig 2e,2g:c; [para 0033]) extending in the first device wafer (fig 2b:200; [para 0029]), comprises: forming the first ablation structures (fig 2e,2g:c; [para 0033]) extending in a portion of the first device wafer (fig 2b:200; [para 0029]).
Regarding claim 26.
Wang in view of Ekkels in view of Nakumura teaches the method of claim 18,
Wang teaches:
forming second ablation structures (fig 3g; [para 0040]) in the second device wafer (fig 3g:300; [para 0038]).
Regarding claim 27.
Wang in view of Ekkels in view of Nakumura teaches the method of claim 26
Wang teaches:
the second ablation structures (fig 3g; [para 0040])overlap the first ablation structures (fig 2e,2g:c; [para 0033]) .
Nakumura teaches:
the first ablation structures (fig 3c:210; [para 0069])overlap the innate ablation structures (fig 1b:210; [para 0076])
Regarding claim 28.
Wang in view of Ekkels in view of Nakumura teaches the method of claim 26
Wang teaches:
forming the second ablation structures (fig 3g; [para 0040])in the second device wafer (fig 3g:300; [para 0038]), comprises: forming the second ablation structures (fig 3g; [para 0040])extending in a portion of the second device wafer (fig 3g:300; [para 0038]).
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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