DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in this office action and presented for examination. Claims 1-2, 4-6, 9, 11-12, 14-16, and 18-20 are newly amended by the response received August 6, 2025.
Claim Objections
Claims 11-17 are objected to because of the following informalities. Appropriate correction is required.
In claim 11, lines 6-7, “to latency threshold” should be “to a latency threshold” for grammatical clarity.
Claims 12-17 are objected to for failing to alleviate the objection of claim 11 above.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 6 and 15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 6 recites the limitation “responsive to the second branch instruction issuing a long latency request exceeding a threshold, pausing the execution of the operations associated with the second branch instruction and initiating execution of the operations associated with the first branch instruction” in lines 3-6. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0010]) does not appear to provide support for the aforementioned pausing being responsive to the second branch instruction issuing a long latency request “exceeding a threshold”, in the context of the remaining limitations of claim 6 (and claim 1, upon which claim 6 is dependent). For example, while paragraph [0010] discloses “For example, in some embodiments, after executing operations of the second branch instruction for a first period of time, the second branch instruction issues a similar memory request as issued in the first branch instruction. And similar to the case described with respect to the first branch instruction, the compiler will also have inserted an indication in the second branch instruction to indicate the longer latency request in the second branch instruction”, the disclosure of the aforementioned “similar[ities]” does not necessarily provide support for the second branch instruction issuing a long latency request “exceeding a threshold”. For example, the case described with respect to the first branch instruction does not appear to be directly analogous to the case of the subject matter of claim 6, since in the case described with respect to the first branch instruction, the claims do not implicitly recite that progress (e.g., progress of a memory request) has already been made with respect to the second latency value, but in the case of the subject matter of claim 6, progress (e.g., progress of a memory request) appears to have already been made with respect to the first latency value. For example, the original disclosure does not disclose, if a comparison of a first latency value of the first branch instruction to a latency threshold that is based on a second latency value of the second branch instruction (as recited in claim 1) resulted in execution of operations associated with a second branch instruction, how it would be the case that a comparison of the second latency value of the second branch instruction to a latency threshold that is based on a first latency value of the first branch instruction – which presumably would result in an opposite comparison result — would instead still result in execution of operations associated with a first branch instruction.
Claim 15 recites the limitation “responsive to the second branch instruction issuing a long latency request exceeding a threshold, pause the execution of the operations associated with the second branch instruction at the plurality of compute units and initiate execution of the operations associated with the first branch instruction at the plurality of compute units” in lines 4-7. However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0010]) does not appear to provide support for the aforementioned pausing being responsive to the second branch instruction issuing a long latency request “exceeding a threshold”, in the context of the remaining limitations of claim 15 (and claim 11, upon which claim 15 is dependent). For example, while paragraph [0010] discloses “For example, in some embodiments, after executing operations of the second branch instruction for a first period of time, the second branch instruction issues a similar memory request as issued in the first branch instruction. And similar to the case described with respect to the first branch instruction, the compiler will also have inserted an indication in the second branch instruction to indicate the longer latency request in the second branch instruction”, the disclosure of the aforementioned “similar[ities]” does not necessarily provide support for the second branch instruction issuing a long latency request “exceeding a threshold”. For example, the case described with respect to the first branch instruction does not appear to be directly analogous to the case of the subject matter of claim 15, since in the case described with respect to the first branch instruction, the claims do not implicitly recite that progress (e.g., progress of a memory request) has already been made with respect to the second latency value, but in the case of the subject matter of claim 15, progress (e.g., progress of a memory request) appears to have already been made with respect to the first latency value. For example, the original disclosure does not disclose, if a comparison of a first latency value of the first branch instruction to a latency threshold that is based on a second latency value of the second branch instruction (as recited in claim 1) resulted in execution of operations associated with a second branch instruction, how it would be the case that a comparison of the second latency value of the second branch instruction to a latency threshold that is based on a first latency value of the first branch instruction – which presumably would result in an opposite comparison result — would instead still result in execution of operations associated with a first branch instruction.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “a first latency value of the first branch instruction” in lines 4-5. However, the metes and bounds of this limitation are indefinite. On one hand, the language appears to convey that the first latency value is of the first branch instruction. On the other hand, various portions of the disclosure (e.g., paragraph [0034]) appear to instead convey that the first latency value is of an instruction with an operation code for a memory request that is associated with longer memory access times such as a buffer load operation (e.g., buffer load) or an image operation (e.g., image_sample). Therefore, it is unclear, for example, what exactly “a first latency value of the first branch instruction” is. Similarly, the limitation “a second latency value of the second branch instruction” in claim 1, lines 6-7, is indefinite, as it is unclear as to whether the second latency value is of the second branch instruction or of a second instruction with an operation code for a memory request that is associated with longer memory access times such as a buffer load operation (e.g., buffer load) or an image operation (e.g., image_sample).
Claims 2-10 are rejected for failing to alleviate the rejection of claim 1 above.
Claim 2 recites the limitation “the first latency value is a time to execute one or more memory requests in the first branch instruction” in lines 1-2. However, the metes and bounds of this limitation are indefinite. For example, it is unclear as to how “one or more memory requests” can be “in” “the first branch instruction”.
Claim 3 is rejected for failing to alleviate the rejection of claim 2 above.
Claim 3 recites the limitation “The method of claim 2, wherein the one or more memory requests comprise a buffer load operation or an image sample operation” in lines 1-2. Claim 2, upon which claim 3 is dependent, recites the limitation “the first latency value is a time to execute one or more memory requests in the first branch instruction” in lines 1-2. However, the metes and bounds of claim 3 in the context of claim 2 are indefinite. For example, it is indefinite as to how “a buffer load operation or an image sample operation” can be “in” “the first branch instruction”.
Claim 6 recites the limitation “a long latency request exceeding a threshold” in lines 3-4. However, the claim does not particularly point out and distinctly define the metes and bounds of the subject matter to be protected by the patent grant, because it would not be clear to a hypothetical person possessing the ordinary level of skill in the pertinent art whether a latency request would be considered to be "long". What is “long” may vary from one person to another. Examiner notes that the disclosure does not explicitly or implicitly provide definite criteria by which whether something is “long” can be determined.
Claim 11 recites the limitation “a first latency value of the first branch instruction” in lines 5-6. However, the metes and bounds of this limitation are indefinite. On one hand, the language appears to convey that the first latency value is of the first branch instruction. On the other hand, various portions of the disclosure (e.g., paragraph [0034]) appear to instead convey that the first latency value is of an instruction with an operation code for a memory request that is associated with longer memory access times such as a buffer load operation (e.g., buffer load) or an image operation (e.g., image_sample). Therefore, it is unclear, for example, what exactly “a first latency value of the first branch instruction” is. Similarly, the limitation “a second latency value of the second branch instruction” in claim 11, lines 7-8, is indefinite, as it is unclear as to whether the second latency value is of the second branch instruction or of a second instruction with an operation code for a memory request that is associated with longer memory access times such as a buffer load operation (e.g., buffer load) or an image operation (e.g., image_sample).
Claims 12-17 are rejected for failing to alleviate the rejection of claim 11 above.
Claim 12 recites the limitation “the first latency value is a time to execute one or more memory requests in the first branch instruction” in lines 1-3. However, the metes and bounds of this limitation are indefinite. For example, it is unclear as to how “one or more memory requests” can be “in” “the first branch instruction”.
Claim 13 is rejected for failing to alleviate the rejection of claim 12 above.
Claim 13 recites the limitation “The accelerated processing unit of claim 12, wherein the one or more memory requests comprise a buffer load operation or an image sample operation” in lines 1-2. Claim 12, upon which claim 13 is dependent, recites the limitation “the first latency value is a time to execute one or more memory requests in the first branch instruction” in lines 1-3. However, the metes and bounds of claim 13 in the context of claim 12 are indefinite. For example, it is indefinite as to how “a buffer load operation or an image sample operation” can be “in” “the first branch instruction”.
Claim 15 recites the limitation “a long latency request exceeding a threshold” in lines 4-5. However, the claim does not particularly point out and distinctly define the metes and bounds of the subject matter to be protected by the patent grant, because it would not be clear to a hypothetical person possessing the ordinary level of skill in the pertinent art whether a latency request would be considered to be "long". What is “long” may vary from one person to another. Examiner notes that the disclosure does not explicitly or implicitly provide definite criteria by which whether something is “long” can be determined.
Claim 18 recites the limitation “a first latency value of the first branch instruction” in lines 8-9. However, the metes and bounds of this limitation are indefinite. On one hand, the language appears to convey that the first latency value is of the first branch instruction. On the other hand, various portions of the disclosure (e.g., paragraph [0034]) appear to instead convey that the first latency value is of an instruction with an operation code for a memory request that is associated with longer memory access times such as a buffer load operation (e.g., buffer load) or an image operation (e.g., image_sample). Therefore, it is unclear, for example, what exactly “a first latency value of the first branch instruction” is. Similarly, the limitation “a second latency value of the second branch instruction” in claim 18, lines 9-10, is indefinite, as it is unclear as to whether the second latency value is of the second branch instruction or of a second instruction with an operation code for a memory request that is associated with longer memory access times such as a buffer load operation (e.g., buffer load) or an image operation (e.g., image_sample).
Claims 19-20 are rejected for failing to alleviate the rejection of claim 18 above.
Claim 19 recites the limitation “the first latency value is a time to execute one or more memory requests in the first branch instruction” in lines 1-2. However, the metes and bounds of this limitation are indefinite. For example, it is unclear as to how “one or more memory requests” can be “in” “the first branch instruction”.
Response to Arguments
Applicant on page 7 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 1 is amended to recite "...a comparison of a first latency value of the first branch instruction to a latency threshold that is based on a second latency value of the second branch instruction." Support for the amendment is found at least, for example, at paragraphs [0009] and [0041] of the specification. As agreed on during the aforementioned interview, this amendment overcomes the rejection. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 8 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 2 is amended to recite "the first latency value is a time to execute one or more memory requests in the first branch instruction." Support for the amendment is found at least, for example, at paragraph [0009] of the specification. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 8 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 4 is amended to recite "the first latency value is identified as exceeding the latency threshold based on an indication from a compiler." Support for the amendment is found at least, for example, at paragraphs [0009], [0017], and [0031] of the specification. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 8 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 5 is amended to recite "...the first latency value is a duration of a fetch operation associated with a memory request of the first branch instruction..." Support for the amendment is found at least, for example, at paragraph [0041] of the specification. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant across pages 8-9 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 5 is amended to recite "...the second latency value is a duration of a fetch operation associated with a memory request of the second branch instruction..." Support for the amendment is found at least, for example, at paragraph [0041] of the specification. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 9 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 6 is amended to recite "responsive to the second branch instruction issuing a long latency request exceeding a threshold, pausing the execution of the operations associated with the second branch instruction and initiating execution of the operations associated with the first branch instruction; and responsive to completing the execution of the operations associated with the first branch instruction, resuming the execution of the operations associated with the second branch instruction." Support for the amendment is found at least, for example, at paragraph [0010] of the specification. Accordingly, the rejection should be withdrawn.’
However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0010]) does not appear to provide support for the aforementioned pausing being responsive to the second branch instruction issuing a long latency request “exceeding a threshold”, in the context of the remaining limitations of claim 6 (and claim 1, upon which claim 6 is dependent). For example, while paragraph [0010] discloses “For example, in some embodiments, after executing operations of the second branch instruction for a first period of time, the second branch instruction issues a similar memory request as issued in the first branch instruction. And similar to the case described with respect to the first branch instruction, the compiler will also have inserted an indication in the second branch instruction to indicate the longer latency request in the second branch instruction”, the disclosure of the aforementioned “similar[ities]” does not necessarily provide support for the second branch instruction issuing a long latency request “exceeding a threshold”. For example, the case described with respect to the first branch instruction does not appear to be directly analogous to the case of the subject matter of claim 6, since in the case described with respect to the first branch instruction, the claims do not implicitly recite that progress (e.g., progress of a memory request) has already been made with respect to the second latency value, but in the case of the subject matter of claim 6, progress (e.g., progress of a memory request) appears to have already been made with respect to the first latency value. For example, the original disclosure does not disclose, if a comparison of a first latency value of the first branch instruction to a latency threshold that is based on a second latency value of the second branch instruction (as recited in claim 1) resulted in execution of operations associated with a second branch instruction, how it would be the case that a comparison of the second latency value of the second branch instruction to a latency threshold that is based on a first latency value of the first branch instruction – which presumably would result in an opposite comparison result — would instead still result in execution of operations associated with a first branch instruction.
Applicant on page 9 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 9 is amended to recite "the compiler is configured to identify whether the first latency value exceeds the latency threshold." Support for the amendment is found at least, for example, at paragraphs [0009] and [0041] of the specification. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant across pages 9-10 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 11 is amended to recite "a comparison of a first latency value of the first branch instruction to latency threshold that is based on a second latency value of the second branch instruction." Support for the amendment is found at least, for example, at paragraphs [0009] and [0041] of the specification. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 10 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 12 is amended to recite "the first latency value is a time to execute one or more memory requests in the first branch instruction." Support for the amendment is found at least, for example, at paragraph [0009] of the specification. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 10 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 14 is amended to recite "wherein the first latency value is a duration of a fetch operation associated with a memory request of the first branch instruction." Support for the amendment is found at least, for example, at paragraph [0041] of the specification. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 10 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 14 is amended to recite "...the second latency value is a duration of a fetch operation associated with a memory request of the second branch instruction..." Support for the amendment is found at least, for example, at paragraph [0041] of the specification. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 11 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 15 is amended to recite "hardware scheduler circuitry is configured to: responsive to the second branch instruction issuing a long latency request exceeding a threshold, pause the execution of the operations associated with the second branch instruction at the plurality of compute units and initiate execution of the operations associated with the first branch instruction at the plurality of compute units; and responsive to completing the execution of the operations associated with the first branch instruction, resume the execution of the operations associated with the second branch instruction at the plurality of compute units." Support for the amendment is found at least, for example, at paragraph [0010] of the specification. Accordingly, the rejection should be withdrawn.’
However, the original disclosure does not appear to provide support for this limitation. For example, the original disclosure (e.g., paragraph [0010]) does not appear to provide support for the aforementioned pausing being responsive to the second branch instruction issuing a long latency request “exceeding a threshold”, in the context of the remaining limitations of claim 6 (and claim 1, upon which claim 6 is dependent). For example, while paragraph [0010] discloses “For example, in some embodiments, after executing operations of the second branch instruction for a first period of time, the second branch instruction issues a similar memory request as issued in the first branch instruction. And similar to the case described with respect to the first branch instruction, the compiler will also have inserted an indication in the second branch instruction to indicate the longer latency request in the second branch instruction”, the disclosure of the aforementioned “similar[ities]” does not necessarily provide support for the second branch instruction issuing a long latency request “exceeding a threshold”. For example, the case described with respect to the first branch instruction does not appear to be directly analogous to the case of the subject matter of claim 6, since in the case described with respect to the first branch instruction, the claims do not implicitly recite that progress (e.g., progress of a memory request) has already been made with respect to the second latency value, but in the case of the subject matter of claim 6, progress (e.g., progress of a memory request) appears to have already been made with respect to the first latency value. For example, the original disclosure does not disclose, if a comparison of a first latency value of the first branch instruction to a latency threshold that is based on a second latency value of the second branch instruction (as recited in claim 1) resulted in execution of operations associated with a second branch instruction, how it would be the case that a comparison of the second latency value of the second branch instruction to a latency threshold that is based on a first latency value of the first branch instruction – which presumably would result in an opposite comparison result — would instead still result in execution of operations associated with a first branch instruction.
Applicant on page 11 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 9 is amended to recite "the compiler is configured to identify whether the first latency value exceeds the latency threshold." Support for the amendment is found at least, for example, at paragraphs [0009] and [0041] of the specification. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on pages 11-12 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 18 is amended to recite "a comparison of a first latency value of the first branch instruction to latency threshold that is based on a second latency value of the second branch instruction." Support for the amendment is found at least, for example, at paragraphs [0009] and [0041] of the specification. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 12 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 19 is amended to recite "first latency value is a time to execute one or more memory requests in the first branch instruction." Support for the amendment is found at least, for example, at paragraph [0009] of the specification. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 12 argues: ‘Without acquiescing to the propriety of the rejection and in the interest of advancing prosecution, claim 20 is amended to recite "...the second latency value is a duration of a fetch operation associated with a memory request of the second branch instruction..." Support for the amendment is found at least, for example, at paragraph [0041] of the specification. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 12 argues: “Claim 6 is amended to remove this limitation. Accordingly, the rejection should be withdrawn.”
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 13 argues: ‘the Office rejects claim 11 for reciting the limitation "operations associated with the second branch instruction" at lines 10-11 since it is indefinite as to whether this limitation is the same as, or different from, "operations associated with the second branch instruction" recited at claim 11, lines 3-4. Claim 11 is amended to correct this discrepancy.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 13 argues: ‘the Office rejects claim 11 for reciting the limitation "operations associated with the first branch instruction" at lines 11-12 since it is indefinite as to whether this limitation is the same as, or different from, "operations associated with the first branch instruction" recited at claim 11, lines 4-5. Claim 11 is amended to correct this discrepancy.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 13 argues: ‘Claim 11 is amended to clarify that the limitation is "schedule operations associated with the second branch instruction for execution prior to execution of operations associated with the first branch instruction." Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 13 argues: ‘At page 10 of the Office Action, the Office rejects claim 15 since the limitation "the one or more memory requests of the first branch instruction" lacks antecedent basis. Claim 15 is amended to remove this limitation. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant on page 13 argues: ‘Claim 15 is amended to recite "the execution of the operations associated with the second branch instruction associated with the second branch instruction at the plurality of compute units" As such, this limitation clearly refers back to the limitation "a plurality of compute units to execute the operations associated with the second branch instruction" in claim 11. Accordingly, the rejection should be withdrawn.’
In view of the aforementioned amendment, the associated previously presented rejection is withdrawn.
Applicant across pages 13-14 argues: ‘At page 11 of the Office Action, the Office rejects claim 15 for reciting "the operations associated with the first branch instruction" at lines 5-6 since this limitation is allegedly indefinite. The Applicant respectfully disagrees. First, the Applicant notes that the limitation recites, in relevant part, "responsive to the second branch instruction issuing a long latency request exceeding a threshold, pause the execution of the operations associated with the second branch instruction at the plurality of compute units and initiate execution of the operations associated with the first branch instruction at the plurality of compute units." In addition, claim 11 (which claim 15 depends from) recites "a plurality of compute unites to execute the operations associated with the second branch instruction prior to the operations associated with the first branch instruction." As such, one of ordinary skill in the art understands that the initiating of the execution of the operations associated with the first branch instruction is clear and definite within the context of claim 15 in combination with claim 11 since "initiate execution of the operations associated with the first branch instruction" is performed after the execution of the operations associated with the second branch instruction is paused. Accordingly, the rejection should be withdrawn.’
In view of an amendment made to claim 11, the associated previously presented rejection is withdrawn.
Applicant on page 14 argues: ‘At page 11 of the Office Action, the Office rejects claim 16 for reciting "the operations associated with the second branch instruction" in line 8 and for reciting "the operations associated with the first branch instruction" in lines 8-9 since these limitations are allegedly unclear. The Applicant respectfully disagrees. The Applicant notes that the limitation recites, in relevant part, "wherein the hardware scheduler circuitry is configured to instruct the plurality of compute units to execute the operations associated with the second branch instruction prior to the operations associated with the first branch instruction." Claim 11 (which claim 16 depends from) recites "a plurality of compute unites to execute the operations associated with the second branch instruction prior to the operations associated with the first branch instruction." As such, the Applicant submits that claim 16 is clear and definite. Accordingly, the rejection should be withdrawn.’
In view of an amendment made to claim 11, the associated previously presented rejection is withdrawn.
Applicant on page 14 argues: ‘At page 11 of the Office Action, the Office rejects claim 17 for reciting "the operations associated with the first branch instruction" and "the operations associated with the second branch instruction" since these limitations are allegedly unclear. The Applicant respectfully disagrees. The Applicant notes that the limitation recites, in relevant part, "an interface to a memory that stores data for executing the operations associated with the first branch instruction and data for executing the operations associated with the second branch instruction." Claim 11 (which claim 17 depends from) recites "a plurality of compute unites to execute the operations associated with the second branch instruction prior to the operations associated with the first branch instruction." As such, the Applicant submits that claim 17 is clear and definite since claim 17 is defining where the data for executing the operations associated with both the first instruction and the second instruction is stored. Accordingly, the rejection should be withdrawn.’
In view of an amendment made to claim 11, the associated previously presented rejection is withdrawn.
Applicant across pages 15-16 argues: “As such, Damani fails to disclose "based on a comparison of a first latency value of the first branch instruction to a latency threshold that is based on a second latency value of the second branch instruction" as recited in claim 1. Accordingly, the rejection to claim 1 should be withdrawn. Claims 11 and 18 are amended to include similar features as claim 1, mutatis mutandis. Accordingly, the rejections to claims 11 and 18 should be withdrawn for similar reasons. Claims 2-10, 12-17, 19, and 20 depend from claims 1, 11, and 18, respectively. Accordingly, Damani fails to disclose the features of these dependent claims, at least by virtue of their respective dependence from claims 1, 11, and 18.”
However, the metes and bounds of the aforementioned amended limitation appear to be indefinite. For example, on one hand, the language appears to convey that the first latency value is of the first branch instruction. On the other hand, various portions of the disclosure (e.g., paragraph [0034]) appear to instead convey that the first latency value is of an instruction with an operation code for a memory request that is associated with longer memory access times such as a buffer load operation (e.g., buffer load) or an image operation (e.g., image_sample). Therefore, it is unclear, for example, what exactly “a first latency value of the first branch instruction” is. Similarly, the limitation “a second latency value of the second branch instruction” in claim 1, lines 6-7, is indefinite, as it is unclear as to whether the second latency value is of the second branch instruction or of a second instruction with an operation code for a memory request that is associated with longer memory access times such as a buffer load operation (e.g., buffer load) or an image operation (e.g., image_sample).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KEITH E VICARY/ Primary Examiner, Art Unit 2182
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