DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement filed on 06/05/2023 has been considered.
Drawings
The drawings filed on 06/05/2023 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 06/05/2023 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5, 8, 9, 11, 13, 16 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Choi (US 2013/0000978).
PNG
media_image1.png
410
368
media_image1.png
Greyscale
Regarding claim 1, Choi discloses:
A semiconductor package comprising:
a lower structure (120, ¶0058, figure 1a is being considered while inverted for the current interpretation) including a first lower conductive pad (140, ¶0058) disposed on an upper surface thereof;
a first semiconductor chip (110, ¶0059) disposed on the lower structure (110), the first semiconductor chip (110) including a first chip conductive pad (130, ¶058) disposed on a lower surface thereof;
a solder ball (150, ¶0058) connecting the first lower conductive pad (140) and the first chip conductive pad (130);
a photosensitive insulating layer filling a space between the lower structure and the first semiconductor chip (epoxy resin is disclosed as bonding the chip to the substrate ¶0119); and
a first organic insulating layer 160 (¶0058, ¶0045, covering a side surface of the first chip conductive pad (130).
Regarding claim 3, Choi further discloses:
wherein the first organic insulating layer (160) extends to cover a side surface of the solder ball (150, figure 1b).
Regarding claim 5, Choi further discloses:
wherein the photosensitive insulating layer includes an epoxy resin (¶0119)
Regarding claim 8, Choi further discloses:
wherein the first organic insulating layer (160) surrounds the first chip conductive pad (130).
Regarding claim 9, Choi discloses:
A semiconductor package comprising:
a first semiconductor chip (120) including a first chip conductive pad (140) disposed on an upper surface thereof (fig. 1a is being considered while inverted for the current interpretation);
at least one second semiconductor chip (110) disposed on the first semiconductor chip, the at least one second semiconductor chip including a second chip conductive pad (130) disposed on a lower surface thereof;
a solder ball (150) connecting the first chip conductive pad to the second chip conductive pad;
a photosensitive insulating layer filling a space between the first semiconductor chip and the at least one second semiconductor chip (¶0119); and
a first organic insulating layer (160) covering a side surface of the second chip conductive pad (130).
Regarding claim 11, Choi further discloses:
wherein the first organic insulating layer (160) extends to cover a side surface of the solder ball (150, figure 1b).
Regarding claim 13, Choi further discloses:
wherein the photosensitive insulating layer includes an epoxy resin (¶0119)
Regarding claim 16, Choi further discloses:
wherein the first organic insulating layer (160) surrounds the first chip conductive pad (130).
Allowable Subject Matter
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 17, the prior art does not disclose “a second photosensitive insulating layer filling a space between the second semiconductor chips; a first organic insulating layer covering a side surface of the first chip upper conductive pad; a second organic insulating layer covering a side surface of the second chip lower conductive pad; and a third organic insulating layer covering a side surface of the second chip upper conductive pad” in combination with the remaining claimed features.
Regarding claims 2 and 10, the prior art does not disclose “ “further including a second organic insulating layer covering a side surface of the first lower conductive pad” in combination with the remaining claimed features.
Regarding claim 4 and 12, the prior art does not disclose “a second organic insulating layer covering a side surface of the first lower conductive pad and in contact with the first organic insulating layer” in combination with the remaining claimed features.
Regarding claims 6 and 14, the prior art does not disclose “wherein: the epoxy resin is a novolac resin, the dissolution inhibitor is diazonaphthoquinone, the curing agent is an imidazole derivative, and the filler is silica” in combination with the remaining claimed features.
Regarding claims 7 and 15, the prior at does not disclose “wherein the first organic insulating layer includes an imidazole derivative” in combination with the remaining claimed features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/WILLIAM A HARRISTON/Primary Examiner, Art Unit 2899