DETAILED ACTION
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Election/Restrictions
Applicant’s election without traverse of claims 1-10 and 20 in the reply filed on 10/07/2025 is acknowledged.
Specification
The following title is suggested: --MEMORY DEVICE AND DATA PAGE PROGRAMMING OPERATIONS THEREFOR--
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 6-8 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim(s) 6 recite(s) the language (emphasis added) “in response to a trigger event not occurring: skip reading”, where “a trigger event” has already been recited in claim 2 and it is unclear if the limitations are different.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 9, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nguyen, US 20220246214 A1.
As to claim 1, Nguyen discloses a memory device (see Nguyen Fig 1), comprising:
an array of memory cells (see Nguyen Para [0060]) in columns and rows (see Nguyen Para [0060]), each memory cell being set to one of 2N final levels (see Nguyen Fig 5 Ref 241 and 243) corresponding to a piece of N-bits data (see Nguyen Para [0081]), where N is an integer greater than 2 (see Nguyen Para [0081]);
word lines (see Nguyen Para [0060]) respectively coupled to rows of the memory cells; and
a peripheral circuit (see Nguyen Fig 3 Ref 143) coupled to the array of memory cells (see Nguyen Fig 3 Ref 131) through the word lines and
configured to: program, in a first pass (see Nguyen Fig 5 Ref Coarse QLC), a select row of the rows of the memory cells (see Nguyen Para [0052]) based on N data pages (see Nguyen Fig 5 Refs Group 0-3), such that each memory cell of the selected row is set to one of k intermediate levels (see Nguyen Fig 5 Refs Group 0-3 and V0-V3, and Para [0101]), where k is an integer not greater than 2N (see Nguyen Fig 5 Refs V0-V3); and read M data pages of the N data pages (see Nguyen Fig 6 Ref Group ID Bit 1, and Para [0109]) from the select row after (see Nguyen Para [0109]) the first pass, where M is an integer smaller than N (see Nguyen Para [0109]).
As to claim 2, Nguyen discloses the memory device of claim 1, wherein
the peripheral circuit is configured to read the M data pages of the N data pages from the select row in response to a trigger event occurring (see Nguyen Para [0189]).
As to claim 3, Nguyen discloses the memory device of claim 2, wherein
the k intermediate levels correspond to k threshold voltage ranges (see Nguyen Fig 11 Refs VR00-VR23), respectively, of the memory cells of the select row; and
at least two threshold voltage ranges (see Nguyen Fig 11 Refs VR00-VR03 and Refs VR10-VR13) corresponding to two adjacent intermediate levels of the k intermediate levels are non-overlapping (see Nguyen Fig 11 Refs Group 0 and Group 1).
As to claim 4, Nguyen discloses the memory device of claim 3, wherein
to read the M data pages, the peripheral circuit comprises a word line driver (see Nguyen Fig 3 Ref 143, and Para [0061]) coupled to the select row through a select word line of the word lines (see Nguyen Para [0060]), and configured to apply an adjusted read voltage between the two threshold voltage ranges to the select word line (see Nguyen Para [0124]).
As to claim 9, Nguyen discloses the memory device of claim 1, wherein
the peripheral circuit is further configured to copy remaining (N−M) data pages to a designated block of the array of memory cells after the first pass (see Nguyen Para [0119]).
As to claim 20, Nguyen discloses a system (see Nguyen Fig 1), comprising:
a memory device (see Nguyen Fig 1 Ref 110) configured to store data, the memory device comprising:
an array of memory cells (see Nguyen Para [0060]) in columns and rows (see Nguyen Para [0060]), each memory cell being set to one of 2N final levels (see Nguyen Fig 5 Ref 241 and 243) corresponding to a piece of N-bits data (see Nguyen Para [0081]), where N is an integer greater than 2 (see Nguyen Para [0081]); word lines respectively coupled to rows of the memory cells (see Nguyen Para [0060]); and a peripheral circuit (see Nguyen Fig 3 Ref 143) coupled to the array of memory cells (see Nguyen Fig 3 Ref 131) through the word lines and
configured to: program, in a first pass (see Nguyen Fig 5 Ref Coarse QLC), a select row of the rows of the memory cells (see Nguyen Para [0052]) based on N data pages (see Nguyen Fig 5 Refs Group 0-3), such that each memory cell of the selected row is set to one of k intermediate levels (see Nguyen Fig 5 Refs Group 0-3 and V0-V3, and Para [0101]), where k is an integer not greater than 2N (see Nguyen Fig 5 Refs V0-V3); and read M data pages of the N data pages (see Nguyen Fig 6 Ref Group ID Bit 1, and Para [0109]) from the select row after (see Nguyen Para [0109]) the first pass, where M is an integer smaller than N; and a memory controller coupled to the memory device and configured to control the memory device (see Nguyen Para [0109]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen, US 20220246214 A1, in view of Park, US 20220415401 A1.
As to claim 5, Nguyen discloses the memory device of claim 4, wherein
to program the select row, the word line driver is further configured to apply a voltage.
Nguyen does not appear to explicitly disclose configured to apply an adjusted verify voltage to the select word line for verifying a lower level of the two adjacent intermediate levels, the adjusted verify voltage being smaller than a default verify voltage for verifying the lower level of the two adjacent intermediate levels.
Park disclose an adjusted verify voltage (see Park Fig 6 Ref Vvfyp) to the select word line for verifying a lower level of the two adjacent intermediate levels (see Park Fig 6 Ref E and P), the adjusted verify voltage being smaller than a default verify voltage for verifying the lower level (see Park Fig 6 Ref VvfyM and Para [0152]) of the two adjacent intermediate levels.
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that memory device, as disclosed by Nguyen, may implement a particular verification schema, as disclosed by Park. The inventions are well known variants of memory device that perform stepwise programming, and the combination of known inventions which produces predictable results is obvious and not patentable. Further evidence to the obviousness of their combination is Park’s attempt to measure change in thresholds voltages (see Park Para [0141]).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nguyen, US 20220246214 A1, in view of Jang, US 20210158874 A1.
As to claim 10, Nguyen discloses the memory device of claim 2, wherein
the trigger event comprises a command.
Nguyen does not appear to explicitly disclose power loss of the memory device.
Jang discloses power loss of the memory device (see Jang Fig 18 Ref S560).
It would have been obvious to one skilled in the art at the time of the effective filing of the invention that a memory device, as disclosed by Nguyen, may implement a particular programming schema after a sudden power off, as disclosed Jang. The inventions are well known variants of memory devices employing disjointed coarse and fine programming, and the combination of known inventions which produces predictable results is obvious, and not patentable. Further evidence to the obviousness of their combination is Jang’s attempt to reduce the overhead of backing up data (see Jang Para [0044]).
Allowable Subject Matter
Claims 6-8 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not appear to disclose (as recited in claim 6):
skip reading the M data pages of the N data pages from the select row; and program, in a second pass, the select row of the rows of the memory cells based on the N data pages after the first pass, such that each memory cell of the selected row is set to one of the 2N final levels.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Xu, US 20220310158 A1 discloses programming in a first pass.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEROME LARRY LEBOEUF whose telephone number is (571)272-7612. The examiner can normally be reached M-Th: 8:00AM - 6:00PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, RICHARD ELMS can be reached at (517)272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JEROME LEBOEUF/Primary Examiner, Art Unit 2824 - 06/18/2026
Prosecution Insights