DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
General Remarks
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection.
3. When responding to this office action, applicants are advised to provide the examiner with paragraph numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable
interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Specification
5. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
“Method for Wafer Treatment using Laser Processes to form Defect Regions”
Appropriate correction is required.
Claim Objections
6. Claim 2 is objected to because of the following informalities:
Claim 2, ln 5 recites “the focal offset distance.” Because this is the first occurrence of the term “focal offset distance,” said limitation should have an antecedent basis such that claim 2, ln 5 recites “a focal offset distance.”
. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3, ln 15 -17 recites “wherein the first focal offset distance is greater than the first focal offset distance.” Claim 3 is rendered indefinite because the first focal offset distance cannot be greater than itself. The said limitations of claim 3 will be omitted from examination until it is corrected accordingly.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claims 1, 8 and 10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chi, Jingshi et al. (Pub No. US 20240100632 A1) (hereinafter, Chi).
Chi, Fig 3, Wafer with main surface, surface layer and base layer on laser apparatus
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Re Claim 1, Chi teaches a method for a wafer treatment, comprising: providing a wafer (Workpiece; 11; Fig 3; ¶[0033]), wherein the wafer comprises a main surface (Surface of reverse side; 11b; Fig 3; ¶[0033]), a surface layer (Reverse side; 11b; Fig 3; ¶[0033]) and a base layer (Face side; 11a; Fig 3; ¶[0033]),
wherein the surface layer is located between the main surface and the base layer; and
performing at least one laser process (Applying laser beams to workpiece 11; ¶[0045]) to irradiate the surface layer with laser, thereby generating a plurality of defect regions (Modified regions; 19; Figs 11A-11B; ¶[0045]) in the surface layer, and the defect regions form at least one array of defect regions (Line of defect regions; Fig 11A). (See Figs 11A-11B below)
Chi, Figs 11A-11B, Laser beam with four focus spots on wafer
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Re Claim 8, Chi teaches the method for a wafer treatment of claim 1, wherein the at least one array of defect regions (Modified regions; 19; Fig 11A; ¶[0045]) comprises:a first array of defect regions (Modified regions located at focused positions 50c/50d; 19; Fig 11A; ¶[0045]) located at a first depth (First level in y-direction; Fig 11A) below the main surface (Surface of reverse side; 11b; Fig 3; ¶[0033]); and
a second array of defect regions (Modified regions located at focused positions 50a/50b; 19; Fig 11A; ¶[0045]) located at a second depth (Depth below 50c/50d; Fig 11A) below the main surface, wherein,
the first depth is different from the second depth.
Re Claim 10, Chi teaches the method for a wafer treatment of claim 1, further comprising:
performing an annealing treatment (Irradiate the workpiece with laser beam; ¶[0034]) to irradiate the main surface (Surface of reverse side; 11b; Fig 3; ¶[0033]) or the surface layer (Reverse side; 11b; Fig 3; ¶[0033]) of the wafer (Workpiece; 11; Fig 3; ¶[0033]) with laser,
and to change the crystallinity (Change crystallinity by forming cracks and making portions of monocrystalline silicon more brittle; ¶[0034]) of the surface layer.
Claim Rejections - 35 USC § 103
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
11. Claims 2-3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chi, Jingshi et al. (Pub No. US 20240100632 A1) (hereinafter, Chi) as applied to claim 1 above.
Re Claim 2, Chi teaches the method for a wafer treatment of claim 1, wherein performing the at least one laser process comprises:
performing a first laser process (Laser process to create focused spots 50a/50b/50c/50d; Figs 11A-11B; ¶[0070]) to irradiate the surface layer (Reverse side; 11b; Fig 3; ¶[0033]) with laser so that the plurality of defect regions (Modified regions; 19; Fig 5A; ¶[0045]) are arranged along a first direction (X-direction; Figs 11A-11B),
and the focal offset distance (3 to 16 microns; ¶[0072]) is constant (Set at constant intervals; ¶[0072]).
However, Chi does not teach the focal offset distance of the laser is in a range of 0.01 µm to 50 µm below the main surface.
Chi fails to disclose the exact focal offset distance range as claimed.
Nevertheless, as depicted in Figure 11A such features (range of focal offset distance) must possess particular dimensions. The choice of 0.01 µm to 50 µm is matter of engineering design choice; therefore, obvious expedient.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Chi’s focal offset distance range to be 0.01 µm to 50 µm because this would be the best engineering design choice.
In addition, the selection of the particular range as claimed is obvious expedient because given Applicant has not demonstrated the criticality of the specific limitation.
“Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device” – MPEP 2144.04
Re Claim 3, Chi teaches the method for a wafer treatment of claim 1, wherein performing the at least one laser process comprises:
performing a first laser process (Laser process to create focused spots 50a/50b/50c/50d; Figs 11A-11B; ¶[0070]) to irradiate the surface layer (Reverse side; 11b; Fig 3; ¶[0033]) with laser so that the plurality of defect regions (Modified regions; 19; Fig 5A; ¶[0045]) are arranged along a first direction (X-direction; Figs 11A-11B),
wherein performing the first laser process comprises:
sequentially and repeatedly performing a first sub-laser process (First laser beam creating focused spot 50a; ¶[0070]), a second sub-laser process (Second laser beam creating focused spot 50b; ¶[0070]), and a third sub-laser process (Third laser beam creating focused spot 50c; ¶[0070]),
wherein the first sub-laser process has a first focal offset distance (Distance between 50a and 50b/50c; Figs 11A-11B; ¶[0073]), the second sub-laser process has a second focal offset distance (Distance between 50b and 50a/50c; Figs 11A-11B; ¶[0073]) and the third sub-laser process has a third focal offset distance (Distance between 50c and 50a/50b; Figs 11A-11B; ¶[0073]).
However, Chi does not teach and the first focal offset distance, the second focal offset distance and the third focal offset distance are located below the main surface from 0.01 µm to 50 µm.
Chi fails to disclose the exact focal offset distance range as claimed.
Nevertheless, as depicted in Figure 11A such features (range of focal offset distance) must possess particular dimensions. The choice of 0.01 µm to 50 µm is matter of engineering design choice; therefore, obvious expedient.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Chi’s focal offset distance range to be 0.01 µm to 50 µm because this would be the best engineering design choice.
In addition, the selection of the particular range as claimed is obvious expedient because given Applicant has not demonstrated the criticality of the specific limitation.
“Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device” – MPEP 2144.04
Re Claim 9, Chi teaches the method for a wafer treatment of claim 1, wherein, during performing at least one laser process (Applying laser beams to workpiece 11; ¶[0045]), scanning path of the laser is linear (Creating a line of modified regions 19; Fig 11A).
However, Chi does not teach scanning pitch of the laser is 1 µm to 100 µm, and scanning width of the laser is 2 µm to 100 µm.
Chi fails to disclose the exact scanning pitch and scanning width as claimed.
Nevertheless, as depicted in Figure 11A such features (scanning pitch and scanning width) must possess particular dimensions. The choice of 1 µm to 100 µm and 2 µm to 100 µm, respectively, is matter of engineering design choice; therefore, obvious expedient.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Chi's scanning pitch and scanning width because this would be the best engineering design choice.
In addition, the selection of the particular ranges as claimed is obvious expedient because given Applicant has not demonstrated the criticality of the specific limitation.
“Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device” – MPEP 2144.04
12. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chi, Jingshi et al. (Pub No. US 20240100632 A1) (hereinafter, Chi) as applied to claim 1 above, and further in view of Kurokawa, Yuto et al. (Pub No. US 20160104620 A1) (hereinafter, Kurokawa).
Re Claim 4, Chi teaches the method for a wafer treatment of claim 1, wherein performing the at least one laser process comprises:
performing a first laser process (Laser process to create focused spots 50a/50b; Figs 11A-11B; ¶[0070]) to irradiate the surface layer (Reverse side; 11b; Fig 3; ¶[0033]) with laser so that some of the plurality of defect regions (Modified regions; 19; Fig 5A; ¶[0045]) are arranged along a first direction (X-direction; Figs 11A-11B),
and the focal offset distance (3 to 16 microns; ¶[0072]) is constant (Set at constant intervals; ¶[0072]); and
performing a second laser process (Laser process to create focused spots 50c/50d; Figs 11A-11B; ¶[0070]) to irradiate the surface layer with laser to so that others of the plurality of defect regions are arranged along a second direction (Y-direction, such that 50c/50d are above 50a/50b; Figs 11A-11B), and the focal offset distance is constant, wherein,
and the focal offset distance (Distance between 50a and 50b/50c; Figs 11A-11B; ¶[0073]) of the first laser process and the focal offset distance of the second laser process (Distance between 50b and 50a/50c; Figs 11A-11B; ¶[0073]) are the same or different from each other (Set at constant intervals; ¶[0072]),
the first laser process and the second laser process are sequentially and repeatedly performed (The laser may be branched into four separate laser beams which move along the x-direction in sequence; ¶¶[0070,0071]).
However, Chi does not teach an included angle is between the first direction and the second direction, and the included angle is 30 to 90 degrees,
wherein the focal offset distance of the laser is 0.01 µm to 10 µm below the main surface.
In the same field of endeavor, Kurokawa teaches an included angle (Angle of 30 degrees; X1; Fig 4; ¶[0026]) is between the first direction and the second direction, and the included angle is 30 to 90 degrees. (See Fig 4 below)
Kurokawa, Fig 4, Laser paths on wafer at angle to crystal axes a1, a2 and a3
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used an included angle is between the first direction and the second direction, and the included angle is 30 to 90 degrees, as taught by Kurokawa for the method of wafer treatment as taught by Chi. One would have been motivated to do this with a reasonable expectation of success because the size of the non-crystalline regions are kept optimum with a laser trajectory which has an non-parallel angle to the crystal axes (a1/a2/a3) of the wafer, as suggested by Kurokawa (¶[0027]).
However, Chi in view of Kurokawa does not teach wherein the focal offset distance of the laser is 0.01 µm to 10 µm below the main surface.
Chi fails to disclose the exact focal offset distance range as claimed.
Nevertheless, as depicted in Figure 11A such features (range of focal offset distance) must possess particular dimension. The choice of 0.01 µm to 50 µm is matter of engineering design choice; therefore, obvious expedient.
Therefore, it would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify Chi's focal offset distance range to be 0.01 µm to 50 µm because this would be the best engineering design choice.
In addition, the selection of the particular range as claimed is obvious expedient because given Applicant has not demonstrated the criticality of the specific limitation.
“Where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device” – MPEP 2144.04
13. Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Chi, Jingshi et al. (Pub No. US 20240100632 A1) (hereinafter, Chi) in view of Kurokawa, Yuto et al. (Pub No. US 20160104620 A1) (hereinafter, Kurokawa) as applied to claim 4 above, and further in view of Seddon, Michael J. et al. (Pub No. US 20190326117 A1) (hereinafter, Seddon).
Re Claim 7, Chi in view of Kurokawa does not teach the method for a wafer treatment of claim 4,
wherein the first laser process and the second laser process have a same pulse energy.
In the same field of endeavor, Seddon teaches the method for a wafer treatment of claim 4, wherein the first
laser process (Laser process to form damage layer at first depth where spot 38 is located; Fig 3; ¶[0067]) and the second laser process (Laser process to form damage layer at second depth where spot 40 is located; Fig 3; ¶[0067]) have a same pulse energy (Two or more laser beams may have same pulse energy, which may be used for either the first or second laser process; ¶[0072]). (See Fig 3 below)
Seddon, Fig 3, SiC substrate being irradiated by a laser on a second surface
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Accordingly, it would have been obvious for a person having ordinary skill in the art before the effective filing date of the invention to have used a first laser process and a second laser process having a same pulse energy, as taught by Seddon for the method of wafer treatment as taught by Chi. One would have been motivated to do this with a reasonable expectation of success because the two lasers must have equal pulse energy to create damage layers with consistent depth and brittleness within the wafer.
Allowable Subject Matter
14. Claims 5-6 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The closest prior art Chi, Jingshi et al. (Pub No. US 20240100632 A1) (hereinafter, Chi) and Kurokawa, Yuto et al. (Pub No. US 20160104620 A1) (hereinafter, Kurokawa) either singularly or in combination fails to anticipate or render obvious
“The method for a wafer treatment of claim 1, wherein performing the at least one laser process comprises:
performing a first laser process to irradiate the surface layer with laser, so that some of the plurality of defect regions are arranged along a first direction, wherein performing the first laser process comprises:
sequentially and repeatedly performing a first sub-laser process, a second sub-laser process and a third sub-laser process,
wherein the first sub-laser process has a first focal offset distance, the second sub-laser process has a second focal offset distance and the third sub-laser process has a third focal offset distance, and the first focal offset distance, the second focal offset distance and the third focal offset distance are 0.01 pm to 10 pm below the main surface; and
performing a second laser process to irradiate the surface layer with laser so that others of the plurality of defect regions are arranged along a second direction,
wherein performing the second laser process comprises: sequentially and repeatedly performing a fourth sub-laser process, a fifth sub-laser process and a sixth sub-laser process,
wherein the fourth sub-laser process has a fourth focal offset distance, the fifth sub-laser process has a fifth focal offset distance and the sixth sub-laser process has a sixth focal offset distance, and the fourth focal offset distance, the fifth focal offset distance and the sixth focal offset distance are 0.01 pm to 50 pm below the main surface, wherein,
an included angle is between the first direction and the second direction, and the included angle is 30 degrees to 90 degrees,
the first focal offset distance is greater than the second focal offset distance,
the second focal offset distance is greater than the third focal offset distance,
the fourth focal offset distance is greater than the fifth focal offset distance,
and the fifth focal offset distance is greater than the sixth focal offset distance,
and any one of the first focal offset distance, the second focal offset distance and the third focal offset distance is different from any one of the fourth focal offset distance, the fifth focal offset distance and the sixth focal offset distance,"
in combination with all other limitations in the claim(s) as claimed and defined by applicant.
In the instant case, Chi and Kurokawa do not render obvious the limitations “the first focal offset distance is greater than the second focal offset distance, the second focal offset distance is greater than the third focal offset distance, the fourth focal offset distance is greater than the fifth focal offset distance, and the fifth focal offset distance is greater than the sixth focal offset distance,” as neither disclose a fourth, fifth, and/or sixth focal offset distance.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
[1] Ran, Qing et al. (Pub No. US20230253251A1) discloses a method of manufacturing a semiconductor package includes forming a plurality of first cuts in a semiconductor wafer. The first cuts extend through a first portion of a thickness of the semiconductor wafer and include a first set of first cuts that are parallel to one another and a second set of first cuts that are parallel to one another and perpendicular to the first set of first cuts. In addition, the method includes forming a plurality of second cuts in the wafer after forming the first cuts. The second cuts are vertically aligned with the first cuts and extend through a second portion of the thickness of the semiconductor wafer. The second cuts include a first set of second cuts that are parallel to one another and a second set of second cuts that are parallel to one another and perpendicular to the first set of second cuts.
[2] Bernard, Benjamin et al. (Pub No. US20220339740A1) discloses a method of splitting a semiconductor work piece includes: forming a separation zone within the semiconductor work piece, wherein forming the separation zone comprises modifying semiconductor material of the semiconductor work piece at a plurality of targeted positions within the separation zone in at least one physical property which increases thermo-mechanical stress within the separation zone relative to a remainder of the semiconductor work piece, wherein modifying the semiconductor material in one of the targeted positions comprises focusing at least two laser beams to the targeted position; and applying an external force or stress to the semiconductor work piece such that at least one crack propagates along the separation zone and the semiconductor work piece splits into two separate pieces. Additional work piece splitting techniques and techniques for compensating work piece deformation that occurs during the splitting process are also described.
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/T.E.D./
Examiner
Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817