DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/03/26 was filed after the mailing date of the Non-Final Rejection on 01//28/26. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and a prior art (such as US 20220320312) of this IDS is used by the current Office Action, making it - Final.
Acknowledgement of Amendment
Applicant amendment filed 04/27/26 has been acknowledged.
Applicant amended Claims 1, 9, 16, and cancelled Claims 12 and 17.
Status of Claims
Claims 1-11, 13-16, and 18-20 are examined on merits herein.
Specification
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required:
Amended Claim 9 contains limitations from the original Claim 12 that recite: “the first region comprises a first side surface that extends in the second direction, wherein the second region comprises a second side surface that extends in the second direction, wherein the third region comprises a third side surface that connects the first side surface to the second side surface”. However, the specification fails to teach a third side surface of the third region that connects the first side surface of the first region and the second side surface of the second region. As a reminder, the specification of the current application teaches first through fourth side surfaces (SW1-SW4) only with respect to the third region.
Claim 15 recites: “the source/drain pattern comprises a first-region source/drain pattern and a second-region source/drain pattern on the first and second regions, respectively”. Claim 15 depends on Claim 9 that teaches first and second regions as being channel regions, while the specification of the current application does not teach that any source/drain regions are disposed on any channel region and does not support the recitation of Claim 15. Source/drain regions of the current application are adjacent to corresponding channel regions; paragraph 0023 of the published application state that channel patterns and source/drain patterns are alternatively arranged in the second direction – see, in addition, Annotated Fig. 3A of the current application showing dispositions of the channels (CH1) and source/drain regions (SD1), supporting the recitation of paragraph 0023:
Annotated Fig. 3A
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Claim Objections
Claim 13 is objected to because of the following informalities:
Claim 13 recites: “the semiconductor device of claim 12”. However, the last amendment to the application cancelled Claim 12. Accordingly, Examiner suggests changing the recitation to: “the semiconductor device of claim 9”, and Claim 13 was examined by the current Office Action in the assumption that the above suggestion is implemented.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-11 and 13-15 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In re Claim 1: Amended Claim has a recitation: “wherein the connection side surface is configured such that a width off the buffer channel pattern discontinuously changes from the first width to the second width”. The recitation is unclear, since conflict with the specification, teaching (paragraph 0073 of the published application) of an “abrupt” change of the width of the buffer channel pattern, not “discontinuous” change.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022], inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971).
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited recitation of claim 1 was interpreted as: “wherein the connection side surface is configured such that a width off the buffer channel pattern abruptly changes from the first width to the second width”.
In re Claims 2-8: Claims 2-8 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 1.
In re Claim 9: Amended Claim 9 incorporates a recitation of the original Claim 12 that was rejected by the Non-Final Rejection under 35 U.S.C. 112(b): “the first region comprises a first side surface that extends in the second direction, wherein the second region comprises a second side surface that extends in the second direction, wherein the third region comprises a third side surface that connects the first side surface to the second side surface”. The recitation is unclear, since it is not supported by the specification of the application that teaches first through third (and fourth) side surfaces only with respect to the third (buffer) region.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022], inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971).
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited recitation of Claim 9 was interpreted in accordance with the specification of the application (e.g., where it describes Figs. 6B and 7B) as: “the third region comprises first, second, and third side surfaces that extend in the second direction, wherein the third side surface connects the first side surface to the second side surface”.
In re Claim 15: Claim 15 recites: “the source/drain pattern comprises a first-region source/drain pattern and a second-region source/drain pattern on the first and second regions, respectively”, where first and second regions are identified as channel regions by Claim 9, on which Claim 9 depends. The recitation is unclear as contradicting to the specification, not teaching that the source/drain regions are disposed on channel regions, as is shown in the Objection to the Specification.
In accordance with MPEP 2173.03 Correspondence Between Specification and Claims [R-07.2022] inconsistence of the claim with the specification makes the claim indefinite, even though the terms of a claim may appear to be definite: see In re Cohn 438 F.2d 989, 169 USPQ 95 (CCPA 1971),
Appropriate correction is required to clarify the claim language.
For this Office Action, the cited limitation was interpreted as: “the source/drain pattern comprises a first-region source/drain pattern and a second-region source/drain pattern adjacent to the first and second regions, respectively”. Claim 15 was examined by the current Office Action in the assumption that the above suggestion is implemented.
In re Claims 10-11 and 13-14: Claims 10-11 and 13-14 are rejected under 35 U.S.C. 112(b) due to dependency on Claim 9.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As far as the claims are understood, Claims 9-11, 13, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2022/0320312).
In re Claim 9, Park teaches a semiconductor device, comprising (Figs. 1A and 1C, when having a cross-section shown in Fig. 7 - not in Fig. 1B, e.g., when having a dummy gate electrode 175 made similar to a gate electrode 160, paragraph 0085):
an active region 105 on a substrate 110 (paragraph 0029);
a source/drain pattern 150 on the active region 105 (paragraph 0029);
a channel pattern 140 (paragraph 0029) on the active region 105 and electrically connected to the source/drain pattern 150 (paragraph 0038),
the channel pattern 140 comprising a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other;
a gate electrode – comprising electrodes 165 and 175 (paragraph 0030, paragraph 0085) - that is on the channel pattern 140 and extends in a first direction Y (as in Fig. 1A), the gate electrode having a first horizontal width MW1 (Fig. 1A, paragraph 0044) in a second direction X that intersects the first direction Y; and
an active contact 185 (paragraph 0061) electrically connected to the source/drain pattern 150,
wherein the channel pattern 140 comprises:
a first region 140W in WS (paragraph 0036) that has a first width WW2 (equal to W2) in the first direction Y (paragraphs 0034, 0039);
a second region 140N in NS (paragraph 0036) that has a second width NW1 (equal to W1) in the first direction Y (paragraphs 0034, 0039) – or – when the first and second regions are identified opposite to the above description, such as the first region is 140N and the second region is 140W – as it could be appropriate for Claim 11 (with correspondingly changing other identification below); and
a third region 140d in TS (paragraphs 0036, 0038) between the first region in WS and the second region in NS, the third region TS having a varying channel third width (obviously, similar to TP in the source/drain region, paragraphs 0034-0035, 0039) in the first direction Y,
wherein the third region has a third width W3 in the first direction Y (paragraph 0034),
wherein the third region has a second horizontal width “MW2 minus a portion from the edge of TS to an edge of gate 170” (paragraph 0055) in the second direction X (Fig. 1A), and
wherein the second horizontal width is smaller than the first horizontal width MM1,
wherein the third region comprises a first side surface FSS (as in Annotated Portion of Fig. 1A, paragraph 0039; the limitation is examined in accordance with the claim interpretation) that extends in the second direction X,
Annotated Portion of Fig. 1A
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wherein the third region comprises a second side surface SSS (as in Annotated Portion of Fig. 1A, paragraph 0039; the limitation is examined in accordance with the claim interpretation) that extends in the second direction X,
wherein the third region comprises a third side surface TSS (as in Annotated Portion of Fig. 1A, paragraph 0039) that connects the first side surface FSS to the second side surface SSS, and
wherein the third side surface TSS has a non-linear profile, when viewed in a plan view.
In re Claim 10, Park teaches the semiconductor device of Claim 9 as cited above, wherein (Fig. 1A) the first width WW2 (equal to W2) is larger than the second width NW1 (equal to W1), and wherein the third width TP of the third region gradually decreases as a distance from the first region increases in a direction toward the second region.
In re Claim 11, Park teaches the semiconductor device of Claim 9 as cited above, wherein (Fig. 1A and using “alternative identification” appropriate for Claim 11 – in Claim 9) the first width NW1 (equal to W1) is smaller than the second width WW2 (equal to W2), and wherein the third width TP of the third region gradually increases as a distance from the first region increases in a direction toward the second region.
In re Claim 13, Park teaches the semiconductor device of Claim 12 (e.g., of Claim 9 – in accordance with the claim interpretation) as cited above, wherein the third region further comprises a fourth side surface FOSS (As in Annotated Portion of Fig. 1A) and wherein the third TSS and fourth FSS side surfaces of the third region are opposite to each other.
In the embodiment of Figs. 1A, 1C, and 7, Park does not teach that the fourth side surface has a non-liner profile. However, in an embodiment of Fig. 6, Park teaches that a fourth surface of the third region (under dummy gate 170) has a non-liner profile.
It would have been obvious for one of ordinary skill in the art before the effective date of filing the application to modify the Park structure of Claim 9 by creating both – the third and fourth side surfaces having a non-liner profile, as is shown in Fig. 6, when such shape of the third region is preferred. Note that in accordance with In accordance with MPEP 2144.04. I.B, referencing In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966), the court held that changes in shape is not patentable since this is a matter of choice of a person of ordinary skill in the art in absent persuasive evidence that the particular configuration is significant.
In re Claim 15, Park teaches the semiconductor device of Claim 9 as cited above, wherein (Fig. 1A) the source/drain pattern comprises a first-region source/drain pattern 150W (paragraph 0049) and a second-region source/drain pattern 150N (paragraph 0049) on the first and second regions, respectively (e.g., “adjacent to first and second regions”, in accordance with the claim interpretation), and wherein a largest width W2 of the first-region source/drain pattern 150W in the first direction Y is larger than a largest width W1 of the second-region source/drain pattern 150N in the first direction Y.
Claims 16 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park in view of Park et al. (US 2022/0173053) – Park-1, hereafter.
In re Claim 16, Park teaches a semiconductor device, comprising (Figs. 1A, 1C, and 7, paragraph 0085 explains how Fig. 7 is used instead of Fig. 1B):
a substrate 101 that includes an active region 105 (paragraph 0029);
a device isolation layer 110 (Fig. 1C, paragraph 0029) that defines the active region 105;
source/drain patterns 150 (paragraph 0029) on the active region 105;
channel patterns 140 (140W, 140N, 140d, paragraphs 0029, 0038-0039) on the active region 105 and electrically connected to respective pairs of the source/drain patterns 150 (paragraph 0038), each of the channel patterns comprising a plurality of semiconductor patterns that are vertically stacked and spaced apart from each other (as Fig. 7 shows);
gate electrodes 165, 175 (paragraphs 0030, 0085) that are on the channel patterns 140, respectively, and extend in a first direction Y (Fig. 1A) parallel to each other;
gate insulating layers 163, 173 (paragraphs 0041, 0085), each of the gate insulating layers between a respective one of the gate electrodes 165 or 175 and a respective one of the channel patterns 140;
gate spacers 164, 174 (paragraphs 0041, 0085), each of the gate spacers on a side surface of a respective one of the gate electrodes;
gate capping patterns 166, 176 (paragraphs 0041, 0085) each of the gate capping patterns on a top surface of a respective one of the gate electrodes;
active contacts 185 (paragraph 0061) that are electrically connected to the source/drain patterns 150, respectively;
metal-semiconductor compound layers 181 (paragraph 0061), each of the metal-semiconductor compound layers 181 between a respective one of the active contacts 185 and a respective one of the source/drain patterns 150;
wherein the channel patterns comprise a first subset 140W (Fig. 7, paragraph 0039) of the channel patterns 140, each of which has a first width WW2 (equal to W2, Fig. 7, paragraph 0039) in the first direction Y, and a second subset 140N (Fig. 7, paragraph 0039) of the channel patterns 140, each of which has a second width NW1 (equal to W1, paragraph 0039) in the first direction Y,
wherein the channel patterns further comprise a buffer channel pattern 140d (Fig. 7, paragraph 0038) between the first subset 140W and the second subset 140N of the channel patterns, and
wherein the buffer channel pattern – in region TS of Figs. 7 and 1A - is configured such that a width of the buffer channel pattern 140d changes from the first width W2 (at the left border of TS Fig. 1A, paragraph 0039) to the second width W1 (at the right border of TS, Fig. 1, paragraph 0039) when moving from the first subset 140W to the second subset 140N of the channel patterns,
wherein the source/drain patterns 150 comprise a first-region source/drain pattern 150W (paragraph 0049, Figs. 7 and 1A) electrically connected to one of the first subset 140W of the channel patterns and a second-region source/drain pattern 150N electrically connected to one of the second subset of the channel patterns 140N (paragraph 0049), and
wherein a largest width of the first-region source/drain pattern 150W in the first direction Y is larger than a largest width W2a of the second-region source/drain pattern 150N in the first direction (Fig. 1A, paragraphs 0034, 0050, where the largest width of the first-region source/drain pattern 150W extends along W2 in the manner similar to W2a in region 150N).
Park does not teach an interlayer insulating layer on the gate capping pattern, does not teach that the active contacts extend into the interlayer insulating layer, and does not teach gate contacts that extend into the interlayer insulating layer and the gate capping pattern and are electrically connected to the gate electrodes, respectively, as well as does not teach a first metal layer on the interlayer insulating layer, the first metal layer comprising first interconnection lines that are electrically connected to at least one of the active contacts and the gate contacts and a second metal layer on the first metal layer, the second metal layer comprising second interconnection lines that are electrically connected to the first metal layer.
Park-1 teaches (Figs. 2A-2H) a semiconductor device comprised:
an interlayer insulating layer 120 (paragraph 0066);
active contacts AC (Fig. 2A, paragraph 0068) extend into the interlayer insulating layer 120 (paragraph 0066),
gate contacts GC (Fig. 2C, paragraph 0071) extending into the interlayer insulating layer 120 and the gate capping pattern CP (paragraph 0069);
a first metal layer M1 (paragraph 0072) on the interlayer insulating layer 120, the first metal layer M1 comprising first interconnection lines IL1 (paragraph 0072) that are electrically connected to at least one of the active contacts and the gate contacts (Figs. 2A-2C); and
a second metal layer M2 (paragraph 0075) on the first metal layer M1, the second metal layer M2 comprising second interconnection lines IL2 that are electrically connected to the first metal layer M1.
Park and Park-1 teach analogous arts directed to semiconductor devices comprised transistors with all-around gates and also comprised a buffer region, and one of ordinary skill in the art before filing the application would have had a reasonable expectation of success in modifying the Park device in view of the Park-1 device since they are from the same field of endeavor, and Park-1 created a successfully operated device.
It would have been obvious for one of ordinary skill in the art before filing the application to modify the Park device by adding all elements the device lacks and the Park-1 device has, wherein it is required to provide external electrical connections to the Liaw semiconductor device.
In re Claim 18, Park/Park-1 teaches the semiconductor device of Claim 16 as cited above, wherein the first width is different from the second width.
In re Claim 19, Park/Park-1 teaches the semiconductor device of Claim 16 as cited above.
Park further teaches (Fig. 1A) that the buffer channel pattern 114d comprises a connection side surface TP that extends in the first direction Y.
In re Claim 20, Park/Park-1 teaches the semiconductor device of Claim 19 as cited above.
Park further teaches that the buffer channel pattern comprises (Annotated Portion of Fig. 1A above) a first side surface FSS that is adjacent to the first subset of the channel patterns 114W and extends in a second direction X intersecting the first direction Y, and a second side surface SSS that is adjacent to the second subset of the channel patterns 114N and extends in the second direction X, wherein the connection side surface TB connects the first side surface FSS to the second side surface SSS.
Allowable Subject Matter
Claims 1 and 14, as interpreted, contain allowable subject matter.
Reason for Identification of Allowable Subject Matter
Re Claim 1: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 1 as: “the connection side surface is configured such that a width of the buffer channel pattern abruptly changes from the first width to the second width when moving from the first subset to the second subset of the channel patterns”, in combination with other limitations of the claim.
Re Claim 14: The prior arts of record, alone or in combination, fail(s) to anticipate or render obvious such limitation of Claim 14 as: “a width of the fourth side surface in the first direction is different from a width of the third side surface in the first direction”, in combination with all limitations of Claims 9 and 13, on which Claim 14 depends.
The prior arts of record include all prior arts cited by the current and previous Office Actions.
Response to Arguments
Applicant’ arguments (REMARKS, filed 04/27/26) have been fully considered.
Examiner agreed with a portion of interview presented by the Interview Summary (page 8), but reminds that the Interview Summary also pointed out that rejections under 35 U.S.C. 112(b) shall be corrected. It looks like incorporation of limitations of Claim 12 into Claim 9 was made without correcting these limitations for 112(b) issue presented by the Non-Final Rejection mailed 01/28/26.
Examiner agrees that Claim 17 was indicated as comprising allowable subject matter by the Non-Final Rejection. However, the new prior arts presented by the applicant in the IDS filed 03/03/26 teaches limitations that were earlier indicated as allowable. Examiner suggests that it would be better, for prosecution the application, presenting this IDS before the initial examination.
Examiner agrees with Applicant regarding Drawings (REMARKS, pages 8-9) – the current Office Action has no objections to the drawings.
Examiner disagrees with arguments (REMARKS, page 9) related to rejection of Claim 12 under 112(b): Side surfaces of channels RG1 and RG2 are not connected by a side surface of RG3, since all adjacent channels are separated by source/drain regions SD, as Annotated Fig. 6B (Reproduced below) clearly shows:
Annotated Fig. 6B
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Paragraph 0082 referenced by Applicant with respect to Figs. 6A-6B, teaches that channels of region RG3 are just placed between RG1 and RG2, and does not teach any connection betweenRG1 and RG2 by RG3.
Examiner further disagrees with arguments (REMARKS, page 9) related to rejection of Claim 15 under 35 U.S.C. 112(b): Examiner does not view Fig. 6B as having source/drain regions – with width SDW – as being disposed on channel patterns SP1 or SP2, but views this figure as having source and drain regions as separating channel regions. Please, be reminded that paragraph 0023 of the published application teaches that channel regions and source/drain regions alternate in the second direction – e.g., source/drain regions are not disposed on the channel regions.
In view of comments for Claims 12 and 15, Examiner disagrees with Applicant (REMARKS, page 9) that the specification of the application is free from objections.
Examiner agrees with the amendment to Claim 1 (REMARKS, page 10), and this amendment shows that at some point, Applicant agrees that channels of different regions are separated by source/drain regions, which makes it unclear arguments related to Claim 12.
Examiner disagrees with incorporating limitations of Claim 12 into Claim 9 without correcting grounds for rejection under 112(b) (REMARKS, pages 10-11).
As it shown above, Examiner disagrees with the Applicant understanding of Claim 15 (REMARKS, page 11).
Also Examiner disagrees with using a word “discontinuously” (REMARKS, page 11 for Claim 1), the prior arts of record do not anticipate and do not make obvious Claim 1.
Examiner views Claim 9 (REMARKS, pages 11-12) as being amended without correcting the 112(b) issue; in addition, as it was explained during the interview, the prior art cited by the IDS submitted on 03/03/26 makes Claim 9 obvious.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication should be directed to GALINA G YUSHINA whose telephone number is 571-270-7440. The Examiner can normally be reached between 8 AM - 7 PM Pacific Time (Flexible).
Examiner interviews are available. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Lynne Gurley can be reached on 571-272-1670.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300; a fax phone number of Galina Yushina is 571-270-8440.
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/GALINA G YUSHINA/Primary Patent Examiner, Art Unit 2811, TC 2800,
United States Patent and Trademark Office
E-mail: galina.yushina@USPTO.gov
Phone: 571-270-7440
Date: 06/08/26
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