DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 3, 4, and 9 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 3, 4, and 9 use the acronyms “FEM” and “PCB”. Acronyms must be defined the first time they are used in each claim group.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 5-11, and 15-17 is/are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Cao et al. US 2018/0322234 A1 (“Cao”).
As to claim 1, Cao discloses a semiconductor design optimization system comprising:
a data base configured to store design data (Figures 4 or 7);
a training data preprocessing unit configured to obtain the design data from the data base and preprocess the design data, resulting in training data (Figures 4 or 7 or Paragraphs 43 or 55 – e.g., necessary in use of machine learning and training data repositories);
a data learning unit configured to generate a physical property prediction model by training using the training data (Figure 7 or Paragraphs 43 or 55 – e.g., model training, Paragraph 45 – e.g., physical attribute prediction);
a physical property prediction unit configured to generate predicted physical property data including information associated with predicted physical property values for each region of a semiconductor device to be fabricated, wherein the physical property prediction unit is configured to input, into the physical property prediction model, input data including information associated with design drawings of the semiconductor device to be fabricated (Figure 7 or Paragraph 45 – e.g., physical attribute prediction of an entire layout using inputs including a proposed layout and actual manufactured circuit data, e.g., Paragraphs 46-49); and
a layout generator configured to generate a design layout for the semiconductor device to be fabricated, wherein the design layout is optimized to distribute the predicted physical property values for each region of the semiconductor device by modifying the design drawings based on the predicted physical property data (Figure 7 or Paragraphs 54-55 – e.g., adjusting mask shapes to reduce manufacturing variability).
As to claim 5, Cao discloses the system of claim 1. Cao further discloses wherein the data base is configured to store the design layout, and wherein the physical property prediction model is configured to train using the design layout (Figure 7 or Paragraphs 45 or 54 – e.g., iterative adjustment, physical attribute prediction, and model training of an entire layout using inputs including a proposed layout and actual manufactured circuit data).
As to claim 6, Cao discloses the system of claim 1. Cao further discloses wherein the input data includes information associated with patterns of wires or circuits arranged on the design drawings of the semiconductor device to be fabricated (Figure 7 or Paragraphs 45 or 54 – e.g., a proposed layout and actual manufactured circuit data).
As to claim 7, Cao discloses the system of claim 6. Cao further discloses wherein the physical property prediction unit is configured to generate sub-predicted property data for each of the design drawings (Paragraph 45 – e.g., calculation for various physical attributes).
As to claim 8, Cao discloses the system of claim 7. Cao further discloses wherein the physical property prediction unit is configured to generate the predicted physical property data of the semiconductor device based on the sub-predicted property data of the design drawings (Paragraph 45 – e.g., evaluation of PSGs based on the various physical attributes).
As to claim 9, Cao discloses the system of claim 8. Cao further discloses wherein the semiconductor device includes a PCB substrate, a semiconductor substrate, a package substrate, a semiconductor chip, or a semiconductor package (Paragraphs 2-5 – e.g., an IC layout).
As to claim 10, Cao discloses the system of claim 1. Cao further discloses an input data preprocessing unit configured to generate preprocessed input data by preprocessing the input data, and wherein the physical property prediction unit is configured to generate the predicted physical property data of the input data by inputting the preprocessed input data into the physical property prediction model (Figures 4 or 7 or Paragraphs 43 or 55 – e.g., use of multiple libraries and data from manufactured circuits in order to predict results and iteratively train a model).
Claims 11 and 15-17 recite elements similar to claims 1 and 5-8, and are rejected for similar reasons.
Allowable Subject Matter
Claims 2-4 and 12-14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or suggest a system or method for semiconductor design optimization having the combination of elements/steps of the claims including, among other elements, the property and image processing elements of the claims, in combination with the training, analysis, and prediction details of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYCE M AISAKA whose telephone number is (571)270-5808. The examiner can normally be reached M-F: 6:30AM-5:00PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571)272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYCE M AISAKA/Primary Examiner, Art Unit 2851
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