Prosecution Insights
Last updated: October 02, 2026

Examiner: AISAKA, BRYCE M

Tech Center 2800 • Art Units: 1737 2825 2851

This examiner grants 87% of resolved cases

Analysis

Bryce M Aisaka is an examiner in Tech Center 2800, working in Art Unit 1737. The examiner has 747 resolved cases. The allowance rate for these cases is 87.4 percent. This rate indicates a favorable probability of success for applications assigned to this examiner.

The interview lift is 10.5 percent. While the baseline allowance rate is 87.4 percent, the 10.5 percent lift suggests that interviews can still provide a benefit. Practitioners should consider an interview as a way to further ensure a positive outcome in Art Unit 1737.

The median days to allowance is 853. This timeframe is a duration for the patent prosecution process. With 747 resolved cases, the examiner has a record in Tech Center 2800. The combination of an 87.4 percent allowance rate and an 853 day median provides an outlook for applicants.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

87.4%
Allow Rate
+19.4% vs TC avg
751
Total Applications
+10.5%
Interview Lift
854
Avg Prosecution Days
Based on 747 resolved cases, 2023–2026

Rejection Statute Breakdown

20.0%
§101 Eligibility
20.8%
§102 Novelty
32.9%
§103 Obviousness
23.0%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18404626 METHOD FOR GENERATING LEARNING MODEL FOR PREDICTING SEMICONDUCTOR DEVICE STRUCTURE AND APPARATUS FOR PREDICTING SEMICONDUCTOR DEVICE STRUCTURE Non-Final OA SAMSUNG ELECTRONICS CO., LTD.
18418425 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING AND DESIGNING Non-Final OA NXP B.V.
18457619 SERIES-CONNECTED BATTERY PACKS, SYSTEM AND METHOD Final Rejection MILWAUKEE ELECTRIC TOOL CORPORATION
18395753 DEVICE, METHOD, AND COMPUTER-READABLE MEDIUM FOR FORMAL VERIFICATION OF A CIRCUIT DESIGN Non-Final OA INTEL CORPORATION
18215514 CELL ROWS WITH MIXED HEIGHTS AND MIXED NANORIBBON WIDTHS Non-Final OA Intel Corporation
18361532 METHOD OF PREDICTING FAILURE IN A CIRCUIT DESIGN CAUSED BY NOISE IMPACT Final Rejection INTERNATIONAL BUSINESS MACHINES CORPORATION
18481866 METHOD AND APPARATUS FOR SIMULATION MODELLING Non-Final OA TEXAS INSTRUMENTS INCORPORATED
18408782 DEVICE HAVING ALTERNATING ROWS OF CORRESPONDING FIRST AND SECOND ROW-ARCHITECTURES AND METHOD OF MANUFACTURING SAME Non-Final OA TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
18512411 CONDUCTOR SCHEME SELECTION AND TRACK PLANNING FOR MIXED-DIAGONAL-MANHATTAN ROUTING Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18346113 METHOD OF PRODUCING MASK DATA FOR SEMICONDUCTOR DEVICE MANUFACTURING Non-Final OA Taiwan Semiconductor Manufacturing Co., Ltd.
18545662 I/O CIRCUIT, SEMICONDUCTOR DEVICE, CELL LIBRARY, AND METHOD OF DESIGNING CIRCUIT OF SEMICONDUCTOR DEVICE Non-Final OA ROHM CO., LTD.
18560283 METAL-INSULATOR-METAL CAPACITOR INSERTION Non-Final OA Synopsys, Inc.

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