DETAILED ACTION
This correspondence is in response to the communications received June 6, 2023. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Objections
Claim 8 and the claims that depend therefrom are objected to because of the following informalities: On lines 1 and 2, the recitation of “plurality of gate insulating layer”, should read as “plurality of gate insulating layers”. Appropriate correction is required.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
PNG
media_image1.png
700
588
media_image1.png
Greyscale
PNG
media_image2.png
672
596
media_image2.png
Greyscale
Regarding claim 1, the Applicant discloses in Figs. 2 and 3, a semiconductor device comprising:
a plurality of bit lines (BL) each extending in a first direction (D1) on a substrate (110) and spaced apart from each other in a second direction (D2) perpendicular to the first direction;
a plurality of semiconductor patterns (AP) respectively disposed on the plurality of bit lines,
the plurality of semiconductor patterns comprising a first semiconductor pattern disposed on a first bit line from among the plurality of bit lines, and a second semiconductor pattern arranged to be offset in the second direction from the first semiconductor pattern on the first bit line (Examiner understands this limitation to identify one AP located for example on a right side region of a given BL, and a second AP located on a left side region of the same BL, see Fig. 2);
a plurality of word lines (WL) each extending in the second direction (D2) and surrounding a sidewall of each of the plurality of semiconductor patterns (see Fig. 2),
the plurality of word lines (WL) comprising a first word line (one of the WL) extending in the second direction and surrounding the first semiconductor pattern, and a second word line (another of the WL) spaced apart in the first direction (D1) from the first word line and extending in the second direction while surrounding the second semiconductor pattern; and
a plurality of storage nodes (SN) respectively disposed on the plurality of semiconductor patterns (SN surrounding AP, and SN wrapped by WL).
Regarding claim 13, the Applicant discloses in Fig. 2 and 3, a semiconductor device comprising:
a plurality of bit lines (BL) each extending in a first direction (D1) on a substrate (110) and spaced apart from each other in a second direction (D2) perpendicular to the first direction;
a plurality of semiconductor patterns (AP) disposed on each of the plurality of bit lines and arranged in a hexagonal array (see Fig. 2),
the plurality of semiconductor patterns comprising:
a plurality of first semiconductor patterns disposed on a first bit line from among the plurality of bit lines and located at a first distance from a first sidewall of the first bit line, and a plurality of second semiconductor patterns located at a second distance that is greater than the first distance from the first sidewall on the first bit line (AP being offset from a first sidewall of BL, so one AP is closer to the left most sidewall of BL, whereas another AP is located farther from the same left most sidewall of BL);
a plurality of word lines (WL) each extending in the second direction (D2) and surrounding a sidewall of each of the plurality of semiconductor patterns (see Fig. 2); and
a plurality of storage nodes (SN) respectively disposed on the plurality of semiconductor patterns (SN surrounding AP, see Fig. 2).
Regarding claim 19, the Applicant discloses in Figs. 2 and 3, a semiconductor device comprising:
a plurality of bit lines (BL) each extending in a first direction (D1) on a substrate (110) and spaced apart from each other in a second direction (D2) perpendicular to the first direction;
a plurality of semiconductor patterns (AP) disposed on each of the plurality of bit lines and arranged in a hexagonal array (see Fig. 2),
the plurality of semiconductor patterns comprising a plurality of first semiconductor patterns disposed on a first bit line from among the plurality of bit lines and located at a first distance from a first sidewall of the first bit line, and a plurality of second semiconductor patterns located at a second distance that is greater than the first distance from the first sidewall on the first bit line (AP being offset from a first sidewall of BL, so one AP is closer to the left most sidewall of BL, whereas another AP is located farther from the same left most sidewall of BL);
a plurality of word lines (WL) each extending in the second direction (D2) and surrounding a sidewall of each of the plurality of semiconductor pattern (WL surrounding AP);
a plurality of gate insulating layers (130) located between the plurality of word lines and the plurality of semiconductor patterns (130 between AP and WL);
an insulating liner (154) disposed on an upper side of the sidewall of each of the plurality of semiconductor patterns,
the insulating liner comprising an air space therein (in Fig. 3, 154 has AS); and
a plurality of storage nodes respectively disposed on the plurality of semiconductor patterns (SN on AP),
the plurality of storage nodes (SN) comprising a lower electrode (162), a capacitor dielectric layer (164), and an upper electrode (166),
wherein a sidewall of a bottom portion of the lower electrode is covered by the insulating liner (lower sidewall of 162 is covered by 154).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 13 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Yeong et al. (US 12,324,146) in view of Sun et al. (US 2023/0371241).
PNG
media_image3.png
426
620
media_image3.png
Greyscale
PNG
media_image4.png
342
676
media_image4.png
Greyscale
Regarding claim 1, the prior art of Yeong discloses in Figs. 3C-26A, and presented in Figs. 14 and 26A (provided above), a semiconductor device (memory device as presented below, which is built upon “The substrate 2 may be a semiconductor substrate”, col. 4, line 36) comprising:
a plurality of bit lines (plural 12 are shown, “bitline 12”, col. 3, line 2) each extending in a first direction (the direction in which the bit lines 12 extend, hereinafter referred to as ‘FD’) on a substrate (“substrate 2”, col. 4, line 36) and spaced apart from each other in a second direction perpendicular to the first direction (second direction is interpreted to be the direction crossing the direction the bitlines 12 extend, hereinafter referred to as ‘SD’);
a plurality of semiconductor patterns (channel regions 22, where 22 are formed from “after patterning the semiconductor material layer 20 to form channel regions 22”, col. 6, lines 32-33) respectively disposed on the plurality of bit lines (22 on 12),
the plurality of semiconductor patterns comprising a first semiconductor pattern (one of the plurality of 22) disposed on a first bit line (on a given 12) from among the plurality of bit lines (plural 12 shown), and a second semiconductor pattern (another of one of the plurality of 22) arranged to be on the first bit line (plural 22 noted on same bit line 12);
a plurality of word lines (28, “wordlines (WLs) 28 wiring patterns”, col. 9, lines 5-6) each extending in the second direction (word lines 28 extend in the SD direction that is crossing the bitlines and FD) and surrounding a sidewall of each of the plurality of semiconductor patterns (28 can be surrounding the sidewall of 22 in Fig. 14), the plurality of word lines comprising a first word line extending in the second direction and surrounding the first semiconductor pattern (28 extend in the SD, crossing the FD which is the direction which bit lines 12 extend), and a second word line (another 28 of the plural 28 shown) spaced apart in the first direction (28 are spaced apart along the FD which is the direction which bit lines 12 extend) from the first word line (plural 28 shown spaced apart from each other) and extending in the second direction (28 extend in SD) while surrounding the second semiconductor pattern (28 can be surrounding the sidewall of 22 in Fig. 14); and
a plurality of storage nodes (43, “cell capacitor 43”, col. 10, lines 53-54, where a capacitor is capable of storing a charge) respectively disposed on the plurality of semiconductor patterns (43 on plural 22).
Yeong does not disclose the italicized portion of the following limitation,
“the plurality of semiconductor patterns comprising a first semiconductor pattern disposed on a first bit line from among the plurality of bit lines, and a second semiconductor pattern arranged to be offset in the second direction from the first semiconductor pattern on the first bit line”.
PNG
media_image5.png
482
476
media_image5.png
Greyscale
Sun discloses in Fig. 4A (annotated by Examiner to display the hexagonal arrangement in heavy black line), the plurality of semiconductor patterns (oval shaped features labeled 222, “semiconductor body 222 … of each row of vertical transistors 220”, ¶ 0123) comprising a first semiconductor pattern (one of the 222 disposed on a left most side of a given bit line 260) disposed on a first bit line from among the plurality of bit lines (one of the 260 among plural 260, “bit lines 260”, ¶ 0122), and a second semiconductor pattern arranged to be offset in the second direction from the first semiconductor pattern on the first bit line (another one of the 222 disposed on a right most side of the bit lines 260). The purpose of arranging the semiconductor patterns on the bit lines in this manner is disclosed as being for the purpose of reducing the distance between each memory site so as to increase memory density, see ¶ 0164.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “the plurality of semiconductor patterns comprising a first semiconductor pattern disposed on a first bit line from among the plurality of bit lines, and a second semiconductor pattern arranged to be offset in the second direction from the first semiconductor pattern on the first bit line”, as disclosed by Sun in the system of Yeong, for the purpose of increasing memory density. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Yeong et al. disclose the semiconductor device of claim 1, wherein, in a plan view, the plurality of semiconductor patterns are arranged in a hexagonal array (as shown by the Sun reference in Fig. 4A, an imaginary hexagonal shaped line can be traced along six relatively oriented semiconductor patterns 222).
Regarding claim 13, the prior art of Yeong discloses in Figs. 3C-26A, and presented in Figs. 14 and 26A (provided above), a semiconductor device (memory device as presented below, which is built upon “The substrate 2 may be a semiconductor substrate”, col. 4, line 36) comprising:
a plurality of bit lines (plural 12 are shown, “bitline 12”, col. 3, line 2) each extending in a first direction (the direction in which the bit lines 12 extend, hereinafter referred to as ‘FD’) on a substrate (“substrate 2”, col. 4, line 36) and spaced apart from each other in a second direction perpendicular to the first direction (second direction is interpreted to be the direction crossing the direction the bitlines 12 extend, hereinafter referred to as ‘SD’);
a plurality of semiconductor patterns (plurality channel regions 22, where 22 are formed from “after patterning the semiconductor material layer 20 to form channel regions 22”, col. 6, lines 32-33) disposed on each of the plurality of bit lines (22 on bitlines 12), the plurality of semiconductor patterns comprising:
a plurality of word lines (28, “wordlines (WLs) 28 wiring patterns”, col. 9, lines 5-6) each extending in the second direction (WL extend in SD) and surrounding a sidewall of each of the plurality of semiconductor patterns (WL/28 surround 22 as can be seen in Fig. 14); and
a plurality of storage nodes (43, “cell capacitor 43”, col. 10, lines 53-54, where a capacitor is capable of storing a charge) respectively disposed on the plurality of semiconductor patterns (43 on 22).
Yeong does not disclose,
“a plurality of semiconductor patterns … arranged in a hexagonal array, the plurality of semiconductor patterns comprising:
a plurality of first semiconductor patterns disposed on a first bit line from among the plurality of bit lines and located at a first distance from a first sidewall of the first bit line, and a plurality of second semiconductor patterns located at a second distance that is greater than the first distance from the first sidewall on the first bit line”.
PNG
media_image5.png
482
476
media_image5.png
Greyscale
Sun discloses in Fig. 4A, a plurality of semiconductor patterns (oval shaped features labeled 222, “semiconductor body 222 … of each row of vertical transistors 220”, ¶ 0123) … arranged in a hexagonal array (see Examiner annotated Fig. 4A, where hexagonal arrangement can be seen highlighted by the heavy black lines), the plurality of semiconductor patterns comprising:
a plurality of first semiconductor patterns (plural 222) disposed on a first bit line (one of the 260 among plural 260, “bit lines 260”, ¶ 0122) from among the plurality of bit lines (plural 260 shown) and located at a first distance from a first sidewall of the first bit line (center point of some of the 222 are at a given distance from a left most edge of 260), and a plurality of second semiconductor patterns located at a second distance that is greater than the first distance from the first sidewall on the first bit line (center point of some of the 222 are at a greater distance to the right of the same bit line 260’s left most edge). The purpose of arranging the semiconductor patterns on the bit lines in this manner is disclosed as being for the purpose of reducing the distance between each memory site so as to increase memory density, see ¶ 0164.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“a plurality of semiconductor patterns … arranged in a hexagonal array, the plurality of semiconductor patterns comprising:
a plurality of first semiconductor patterns disposed on a first bit line from among the plurality of bit lines and located at a first distance from a first sidewall of the first bit line, and a plurality of second semiconductor patterns located at a second distance that is greater than the first distance from the first sidewall on the first bit line”, as disclosed by Sun in the system of Yeong, for the purpose of increasing memory density. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 15, the prior art of Yeong et al. disclose the semiconductor device of claim 13, and Yeong discloses, wherein the plurality of semiconductor patterns (plurality channel regions 22, where 22 are formed from “after patterning the semiconductor material layer 20 to form channel regions 22”, col. 6, lines 32-33) comprise at least one of silicon, silicon-germanium, silicon carbide, gallium arsenide, indium phosphide, indium oxide, indium gallium oxide, indium zinc gallium oxide, and aluminum indium gallium oxide (“The semiconductor material layer 20 may be any suitable material, including any of those materials listed above for the substrate 2, or, for example, a semiconductor oxide, such as indium oxide (InO), zinc oxide (ZnO), gallium oxide (GaO), indium zinc oxide (IZO), indium tungsten oxide (IWO), indium tin oxide (ITO), indium zinc gallium oxide (IZGO), the like, or combinations thereof. In other embodiments, the semiconductor material layer 20 may include polysilicon in an amorphous or crystalline form.”, col. 6, lines 16-24).
Claims 5 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yeong et al. (US 12,324,146) in view of Sun et al. (US 2023/0371241) in view of Okajima et al. (US 2022/0285350).
Regarding claim 5, the prior art of Yeong et al. disclose the semiconductor device of claim 1, however Yeong does not disclose,
“wherein each of the plurality of word lines comprises a main gate portion surrounding the semiconductor pattern, and a connection gate portion disposed between two main gate portions adjacent to each other in the second direction, the connection gate potion being connected to the two main gate portions.”
PNG
media_image6.png
402
374
media_image6.png
Greyscale
PNG
media_image7.png
554
402
media_image7.png
Greyscale
Okajima discloses in Figs. 2 and 3, wherein each of the plurality of word lines (“word lines WL”, ¶ 0090) comprises a main gate portion (12, “The gate electrodes 12 … function as the word line WL”, ¶ 0179) surrounding the semiconductor pattern (“semiconductor layer 10”, ¶ 0177), and a connection gate portion (“the gate interconnects 19 function as the word line WL”, ¶ 0179) disposed between two main gate portions adjacent to each other in the second direction (plural semiconductor memory sites shown in Fig. 2, which represents a plurality of the unit cells in Fig. 3, so the connection line from gate to neighboring gate are the 19 interconnections), the connection gate potion being connected to the two main gate portions (where ever gate 12 has a neighboring gate 12, connected by a gate interconnect 19).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of “wherein each of the plurality of word lines comprises a main gate portion surrounding the semiconductor pattern, and a connection gate portion disposed between two main gate portions adjacent to each other in the second direction, the connection gate potion being connected to the two main gate portions”, as disclosed by Okajima in the system of Yeong et al., for the purpose of creating an electrically connected matrix of control gates which can be addressed across an array of memory sites to be able to function as a memory array. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 6, the prior art of Yeong et al. disclose the semiconductor device of claim 5, wherein, in a plan view, the main gate portion of the first word line is arranged to be offset in the first direction and the second direction from the main gate portion of the second word line (the “main gate” aspect has been disclosed in the rejection of claim 5 under the Okajima reference, and the “offset” arrangement of semiconductor patterns have already been disclosed in the rejection of claim 1, and the gates are contained in the references used in the rejection of claim 1, and now the gate of Okajima disclosed in the rejection of claim 5, which surrounds the semiconductor pattern, will then be utilized for their shape and further in the context of the claim 1 rejection).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yeong et al. (US 12,324,146) in view of Sun et al. (US 2023/0371241) in view of Okajima et al. (US 2022/0285350) in view of Calabrese et al. (US 11,373,914) in view of Lung et al. (US 8,310,864).
Regarding claim 8, the prior art of Yeong et al. disclose the semiconductor device of claim 5, however Yeong does not disclose,
“further comprising a plurality of gate insulating layer between the plurality of word lines and the plurality of semiconductor patterns, wherein each of the plurality of gate insulating layer structures comprises:
a first dielectric layer surrounding a sidewall of each of the plurality of semiconductor patterns and having an upper surface at a higher level than an upper surface of each of the plurality of semiconductor patterns; and
a second dielectric layer surrounding the sidewall of each of the plurality of semiconductor patterns on the first dielectric layer, and having an upper surface at a lower level than the upper surface of each of the plurality of semiconductor patterns.”
PNG
media_image8.png
472
632
media_image8.png
Greyscale
Calabrese discloses in Fig. 18,
further comprising a plurality of gate insulating layer (at least 33 and 45, details below) between the plurality of word lines and the plurality of semiconductor patterns (plural pillars of 30, 15, 32, col. 3, lines 31-41, and col. 4, lines 64-67, discusses their semiconductor materials being silicon. Hereinafter referred to as SP), wherein each of the plurality of gate insulating layer structures comprises:
a first dielectric layer (the “first dielectric layer” would be Calabrese’s 45, “Second gate insulator material 45 may be formed by any suitable manner, for example by oxidizing material of vertical projections/pillars 29 (e.g., by growing an oxide therefrom)”, col. 4, lines 42-45. Then as stated above, the pillar is silicon, so oxidized silicon is silicon dioxide) surrounding a sidewall of each of the plurality of semiconductor patterns (45 surrounding SP) and having an upper surface at a higher level than an upper surface of each of the plurality of semiconductor patterns (45 having upper surface higher than top surface of 32 of SP); and
a second dielectric layer (The “second dielectric layer” would be Calabrese’s 33. Where 33 is described as “first insulating material” and in col. 7, lines 39-44, also is relatively higher k dielectric) surrounding the sidewall of each of the plurality of semiconductor patterns (33 on side surfaces and surrounding SP) on the first dielectric layer (“on the first dielectric layer”… since 33 is ‘on’ a lower surface of 45), and having an upper surface at a lower level than the upper surface of each of the plurality of semiconductor patterns (top of 33 is lower than the top surface of SP’s 32).
Calabrese does not specify wherein 33 which has been interpreted to be the “second dielectric layer”, is explicitly a dielectric material.
Lung discloses that a comparable gate insulating element is a high-k dielectric material (Fig. 9A’s 535, see col. 10, lines 33-37, “The gate dielectric material could comprise silicon dioxide, silicon nitride, zirconium oxide, hafnium oxide, aluminum oxide or other dielectrics such as high-K dielectrics suitable for use with small dimension, vertical FET transistors.”).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“further comprising a plurality of gate insulating layer between the plurality of word lines and the plurality of semiconductor patterns, wherein each of the plurality of gate insulating layer structures comprises:
a first dielectric layer surrounding a sidewall of each of the plurality of semiconductor patterns and having an upper surface at a higher level than an upper surface of each of the plurality of semiconductor patterns; and
a second dielectric layer surrounding the sidewall of each of the plurality of semiconductor patterns on the first dielectric layer, and having an upper surface at a lower level than the upper surface of each of the plurality of semiconductor patterns.”, as disclosed by Calabrese/Lung in the system of Yeong et al., for the purpose of providing a high performance insulating material which allows the word line /gate to impart an electrical field upon the channel so as to allow current flow to allow electrical access to the capacitor memory site. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 9, the prior art of Yeong et al. disclose the semiconductor device of claim 8, and the Calabrese reference discloses,
wherein the first dielectric layer comprises a silicon oxide (45, “Second gate insulator material 45 may be formed by any suitable manner, for example by oxidizing material of vertical projections/pillars 29 (e.g., by growing an oxide therefrom)”, col. 4, lines 42-45. Then as stated above, the pillar is silicon, so oxidized silicon is silicon dioxide. The plural pillars of 30, 15, 32, col. 3, lines 31-41, and col. 4, lines 64-67, discusses their semiconductor materials being silicon.), and the second dielectric layer (33) comprises a high-k dielectric material having a greater dielectric constant than the silicon oxide (Calabrese states that 33 is relatively higher k material, col. 7, lines 39-44, and then in the combination rejection of claim 8, the Lung reference is utilized to specify that gate insulators are both dielectrics and can be high-k materials, see col. 10, lines 33-37, “The gate dielectric material could comprise silicon dioxide, silicon nitride, zirconium oxide, hafnium oxide, aluminum oxide or other dielectrics such as high-K dielectrics suitable for use with small dimension, vertical FET transistors.”).
Allowable Subject Matter
Claims 3, 4, 7, 10-12, 14, 16, 17 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
“3. The semiconductor device of claim 1, wherein the plurality of word lines have a pitch of 2F in the second direction, each of the plurality of bit lines has a first width of 1.74F in the first direction, and the plurality of bit lines are spaced apart from each other at a first interval of 0.58F in the first direction.”
While the prior art of Fujimoto (US 9,177,947), col. 4, line 66 to col. 5, line 6, discloses, “In order to implement the above layout, when F denotes a minimum processing size, B, W and C may be set as follows.
Line pitch B of bit line 2=2 F
Line pitch W of word line 1=2.3 F (more precisely, (4/√3)×F)
Distance C=0.58 F (more precisely, (1/√3)×F)”, and the prior art of Hamamoto (US 2011/0062504) ¶ 0060, “Accordingly, although the size of a cell is approximately the same as that in the conventional example, the effective area of a capacitor can be expanded. In the second embodiment, the effective area of a capacitor is 1.16 F.times.1.5 F=1.74 F.sup.2.”, it is clear that the totality of the prior art of record fails to disclose the feature sizes, together as a coherent grouping of size dimensions for one memory cell. This rationale applies to claims 3, 4 and 14.
“4. The semiconductor device of claim 3, wherein the plurality of semiconductor patterns have a unit cell area of 4.64F2.”
Regarding claim 7, the prior art of Yeong et al. disclose the semiconductor device of claim 5, and Okajima discloses in Fig. 3, wherein an upper surface of the main gate portion (12) and an upper surface of the connection gate portion (19) are coplanar with each other (see Okajima’s Fig. 3, where both 12 and 19 have upper surfaces that are coplanar). However, Yeong et al. do not disclose, “an upper surface of each of the plurality of semiconductor patterns is disposed at a lower vertical level than the upper surface of the main gate portion.”
“10. The semiconductor device of claim 8, further comprising an insulating liner disposed on an upper side of the sidewall of each of the plurality of semiconductor patterns, the insulating liner comprising an air space therein, wherein the air space is arranged between the main gate portion and the first dielectric layer.”
Claims 11-12 are objected to, due to their dependence upon claim 10.
“14. The semiconductor device of claim 13, wherein the plurality of word lines have a pitch of 2F in the second direction, each of the plurality of bit lines has a first width of 1.74F in the first direction, the plurality of bit lines are spaced apart from each other at a first interval of 0.58F in the first direction, and the plurality of semiconductor patterns have a unit cell area of 4.64F2.”
“16. The semiconductor device of claim 13, further comprising:
a plurality of gate insulating layer structures located between the plurality of word lines and the plurality of semiconductor patterns; and
an insulating liner disposed on an upper side of the sidewall of each of the plurality of semiconductor patterns, the insulating liner comprising an air space therein,
wherein each of the plurality of word lines comprises a main gate portion surrounding the semiconductor pattern, and a connection gate portion disposed between two main gate portions adjacent to each other in the second direction, the connection gate portion being connected to the two main gate portions, and each of the plurality of gate insulating layer structures comprises:
a first dielectric layer surrounding the sidewall of each of the plurality of semiconductor patterns and having an upper surface at a higher level than an upper surface of each of the plurality of semiconductor patterns; and
a second dielectric layer surrounding the sidewall of each of the plurality of semiconductor patterns on the first dielectric layer, and having an upper surface at a lower level than the upper surface of each of the plurality of semiconductor patterns.”
“17. The semiconductor device of claim 16, wherein an upper surface of the main gate portion and an upper surface of the connection gate portion are coplanar with each other, and the upper surface of each of the plurality of semiconductor patterns is disposed at a lower vertical level than the upper surface of the main gate portion.”
“18. The semiconductor device of claim 16, wherein each of the plurality of storage nodes comprises:
a lower electrode directly disposed on upper surfaces of the plurality of semiconductor patterns and extending in a third direction perpendicular to an upper surface of the substrate;
an upper electrode surrounding the lower electrode; and
a capacitor dielectric layer located between the lower electrode and the upper electrode, a bottom surface of the lower electrode is disposed at a lower level than an upper surface of the main gate portion, and a sidewall of a bottom portion of the lower electrode is covered by the insulating liner.”
Claims 19 and 20 are allowed. A rejection under 35 U.S.C. 103 as being unpatentable over Yeong et al. (US 12,324,146) in view of Sun et al. (US 2023/0371241) in view of Calabrese et al. (US 11,373,914) was attempted, however as can be seen at the end of the rejection below, several limitations of the claim, were not found to be disclosed or suggested by the prior art of record.
Regarding claim 19, the prior art of Yeong discloses in Figs. 3C-26A, and presented in Figs. 14 and 26A (provided above), a semiconductor device (memory device as presented below, which is built upon “The substrate 2 may be a semiconductor substrate”, col. 4, line 36) comprising:
a plurality of bit lines (plural 12 are shown, “bitline 12”, col. 3, line 2) each extending in a first direction (the direction in which the bit lines 12 extend, hereinafter referred to as ‘FD’) on a substrate (“substrate 2”, col. 4, line 36) and spaced apart from each other in a second direction perpendicular to the first direction (second direction is interpreted to be the direction crossing the direction the bitlines 12 extend, hereinafter referred to as ‘SD’);
a plurality of semiconductor patterns (plurality channel regions 22, where 22 are formed from “after patterning the semiconductor material layer 20 to form channel regions 22”, col. 6, lines 32-33) disposed on each of the plurality of bit lines (22 on bitlines 12) and arranged in an array (array of 22 disposed on plurality of bitlines 12, as can be seen in Fig. 14),
a plurality of word lines (28, “wordlines (WLs) 28 wiring patterns”, col. 9, lines 5-6) each extending in the second direction (WL extend in SD) and surrounding a sidewall of each of the plurality of semiconductor patterns (WL/28 surround 22 as can be seen in Fig. 14); and
a plurality of gate insulating layers (plural elements 24, “A gate dielectric 24 surrounds (laterally wraps around) a gate channel for each cell which are embedded in the WLs 28.”, col. 3, lines 50-52) located between the plurality of word lines and the plurality of semiconductor patterns (plural gate dielectric 24 instances are between plural word lines 28 and plural semiconductor patterns 22, see Fig. 26A);
an insulating material (“first inter layer dielectric (ILD) 34”, col. 3, line 52) disposed on an upper side of the sidewall of each of the plurality of semiconductor patterns (portions of 34 on upper sidewalls of 22),
a plurality of storage nodes (43, “cell capacitor 43”, col. 10, lines 53-54, where a capacitor is capable of storing a charge) respectively disposed on the plurality of semiconductor patterns (43 on 22),
the plurality of storage nodes comprising a lower electrode (“bottom electrode 38”, col. 3, line 54), a capacitor dielectric layer (“capacitor dielectric 40”, col. 3, line 54), and an upper electrode (“top electrode 42”, col. 3, lines 54-55),
wherein a sidewall of a bottom portion of the lower electrode (38) is covered by the insulating material (bottom portion of 38 is covered by 34, see Fig. 26A).
First, Yeong does not disclose,
“a plurality of semiconductor patterns disposed on each of the plurality of bit lines and arranged in a hexagonal array, the plurality of semiconductor patterns comprising a plurality of first semiconductor patterns disposed on a first bit line from among the plurality of bit lines and located at a first distance from a first sidewall of the first bit line, and a plurality of second semiconductor patterns located at a second distance that is greater than the first distance from the first sidewall on the first bit line”.
Sun discloses in Fig. 4A, a plurality of semiconductor patterns (oval shaped features labeled 222, “semiconductor body 222 … of each row of vertical transistors 220”, ¶ 0123) … arranged in a hexagonal array (see Examiner annotated Fig. 4A, where hexagonal arrangement can be seen highlighted by the heavy black lines, earlier in the office action), the plurality of semiconductor patterns comprising a plurality of first semiconductor patterns (plural 222) disposed on a first bit line (one of the 260 among plural 260, “bit lines 260”, ¶ 0122) from among the plurality of bit lines (plural 260 shown) and located at a first distance from a first sidewall of the first bit line (center point of some of the 222 are at a given distance from a left most edge of 260), and a plurality of second semiconductor patterns located at a second distance that is greater than the first distance from the first sidewall on the first bit line (center point of some of the 222 are at a greater distance to the right of the same bit line 260’s left most edge). The purpose of arranging the semiconductor patterns on the bit lines in this manner is disclosed as being for the purpose of reducing the distance between each memory site so as to increase memory density, see ¶ 0164.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to use the limitation of,
“a plurality of semiconductor patterns … arranged in a hexagonal array, the plurality of semiconductor patterns comprising a plurality of first semiconductor patterns disposed on a first bit line from among the plurality of bit lines and located at a first distance from a first sidewall of the first bit line, and a plurality of second semiconductor patterns located at a second distance that is greater than the first distance from the first sidewall on the first bit line”, as disclosed by Sun in the system of Yeong, for the purpose of increasing memory density. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Second, Yeong does not disclose,
“a plurality of gate insulating layers located between the plurality of word lines and the plurality of semiconductor patterns;
an insulating liner disposed on an upper side of the sidewall of each of the plurality of semiconductor patterns,
the insulating liner comprising an air space therein; and
wherein a sidewall of a bottom portion of the lower electrode is covered by the insulating liner.”
PNG
media_image8.png
472
632
media_image8.png
Greyscale
Calabrese discloses in Fig. 18,
a plurality of gate insulating layers (45, “second gate insulator material 45”, col. 5, line 55, and 33, “first gate insulator material 33”, col. 5, lines 37-38) located between the plurality of word lines (54, “conductive gate material 54”, col. 5, line 47, where the gate lines are the “word lines”, see “access lines (which may also be referred to as wordlines, gatelines, or gate lines)”, col. 1, lines 32-33) and the plurality of semiconductor patterns (plural pillars of 30, 15, 32, col. 3, lines 31-41, and col. 4, lines 64-67, discusses their semiconductor materials being silicon. Hereinafter referred to as ‘SP’);
an insulating liner (45) disposed on an upper side of the sidewall of each of the plurality of semiconductor patterns (45 on upper sidewall of SP).
Calabrese and the prior art of record fail to disclose the previously disclosed claimed features in combination with the features of,
“the insulating liner comprising an air space therein; and
wherein a sidewall of a bottom portion of the lower electrode is covered by the insulating liner.”
It is unclear how one of ordinary skill in the art would modify the Yeong reference to have the “insulating liner” be located on a bottom portion of the lower electrode of Yeong, when Yeong already has the interlevel dielectric. Further the prior art of record does not situate an air gap at that location between capacitor and access transistor along the liner material.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EDUARDO A RODELA/Primary Examiner, Art Unit 2893