The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 4-11 are rejected under 35 U.S.C. 103 as being unpatentable over Hasegawa et al. (2013/0056714) in view of Chuang (10,068,861) and Lin et al. (2017/0345801).Regarding claim 1, Hasegawa et al. teach in figure 22 and related text an electronic device, comprising:
a substrate 10a;
a driving layer 10 disposed on the substrate, wherein the driving layer comprises a dielectric layer 110 and a thin film transistor 11, wherein the thin film transistor 11 comprises a gate (of transistor 3A, see figure 24) and a conductive layer (drain/source contact), a portion of the dielectric layer is disposed adjacent the conductive layer and the gate,
an inorganic layer 112 disposed on (on at least part of) the driving layer, the organic layer comprising a connecting hole 114A and a through hole portion 114B; and
a diode 14/16/17 disposed on the inorganic layer and overlapped with the through hole portion, the diode being electrically connected to the driving layer by a bonding pad 21P overlapped with the through hole portion,
wherein the diode 14/16/17 (at least part thereof, e.g. electrode 14) is not overlapped with the thin film transistor (not overlap with the left part of the thin film transistor),
an insulating layer 15 disposed on the now organic layer, wherein the insulating layer comprises a plurality of openings, and
another conductive layer 114b/14b disposed between the now organic layer 112 and the insulating layer 15 in a direction perpendicular to a surface of the substrate,
wherein the connecting hole 114A is in contact with the conductive layer (of transistor 11), the through hole portion 114B is in contact with a surface of another portion of the dielectric layer 110 that connects with the portion of the dielectric layer,
wherein a portion of the another conductive layer 114b/14b is disposed in the through hole portion overlapped with the bonding pad 21P, and the plurality of openings exposes a portion of a surface of the another conductive layer.
Hasegawa et al. do not teach using an organic layer, and wherein a portion of the dielectric layer is disposed between the conductive layer and the gate.
Chuang teaches in figure 1F and related text using organic material layer 106 as an alternative to inorganic material.
Lin et al. teach in figure 6 and related text that a portion of the dielectric layer 108 is disposed between the conductive layer 114 and the gate 106.
Lin et al., Chuang and Hasegawa et al. are analogous art because they are directed to semiconductor devices comprising external connections and one of ordinary skill in the art would have had a reasonable expectation of success to modify Hasegawa et al. because they are from the same field of endeavor.It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to use an organic material as an alternative to the inorganic material, as taught by Chuang, and to dispose a portion of the dielectric layer between the conductive layer and the gate, as taught by Lin et al., in Hasegawa et al.’s device, in order to improve the insulation of the device and in order to be able to operate the device in its intended use by forming a dielectric layer between the drain and the gate, as is well known in the art, respectively.
Regarding the claimed limitations of using specific materials (an organic material), it is noted that substitution of materials is not patentable even when the substitution is new and useful. Safetran Systems Corp. v. Federal Sign & Signal Corp. (DC NIII, 1981) 215 USPQ 979.
It is further held that it is within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Note that a change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 4, Hasegawa et al. teach in figure 22 and related text the another conductive layer 14a2/14b/114b comprises a plurality of first recesses and the diode is overlapped with the plurality of first recesses.
Regarding claim 5, Hasegawa et al. do not teach in figure 22 and related text that a portion of the insulating layer is disposed in one of the plurality of first recesses. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention to dispose a portion of the insulating layer in one of the plurality of first recesses in prior art’s device in order to simplify the processing steps of making the device by not requiring the alignment of the insulating layer with the top of the bonding pad.
Regarding claim 6, Hasegawa et al. teach in figure 22 and related text that the bonding pad 21P is disposed on the another conductive layer, but do not teach that a portion of the bonding pad is disposed in the plurality of first recesses. Chuang teaches in figure 1F and related text that a portion of the bonding pad 116 is disposed in the plurality of first recesses. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to dispose a portion of the bonding pad in the plurality of first recesses, as taught by Chuang, in Hasegawa et al.’s device, in order to improve the structural integrity of the device.
Regarding claim 7, the combined device comprises a top surface of the bonding pad comprises a plurality of second recesses, because Chuang teaches in figure 1F and related text that a top surface of the bonding pad 116 comprises a plurality of second recesses 117.
Regarding claim 8, Hasegawa et al. teach in figure 22 and related text that the connecting hole is not overlapped with the diode, and another portion of the conductive layer 114B is disposed in the connecting hole.
Regarding claim 9, Hasegawa et al. teach in figure 22 and related text a portion of the thin film transistor is exposed by a connecting hole 114A, and the another conductive layer is electrically connected (inherently therein) to the thin film transistor through the connecting hole. Hasegawa et al. do not teach that a portion of a drain of the thin film transistor is exposed by the connecting hole. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to expose a portion of a drain of the thin film transistor by the connecting hole in prior art’s device in order to provide external connection to the thin film transistor.
Regarding claim 10, Hasegawa et al. teach in figure 22 and related text that the dielectric layer comprises a top surface perpendicular to a top view direction of the electronic device, and a portion of the top surface of the dielectric layer is exposed by the through hole portion 114B of the organic layer.
Regarding claim 11, Hasegawa et al. teach in figure 22 and related text that the through hole portion 114B comprises a through hole, and that a portion of the top surface of the dielectric layer 15 is exposed by the through hole.
Hasegawa et al. do not explicitly state that a portion of a drain of the thin film transistor is exposed by the connecting hole. Hasegawa et al. teach in figure 22 and related text that a portion of a contact layer of the thin film transistor is exposed by the connecting hole. It would have been obvious to a person of ordinary skill in the art, before the effective filling date of the claimed invention, to form said contact layer of the thin film transistor as a drain electrode in prior art’s device in order to operate the device in its intended use.
Response to Arguments
1. Applicants argue that “the low reflection conductive film 14b is considered as the another conductive layer 124 and the bonding pad 1280/1282 of the claimed invention at the same time by the Examiner. Since the claimed invention claims two different elements but the cited reference only discloses one element in his application, the Applicant asserts that the same element of the cited reference cannot correspond to two different elements of the claimed invention”.
1. Applicants’ argument is unclear. The another conductive layer is 114b/14b, as recited in the rejection, and not 114b or 14b, as argue by applicants.
Furthermore, since insulating layer 15 overlaps the another conductive layer is 114b/14b, then the another conductive layer 114b/14b disposed between the inorganic layer 112 and the insulating layer 15 in a direction perpendicular to a surface of the substrate.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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O.N. /ORI NADAV/
11/11/2025 PRIMARY EXAMINER
TECHNOLOGY CENTER 2800