377413
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Remarks
Applicant's arguments filed 01/08/2026 have been fully considered but they are not persuasive. See pages 1-3 regarding the 35 U.S.C. 102 Rejection. The Examiner respectfully argues that Kimura (US 20060261472) does meet the limitations of independent claims 1 and 13. As previously disclosed in the Annotated Kimura Fig. 11, the pads (143) of the Kimura device, are on the conductive line and are configured to receive interconnect components. Though there is a solder ball (244) between the conductive line and the pad, the pad is indirectly on the conduction line. It is noted in the following statement, though not a part of the non-final rejection, there are also pads, obviously if not inherently, between the connection of the solder and conductive line. Therefore, the rejection of claim 1-7, 13 and 15-20 stands.
However, the Applicant’s arguments on pages 4-5, filed 01/08/2026, with respect to the rejection(s) of claim(s) 12 (now cancelled) and incorporated into the features of independent claim 9, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Kimura (US 20060261472) in view of Yiu et al. (US 20160372445). Kimura does not explicitly teach the limitations of the amended claim 9, as there is no top view of the Kimura device to explicitly show a single section of the conductive line (either the top, bottom, or side) divided into two sections with a specified angle between them.
However, Fig 2 of the Yiu device shows a single section of the conductive line divided into sections with a <180 degree angle between them, which discloses every element of claim 9. Thus, 35 U.S.C. 103 rejection is unpatentable under Kimura in view of Yiu. It is obvious to connect chips with different footprints using a section of a conductive line comprising a first segment and a second segment intersection point at an angle different from 180 degrees, such that chips of different sizes connect; thereby redirecting signals from respective irregular footprints.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, and 3- 7 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Kimura et al. herein referred to as Kimura (US 20060261472) Fig. 11
As to claim 1, Kimura teaches a microelectronic device structure (¶ 0094, multilayer module 141, Kimura) comprising: a device (¶ 0094, 1st module 32c) having
(i) a lower surface (Annotated module 32c lower surface, Fig. 11, Kimura),
(ii) an upper surface opposite the lower surface (Annotated module 32c upper surface, Fig. 11, Kimura), and
(iii) a side surface extending between the lower surface and the upper surface (Annotated module 32c side surface, Fig. 11, Kimura); and
a conductive line (¶ 0084, conductive terminal 34a/34b, Fig. 11 Kimura) having
(i) a first section on the upper surface (Annotated 1st section module 34a/34b, Fig. 11, Kimura),
(ii) a second section on the side surface (Annotated 2nd section 34a/34b, Fig. 11, Kimura), and
(iii) a third section on the lower surface (Annotated 3rd section 34a/34b, Fig. 11, Kimura); wherein
the first section and the second section of the conductive line is a monolithic conductive structure (Annotated 1st and 2nd sections 34a/34b are monolithic as shown in Fig. 11, Kimura), and/or
the second section and the third section of the conductive line is a monolithic conductive structure (Annotated 2nd and 3rd sections 34a/34b are monolithic as shown in Fig. 11, Kimura).
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As to claim 3, Kimura teaches the microelectronic device structure of claim 1, further comprising
the first interconnect component (¶ 0085, Annotated 1st cream solder 111, Kimura) and the second interconnect component (¶ 0085, Annotated 2nd cream solder 144, Kimura), wherein
the first interconnect component is a solder ball or a solder bump (Annotated (1st solder ball 111) as shown in Fig. 11, Kimura), and
the second interconnect component is a solder ball or a solder bump (Annotated (2nd solder ball 144) as shown in Fig. 11, Kimura).
As to claim 4, Kimura teaches the microelectronic device structure of claim 1, wherein
the device is a first device (¶ 0094, 1st module 32c), and wherein the integrated circuit structure (¶ 0094, IC circuit structure, Kimura) further comprises:
a second device (¶ 0094, 2nd module 33c), above the first device (¶ 0094, 1st module 32c); and
an interconnect component (Annotated 1st solder ball 111, Fig. 11) configured to couple the second device (¶ 0094, 2nd module 33c), to the first section of the conductive line (Annotated 1st section 34a/34b, Fig. 11, Kimura).
As to claim 5, Kimura teaches the microelectronic device structure of claim 4, wherein
the interconnect component is a first interconnect component (Annotated 1st (111), Fig. 11), and wherein
the integrated circuit structure (¶ 0094, IC circuit structure, Kimura) further comprises:
a third device (¶ 0094, mother board 142) below the first device (¶ 0094, 1st module 32c); and
a second interconnect component (Annotated (2nd solder ball 144), Fig. 11) configured to couple the third section of the conductive line (Annotated 3rd section 34a/34b, Fig. 11, Kimura) to the third device (¶ 0094, mother board 142).
As to claim 6, Kimura teaches the microelectronic device structure of claim 1, wherein
the first, second, and third sections of the conductive line are part of a monolithic conductive structure, with no seam or interface between the first, second and third sections (Annotated 1st , 2nd and 3rd sections 34a/34b are monolithic as shown in Fig. 11, Kimura).
As to claim 7, Kimura teaches the microelectronic device structure of claim 1, wherein
at least one of the first, second, or third sections of the conductive line (Annotated 1st , 2nd and 3rd sections of 34a/34b, Fig. 11, Kimura) comprises:
a first segment and a second segment, such that the first segment and the second segment intersect at an intersection point at angle different from 180 degrees (Annotated 1st and 2nd segments of 34a/34b, form a 90o angle as shown in Fig. 11, Kimura).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Kimura et al. herein referred to as Kimura (US 20060261472) Fig. 11
As to claim 8, Kimura teaches the microelectronic device structure of claim 7, wherein
a first thickness (obvious) of the conductive line (Annotated 1st thickness of conductive line, Kimura) at the intersection point and
a second thickness (obvious) of the conductive line (Annotated 2nd thickness of conductive line, Kimura) at a non- intersection point of the first section are within 5% of each other (Annotated 1st and 2nd segment thicknesses are within 5% of each other, Fig. 11 shows thickness being substantially equal, Kimura).
(Regarding claim 8, Kimura teaches all the limitations of claim 8, but does not explicitly teach that: the thickness difference between the first thickness of the conductive line at the intersection point, and a second thickness of the conductive line at a non- intersection point of the first section, is within 5 %. However, Fig. 11 shows an obvious if not inherent thicknesses between the first and second thickness being substantially equal, so as to allow for predictability of current flow. Furthermore, the Applicant has not shown that a 5% thickness difference is somehow unique, novel or cutting edge in the fabrication method and use of the disclosed device. Therefore, the Applicant has not shown that the limitation 5% is a critical (range/limit/requirement) and that it would not have been found through routine experimentation.)
Claim(s) 9-11, is/are rejected under 35 U.S.C. 103 as being unpatentable over by Kimura et al. herein referred to as Kimura (US 20060261472) Fig. 11 in view of Yiu et al. (US 20160372445) herein referred to as Yiu Fig. 2 and 1G.
As to claim 9, Kimura teaches a system comprising:
a first device (¶ 0094, 1st module 32c) having
(i) a lower surface (Annotated module 32c lower surface, Fig. 11, Kimura), (ii) an upper surface opposite the lower surface (Annotated module 32c upper surface, Fig. 11, Kimura), and (iii) a side surface extending between the lower surface and the upper surface (Annotated module 32c side surface, Fig. 11, Kimura);
a second device (¶ 0094, 2nd module 33c) above the first device (¶ 0094, 1st module 32c); a third device (¶ 0094, mother board 142) below the first device (¶ 0094, 1st module 32c);
a continuous conductive line (¶ 0084, conductive terminal 34a/34b, Fig. 11 Kimura) extending on the upper surface, the side surface, and the lower surface (Annotated 1st , 2nd and 3rd sections of 34a/34b, Fig. 11, Kimura) of the first device (¶ 0094, 1st module 32c), wherein
a portion of the conductive line (34a/34b, Fig. 11 Kimura) extending on at least two adjacent surfaces of the first die is monolithic (34a/34b is a one piece continuous component as shown in Fig. 11);
a first interconnect component (Annotated (1st solder ball 111), Fig. 11) coupled between
(i) the second device (¶ 0094, 2nd module 33c), and (ii) a section of the conductive line that on the upper surface of the first device (Annotated 1st section 34a/34b, Fig. 11, Kimura); and a second interconnect component (Annotated (2nd solder ball 144), Fig. 11) coupled between (i) the third device (¶ 0094, mother board 142), and (ii) a section of the conductive line that on the lower surface of the first device (Annotated 3rd section 34b, Fig. 11, Kimura).
a section of the conductive line, which extends on one of the lower, side, or upper surfaces of the first die (Annotated 1st , 2nd and 3rd section 34a/34b, Fig. 11, Kimura), comprises
a first segment and a second segment, such that the first segment and the second segment intersect at an intersection point at angle different from 180 degrees (Annotated 1st and 2nd segment 34a/34b form a 90o angle as shown in Fig. 11, Kimura), and
a first thickness (obvious) of the conductive line at the intersection point and a second thickness (obvious) of the conductive line at a non-intersection point of the section is within 5% of each other (Annotated 1st and 2nd segment thicknesses are within 5% of each other, Fig. 11 shows thickness being substantially equal, Kimura).
a first thickness (obvious) of the conductive line at the intersection point and a second thickness (obvious) of the conductive line at a non-intersection point of the section is within 5% of each other. (Annotated 1st and 2nd segment thicknesses are within 5% of each other, Fig. 11 shows thickness being substantially equal, Kimura).
Kimura does not appear to expressly disclose “wherein: a section of the conductive line, which extends on one of the lower, side, or upper surfaces of the first die, comprises a first segment and a second segment, such that the first segment and the second segment intersect at an intersection point at angle different from 180 degrees”;
Yiu teaches
a section of the conductive line, which extends on one of the lower, side, or upper surfaces of the first die, (Annotated 1st , 2nd Fig. 2, Yiu)comprises
a first segment and a second segment, such that the first segment and the second segment intersect at an intersection point at angle different from 180 degrees” (Annotated 1st and 2nd segment form a 90o angle as shown in Fig. 2, Yiu)
(Regarding claim 9, Kimura teaches all the limitations of claim 8, but does not explicitly teach that the thickness difference between the first thickness of the conductive line at the intersection point, and a second thickness of the conductive line at a non- intersection point of the first section is within 5 %. However, Fig. 11 shows an obvious if not inherent thicknesses between the first and second thickness being substantially equal, so as to allow for predictability of current flow. Furthermore, the Applicant has not shown that a 5% difference is somehow unique, novel or cutting edge in the fabrication method and use of the disclosed device. Therefore, the Applicant has not shown that the limitation 5% is a critical (range/limit/requirement) and that it would not have been found through routine experimentation.
Also, Kimura, lacking a top view, does not explicitly show the amended limitations of claim 9 regarding the section of the conductive line, which extends on one of the lower, side, or upper surfaces of the first die. The Annotated Fig. 2 of Yiu shows a first segment and a second segment, such that the first segment and the second segment intersect at an intersection point at angle different from 180 degrees”. Regardless of the footprint of the die, conductive pathways include conductive lines that connect any of the conductive contacts in the die in a suitable manner. Thus, arranging to route electrical signals to meet the footprint of the die, is well known in semiconductor manufacturing. Therefore It would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to make the conductive line segments of the Kimura device such that the intersection point is at angles different than 180 degrees, as in disclosed in the Yiu device, so as to use an industrially tested and accepted device/process.)
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As to claim 10, Kimura as combined with Yiu teaches the system of claim 9, wherein:
the first device (¶ 0094, 1st module 32c, Kimura) is first integrated circuit die or a first integrated circuit package (¶ 0094, 1st module 32c is considered a package, Kimura);
the second device (¶ 0094, 2nd module 33c Kimura) is a second integrated circuit die or a second integrated circuit package (¶ 0094, 2nd module 33c is considered a package, Kimura); and
the third device (¶ 0094, mother board 142, Kimura) is a third integrated circuit die, a third integrated circuit package, or a circuit board (¶ 0094, mother board 142 is a circuit board, Kimura).
As to claim 11, Kimura as combined with Yiu the system of claim 9, wherein
the first interconnect component is a solder ball or a solder bump (Annotated (1st solder ball 111) as shown in Fig. 11, Kimura), and the second interconnect component is a solder ball or a solder bump (Annotated (2nd solder ball 144) as shown in Fig. 11, Kimura).
Claim(s) 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Kimura et al. herein referred to as Kimura (US 20060261472) in view of Lin et al. herein referred to as Lin (US 20240145453) Fig. 11 (Kimura), Lin ( Fig. 1A)
As to claim 13. Kimura teaches a method comprising:
depositing first conductive (obvious) material on a first surface of an integrated circuit device (¶ 0032 “modules 32, 33 are formed at the top and bottom surfaces with those layers containing a base material , ([0038] Conductor patterns 34 and 35 are formed on the surface of resin/base-material composites 43 and 44, respectively as shown in Fig. 1/11, Kimura);)
patterning the first conductive material on the first surface, to form a first section of a conductive line ([0038] Conductor patterns 34 and 35 are formed on the surface of resin/base-material composites 43 and 44, respectively as shown in Fig. 1/11, Kimura);
depositing second conductive material on a second surface and a third surface of the integrated circuit device, one of the second or third surfaces is substantially perpendicular to the first surface ([0038] Conductor patterns 34 and 35 are formed on the surface of resin/base-material composites 43 (device 1) and 44 (device 2), respectively as shown in Fig. 11, Kimura); and
patterning the second conductive material on the second and third surfaces, to form a second section and a third section of the conductive line on the second surface and the third surface, respectively, of the integrated circuit device, such that the conductive line is a continuous structure that extends on the first surface, the second surface, and the third surface of the integrated circuit device ([0038] Conductor patterns 34 and 35 are formed on the surface of resin/base-material composites 43 and 44, respectively as shown in Fig. 1/11, Kimura);.
coupling a first interconnect component (111) on the first section of the conductive line that is on the first surface ([0084] connection terminals 34a, 34b of module 32 are connected by means of cream solder 111, Kimura) and
coupling a second interconnect component (144) on the third section of the conductive line that is on the third surface that is opposite to the first surface. ([0094] Multilayer module 141 is connected on mother substrate's conductor pattern 143 using also cream solder 144., Kimura)
(Regarding claim 13, Kimura teaches the limitations of claim 13 but does not explicitly teach that a conductive material is deposited on a first surface of an integrated circuit device. Modules 32 and 32 are package devices enclosing and insulating the semiconductor die and its delicate internal wiring. However, certain materials and internal components within the package are designed to be highly conductive in order to optimize the device reliability/design and connectivity requirements owing to the properties of the material. Furthermore, conductor patterns (such as component 34) are inherently conductive. Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to deposit conductive material on a first surface of an integrated circuit device so as to use an industrially tested and accepted device/process/material.
Kimura also does not explicitly teach the method of depositing and patterning the first and second conductive materials. However, Lin does teach the method of depositing and patterning the first and second conductive materials. See [0030, Lin] “sputtering and etching” are a depositing and patterning process. Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to use the method of Lin to deposit and pattern the first and second conductive materials on the first, second and third sections of the conductive line of Kimura, so as to use an industrially tested and accepted device/process/material.)
As to claim 15, Kimura as combined with Lin teaches the method of claim 13, wherein
the integrated circuit device is a first integrated circuit device (32c) , and wherein the method further comprises: coupling a second integrated circuit device (33c) to the first interconnect component (32c), and coupling a third integrated circuit device (142) to the second interconnect component (33c) ([0094] In FIG. 11, cream solder 111 is used as the connection member between module 32c and module 33c. Multilayer module 141 is connected on mother substrate's conductor pattern 143 using also cream solder 144.)
As to claim 16, Kimura as combined with Lin teaches the method of claim 13, wherein
the first interconnect component is a solder ball or a solder bump (¶ 0094, solder ball 111 id shown in Fig. 11) , and
the second interconnect component is a solder ball or a solder bump (¶ 0094, solder ball 144 is shown in Fig. 11).
As to claim 17, Kimura as combined with Lin teaches the method of claim 13, wherein
the first conductive material and the second conductive material are deposited using a same deposition process (¶ 0032 “modules 32, 33 are formed at the top and bottom surfaces with those layers containing a base material ([0038] Conductor patterns 34 and 35 are formed on the surface of resin/base-material composites 43 and 44, respectively as shown in Fig. 1/11 and ¶ 0030 Lin );
(Regarding claim 17, Kimura does not explicitly teach the method of depositing the first and second conductive materials using the same deposition process. However, Lin does teach the method of depositing the first and second conductive materials using the same deposition process. ¶ 0030 discloses, “ In this embodiment, since the first bonding portion 210, the first extension portion 220, the second extension portion 230, and the second bonding portion 240 are formed by applying the same method and are made of the same material,…”
Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to use the method of Lin, which deposits the first and second conductive materials using the same deposition process, on the Kimura device so as to use an industrially tested and accepted device/process/material.)
As to claim 18, Kimura as combined with Lin teaches the method of claim 13, wherein
the first conductive material and the second conductive material are patterned using a same patterning process. (¶ 0032 “modules 32, 33 are formed at the top and bottom surfaces with those layers containing a base material ([0038] Conductor patterns 34 and 35 are formed on the surface of resin/base-material composites 43 and 44, respectively as shown in Fig. 1/11 and ¶ 0030 Lin);
(Regarding claim 18, Kimura does not explicitly teach the method of patterning the first and second conductive materials. However, Lin does teach the method of patterning the first and second conductive materials. ¶ 0030 discloses “In this embodiment, since the first bonding portion 210, the first extension portion 220, the second extension portion 230, and the second bonding portion 240 are formed by applying the same method and are made of the same material,…”Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to use the method of Lin to pattern the first and second conductive materials of the Kimura device, so as to use an industrially tested and accepted device/process/material.)
As to claim 19, Kimura as combined with Lin teaches the method of claim 13, wherein
the second conductive material is deposited subsequent to patterning the first conductive material. (¶ 0027, sequentially connected, Lin)
(Regarding claim 19, Kimura does not explicitly teach the method in which the second conductive material is deposited subsequent to patterning the first conductive material. However, Lin does teach the method in which the second conductive material is deposited subsequent to patterning the first conductive material. ¶ 0027 discloses “ The side wire 200 includes a first bonding portion 210, a first extension portion 220, a second extension portion 230, and a second bonding portion 240, where the first bonding portion 210, the first extension portion 220, the second extension portion 230, and the second bonding portion 240 are sequentially connected.” Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to use the method of Lin to deposit and pattern the first and second conductive materials on the first, second and third sections of the conductive line of Kimura, so as to use an industrially tested and accepted device/process/material.)
As to claim 20, Kimura as combined with Lin teaches the method of claim 13, wherein
patterning the first conductive material and the second conductive material comprises: patterning the first conductive material and the second conductive material using corresponding laser beams ([0038] Conductor patterns 34 and 35 are formed on the surface of resin/base-material composites 43 and 44, respectively, ¶ 0030 laser engraving, Lin).
(Regarding claim 20, Kimura does not explicitly teach the method of patterning the first and second conductive materials using corresponding laser beams. However, Lin does teach the method of patterning the first and second conductive materials using corresponding laser beams. ¶ 0030 discloses “ the method of forming the first bonding portion 210, the first extension portion 220, the second extension portion 230, and the second bonding portion 240 includes sputtering, printing, etching, laser engraving, or other appropriate processes,..” Therefore, it would have been obvious to one who is skilled in the art, before the effective filing date of the claimed invention, to use the method of Lin to pattern the first and second conductive materials using corresponding laser beams, in the device of Kimura, so as to use an industrially tested and accepted device/process/material.)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN SHAW MUSLIM whose telephone number is (571)270-0071. The examiner can normally be reached Mon-Fri 7 am - 4 pm.
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/SHAWN SHAW MUSLIM/Examiner, Art Unit 2897
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897