DETAILED ACTION
This Office action responds to the Amendment file on December 19, 2025, responding to the Office action mailed on September 19, 2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Applicant cancelled claim 14. Accordingly, pending in the application are claims 1-13 and 15-20.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments to the Specification have only overcome two out of four objections to the specification. There are three occurrences of “the device 104” in ¶ [0034] of the originally filed specification, but only two out of three occurrences of “the device 104” in ¶ [0034] are corrected in the amended specification filed on December 19, 2025.
Response to Argument
Applicant argues that the B5 does not contact B3 of Kimura et al. prior art of record. The combination of B5 and B4 formed of the same material, Cu is in contact with B3 of Kimura et al. prior art of record.
New 103 rejection has been made for Claim 18.
Applicant argues that Takai et al. (JP 2003-282788) does not teach “continuous/monolithic requirements of the claim”. Takai et al. (see ¶ [0029]) teaches “as shown in FIG. 5, a barrier metal resistor R3 made of a barrier metal (barrier metal layer) 35 is formed between bonding pad 1 (31A) and bonding pad 2 (31b) on an IC chip 30” and FIG. 5 clearly depicts the R3 is continuous/monolithic across the IC chip 30 and is common to both resistive structures (right and left sides).
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “an interconnect component above and in contact with the second layer” and “the second layer comprising a resistive material” must be shown or the feature(s) canceled from the Claim 1. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: The number 104 is used for both the resistive contact pad structure and the device in ¶ [0034]. Appropriate correction is required.
The specification is objected to as failing to provide proper antecedent basis for the claimed subject matter. See 37 CFR 1.75(d)(1) and MPEP § 608.01(o). Correction of the following is required: the specification does not teach “an interconnect component above and in contact with the second layer” in Claim 1.
According to the paragraph (¶) [0031] of the specification, “the resistive contact pad structure 104 is configured to receive an interconnect component, such as a conductive ball or a conductive bump (see Figs 3 or 5, not illustrated in Fig. 1), and wherein the interconnect component is to couple the device 108 to another device”. According to ¶ [0040] of the specification, “The layer 128 is configured as a contact pad structure to receive a solder ball or a solder bump (e.g., see Fig. 3) … comprises appropriate metals and/or alloys thereof, which can adhere to a solder ball or a solder bump”. According to ¶ [0052] of the specification, “two interconnect components 304 and 344 respectively on the resistive contact pad structure 104 and the non-resistive contact pad structure 220”. Hence, the specification only teaches the interconnect component 304 or 344 only in contact with top conductive metal layer 128 or the non-resistive contact pad structure 220, not the intermediate resistive layer 124 as recited in Claim 1.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
According to the paragraph (¶) [0031] of the specification, “the resistive contact pad structure 104 is configured to receive an interconnect component, such as a conductive ball or a conductive bump (see Figs 3 or 5, not illustrated in Fig. 1), and wherein the interconnect component is to couple the device 108 to another device”. According to ¶ [0040] of the specification, “The layer 128 is configured as a contact pad structure to receive a solder ball or a solder bump (e.g., see Fig. 3) … comprises appropriate metals and/or alloys thereof, which can adhere to a solder ball or a solder bump”. According to ¶ [0052] of the specification, “two interconnect components 304 and 344 respectively on the resistive contact pad structure 104 and the non-resistive contact pad structure 220”. Hence, the specification only teaches the interconnect component 304 or 344 only in contact with top conductive metal layer 128 or the non-resistive contact pad structure 220, not the intermediate resistive layer 124 as recited in Claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, and 4 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Kimura et al. (Kimura hereinafter) (US 7,061,093).
Examiner assumes the 112 rejection of Claim 1 has been corrected as shown in Figs. 3 and 5.
Regarding Claims 1, 2, and 4:
Kimura (see FIG. 2) teaches {1} an integrated circuit structure comprising: a first layer B2 comprising a first metal (Al); a second layer above and in contact with the first layer, the second layer B3 comprising a resistive material (Cr/Ti); a third layer (B4, B5) above and in contact with the second layer, the third layer comprising a second metal (Cu), wherein the resistive material is different from one or both the first metal and the second metal; and an interconnect component (B6) above and in contact with the second layer; {2} the interconnect component is a solder bump or a solder ball; and {4} the resistive material comprises one or more of (i) a third metal different from the first and second metals, (ii) a metalloid, and (iii) the third metal and at least one of oxygen and nitrogen.
Kimura (see col.1/ll.59-63 and col.7/ll.16-22) teaches “In the conventional wafer level CSP, it is assumed that the aluminum electrode B2 placed on the pad of the IC chip B1 is connected to the copper post B5 and the solder bump (the solder ball) B6 only through the reroute trace B4 having a resistance as low as possible” and “deliberately lengthening or narrowing or both lengthening and narrowing he pattern of the copper reroute trace between the bonding pad 41 and the solder bump 43, or … by changing the material to a barrier metal, such as chromium (Cr) or titanium (Ti) … the resistance Rout can be designed to any desired value”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. (Kimura hereinafter) (US 7,061,093) as applied to claim 1 above, and further in view of Electrical Resistivity of Chemical Elements (https://material-properties.org/electrical-resistivity-of-chemical-elements/).
Regarding Claim 3:
Kimura does not explicitly teach a resistivity of the resistive material is at least 20% greater than a resistivity of each of the first and third layers.
According to the table of Electrical Resistivity of Chemical Elements, the resistivity of Al is 26.5 nΩ·m; that of Cu is 16.8 nΩ·m; that of Cr is 125 nΩ·m; and that of Ti is 420 nΩ·m.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Kimura to further include the teaching of the table of Electrical Resistivity of Chemical Elements to anticipate the resistivities of the resistor made of barrier metal, such as Cr or Ti are more than the electrodes sandwiching the resistor.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. (Kimura hereinafter) (US 7,061,093) as applied to claim 1 above, and further in view of Kawazoe et al. (Kawazoe hereinafter) (US 2005/0153504).
Regarding Claim 5:
Kimura does not explicitly teach the first and second metals are the same metal.
Kawazoe (see ¶ [0034] and [0035] and FIG. 1) teaches “the lower electrode, single noble metals including … Pt, Pd, Rh, and Ir …”, “the upper electrode … is not limited to the above noble metal elements but rather a variety of materials such as Al, Cu, Ni, Ti and Ta, as well as oxide conductors are applicable”, and a variable resistor made of perovskite-type metal oxide film.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Kimura to further include the teaching of Kawazoe to use the same material or different material of the electrodes sandwiching a resistive element in order to form desired resistor configuration.
Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. (Kimura hereinafter) (US 7,061,093) as applied to claim 1 above, and further in view of Ruby et al. (Ruby hereinafter) (US 4,782,381).
Regarding Claims 6 and 7:
Kimura does not explicitly teach {6} the first layer is in contact with or a part of an integrated circuit die, wherein the interconnect component is between the integrated circuit die and a carrier substrate, and wherein the interconnect component is a solder bump; and {7} the first layer is in contact with or a part of a carrier substrate, wherein the interconnect component is between the carrier substrate and an integrated circuit die, and wherein the interconnect component is a solder bump.
Ruby (see col.1/l.57-col.2/l.18 and FIG. 1) teaches either mounting the chips on a printed circuit board or on a chip carrier, “circuit component structure 16a includes a resistor and a diode”, solders 26 bonding the chip carrier 10 with circuit chip 12 through bonding pads 24 and 28, “individual circuit components either in a chip or next to it, they may be placed instead at or near the substrate of a chip carrier”, and “for very high speed computer applications, for example, electrical signal lines that exist between logic chips should be terminated in resistors … form part of a larger chip; alternatively, a discrete resistor placed next to the chip may also be used … provide a chip carrier which can be used”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Kimura to further include the teaching of Ruby to stack the IC chip with resistors on a chip carrier to provide high-density connections and heat dissipation and to form resistors on the chip carrier to free up the real estate on the IC chip.
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. (Kimura hereinafter) (US 7,061,093) as applied to claim 1 above, and in view of McKee et al. (McKee hereinafter) (US 6,418,029) and further in view of Japp et al. (Japp hereinafter) (US 2008/0191353).
Regarding Claims 8 and 9:
Kimura does not explicitly teach {8} the first layer is in contact with or a part of an integrated circuit package, wherein the interconnect component is between the integrated circuit package and a printed circuit board, and wherein the interconnect component is a solder ball; and {9} the first layer is in contact with or a part of a printed circuit board, wherein the interconnect component is between the printed circuit board and an integrated circuit package, and wherein the interconnect component is a solder ball.
McKee (see Abstract and col.2/l.59–col.4/l.23 and FIGs. 1 and 2) teaches an IC die 25 placed on chip carrier soldered to a PCB and “very small chip components (50) such as resistors” placed between a carrier substrate 10” and the PCB and “the interposer … also contains an integrated circuit die or an array of larger discrete chip components”, “vertically mounted component 50 provide an electrical interconnection path between the main PCB and the IC 25”, and “all the prior art depicts the chip components as being soldered at both ends to solder pads”.
Japp (see ¶ [0008] and FIGs. 6 and 7) teaches multilayered circuitized substrates such as printed circuit boards including inner-layers and ground planes and power planes separated by insulating layers and “various elements of these outer layers, such as pads may be electrically coupled to selected electronic components eventually mounted on the structure, such components including capacitors, resistor … even semiconductor chips”.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Kimura to include the teaching of McKee to mount the IC chip on a carrier substrate and to solder a resistor between the carrier substrate and the PCB and to further include the teaching of Japp to integrate resistor with PCB before it is soldered to other structures, such as IC package in order to place the resistors at desired locations.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. (Kimura hereinafter) (US 7,061,093) as applied to claim 1 above, and further in view of Takai et al. (Takai hereinafter) (JP 2003282788).
Regarding Claims 10 and 11:
Kimura does not explicitly teach {10} the interconnect component is a first interconnect component, and wherein the integrated circuit structure further comprises: a fourth layer comprising the first metal, wherein the second layer is above and in contact with the fourth layer, and wherein the second layer extends continuously and monolithically from above the first layer to above the fourth layer; a fifth layer above the second and fourth layers, the fifth layer comprising the second metal; and a second interconnect component above and in contact with the fifth layer; and {11} the first and second interconnect components are either solder bumps or solder balls.
Takai (see ¶ [0029] and FIG. 5) teaches a barrier metal resistor R3 (33) formed between bonding pad 1(31A) and bonding pad 2 (31B) on an IC chip 30, copper rewirings 34, copper posts 36, and solder balls 37.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Kimura to further include the teaching of Takai to extend the barrier metal layer B3 continuously and monolithically in order to be used as a current monitor resistor.
Claims 12 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. (Kimura hereinafter) (US 7,061,093) in view of Takai et al. (Takai hereinafter) (JP 2003282788) and further in view of Electrical Resistivity of Chemical Elements (https://material-properties.org/electrical-resistivity-of-chemical-elements/).
Regarding Claims 12 and 17:
Kimura (see FIG. 2) teaches {12} an integrated circuit structure comprising: a device B1; a resistive contact pad structure on the device, the resistive contact pad structure comprising (i) a lower layer B2 comprising a first metal (Al), (ii) an upper layer (B4, B5) above the lower layer, the upper layer comprising a second metal (Cu), and (iii) a resistor B3 between the lower layer and the upper layer; and a solder ball or solder bump B6 on the resistive contact pad structure, the solder ball or solder bump configured to couple the device to another device; wherein the resistive contact pad structure is a first resistive contact pad structure, wherein the lower layer is a first lower layer B2, wherein the upper layer is a first upper layer (B4, B5), and wherein integrated circuit structure further comprises: a second resistive contact pad structure on the device, the second resistive contact pad structure laterally adjacent to the first resistive contact pad structure, the second resistive contact pad structure comprising (i) a second lower layer B2 comprising the first metal (Al), (ii) a second upper layer (B4, B5) above the second lower layer, the second upper layer comprising the second metal (Cu), and (iii) the resistor between the second lower layer and the second upper layer and {17} the device is one of an integrated circuit die, an integrated circuit package, and a printed circuit board (PCB).
Kimura (see col.1/ll.59-63 and col.7/ll.16-22) teaches “In the conventional wafer level CSP, it is assumed that the aluminum electrode B2 placed on the pad of the IC chip B1 is connected to the copper post B5 and the solder bump (the solder ball) B6 only through the reroute trace B4 having a resistance as low as possible” and “deliberately lengthening or narrowing or both lengthening and narrowing he pattern of the copper reroute trace between the bonding pad 41 and the solder bump 43, or … by changing the material to a barrier metal, such as chromium (Cr) or titanium (Ti) … the resistance Rout can be designed to any desired value”.
However, Kimura does not explicitly teach {12} wherein a resistivity of the resistor is at least 20% greater than a resistivity of each of the lower and upper layers; wherein the resistor extends continuously and monolithically from between the first upper and lower layers to between the second upper and lower layers, and wherein the resistor is part of both the first and second resistive contact pad structures.
Takai (see ¶ [0029] and FIG. 5) teaches a barrier metal resistor R3 (33) formed between bonding pad 1(31A) and bonding pad 2 (31B) on an IC chip 30, copper rewirings 34, copper posts 36, and solder balls 37.
According to the table of Electrical Resistivity of Chemical Elements, the resistivity of Al is 26.5 nΩ·m; that of Cu is 16.8 nΩ·m; that of Cr is 125 nΩ·m; and that of Ti is 420 nΩ·m.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Kimura to include the teaching of Takai to extend the barrier metal layer B3 continuously and monolithically in order to be used as a current monitor resistor and to further include the teaching of the table of Electrical Resistivity of Chemical Elements to anticipate the resistivities of the resistor made of barrier metal, such as Cr or Ti are more than the electrodes sandwiching the resistor.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. (Kimura hereinafter) (US 7,061,093) in view of Takai et al. (Takai hereinafter) (JP 2003282788) and further in view of Electrical Resistivity of Chemical Elements (https://material-properties.org/electrical-resistivity-of-chemical-elements/) as applied to claim 12 above, and further in view of Kawazoe et al. (Kawazoe hereinafter) (US 2005/0153504).
Regarding Claim 13:
Kimura in the device of Takai in view of Electrical Resistivity of Chemical Elements does not explicitly teach the resistor comprises a third metal, and one or both of oxygen and nitrogen.
Kawazoe (see ¶ [0034] and [0035] and FIG. 1) teaches “the lower electrode, single noble metals including … Pt, Pd, Rh, and Ir …”, “the upper electrode … is not limited to the above noble metal elements but rather a variety of materials such as Al, Cu, Ni, Ti and Ta, as well as oxide conductors are applicable”, and a variable resistor made of perovskite-type metal oxide film.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Kimura in the device of Takai in view of Electrical Resistivity of Chemical Elements to further include the teaching of Kawazoe to use metal oxide material for the resistive element in order to form desired resistor properties.
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. (Kimura hereinafter) (US 7,061,093) in view of Takai et al. (Takai hereinafter) (JP 2003282788) and further in view of Electrical Resistivity of Chemical Elements (https://material-properties.org/electrical-resistivity-of-chemical-elements/) as applied to claim 12 above, and in view of Lam et al. (Lam hereinafter) (US 6,511,901) and further in view of Umemoto et al. (Umemoto hereinafter) (US 2021/0098585).
Regarding Claims 15 and 16:
Kimura in the device of Electrical Resistivity of Chemical Elements does not explicitly teach {15} a non-resistive contact pad structure laterally adjacent to the resistive contact pad structure, the non-resistive contact pad structure comprising a layer comprising the first metal, wherein a bottom surface of the layer of the non-resistive contact pad structure is coplanar with a bottom surface of the lower layer of the resistive contact pad structure, wherein the non-resistive contact pad structure lacks a resistor; and {16} the solder ball or solder bump is a first solder ball or a solder bump, and wherein the integrated circuit structure further comprises: a second solder ball or solder bump on the layer of the non-resistive contact pad structure; wherein a lower surface of the second solder ball or solder bump is on a first horizontal plane that is lower than a second horizontal plane of a lower surface of the first solder ball or solder bump.
Lam (see col.3/ll.4-8 and FIGs. 1 and 2I) teaches a solder bump 122 formed on a Cu layer 208 on a Ni layer 206 on a portion of an Al layer 204 and wire 230 bonded on another portion of the Al layer 204.
Umemoto (see FIG. 4) teaches a solder layer 76 formed on a metal pillar 73 at different heights.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the combined teaching of Kimura in the device of Takai in view of Electrical Resistivity of Chemical Elements to include the teaching of Lam to directly connect the lower electrode B2 without other metal layers B3 and B4 to meet the desired interconnect configuration and to further include the teaching of Umemoto to deposit the solder material directly onto the lower electrode B2 despite the different height of the bottom landing location in order to interconnect with external components.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kimura et al. (Kimura hereinafter) (US 7,061,093) in view of Takai et al. (Takai hereinafter) (JP 2003-282788) and further in view of Lam et al. (Lam hereinafter) (US 6,511,901).
Regarding Claims 18-20:
Kimura (see FIGs. 2-4B) teaches {18} a method to form a resistive contact pad structure and a non-resistive contact pad structure of an integrated circuit structure, comprising: forming, on a device 81, a first pad B2 and a laterally adjacent second pad B2; forming a resistor B3 on the first pad; forming a third pad (B4, B5) on the resistor and above the first pad, wherein a combination of the first pad, the resistor, and the third pad forms a resistive contact pad structure of the device, and wherein the second pad forms a non-resistive contact pad structure of the device; {19} depositing a first interconnect component B6 of the third pad, and a second interconnect component B6 of the second pad, wherein each of the first and second interconnect components is a corresponding solder ball or a solder bump; and {20} forming, on the device, a fourth pad B2 that is laterally adjacent to the first and second pads, wherein forming the resistor comprises forming (i) a first section B3 of the resistor on the first pad and (ii) a second section B3 of the resistor on the fourth pad, and forming a fifth pad (B4, B5) on the second section of the resistor and above the fourth pad, wherein a combination of the fourth pad, the second section of the resistor, and the fifth pad forms another resistive contact pad structure of the device.
Kimura (see col.1/ll.59-63, col.4/ll.48-56, and col.7/ll.16-22) teaches “In the conventional wafer level CSP, it is assumed that the aluminum electrode B2 placed on the pad of the IC chip B1 is connected to the copper post B5 and the solder bump (the solder ball) B6 only through the reroute trace B4 having a resistance as low as possible”; “the resistance of the reroute trace 4a is designed to be nearly zero and the resistance of the reroute trace 4b is designed to be a value of r1”; and “deliberately lengthening or narrowing or both lengthening and narrowing he pattern of the copper reroute trace between the bonding pad 41 and the solder bump 43, or … by changing the material to a barrier metal, such as chromium (Cr) or titanium (Ti) … the resistance Rout can be designed to any desired value”.
However, Kimura does not explicitly teach {18} without forming any resistor on the second pad; and {20} the first section and the second section of the resistor are part of a monolithic resistor structure;
Takai (see ¶ [0029] and FIG. 5) teaches a barrier metal resistor R3 (33) formed between bonding pad 1(31A) and bonding pad 2 (31B) on an IC chip 30, copper rewirings 34, copper posts 36, and solder balls 37.
Lam (see col.3/ll.4-8 and FIGs. 1 and 2I) teaches a solder bump 122 formed on a Cu layer 208 on a Ni layer 206 on a portion of an Al layer 204 and wire 230 bonded on another portion of the Al layer 204.
It would have been obvious to a person of ordinarily skilled in the art before the effective filing date of the instant invention to modify the teaching of Kimura to include the teaching of Takai to extend the barrier metal layer B3 continuously and monolithically in order to be used as a current monitor resistor and to further include the teaching of Lam to externally connect to the lower electrode B2 without other metal layers B3 and B4, via solder bump/ball to meet the desired interconnect configuration.
The differences in the step of not forming a resistor in non-resistive area when forming a resistor in resistive area will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such the step of not forming a resistor in non-resistive area when forming a resistor in resistive area are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Accordingly, since the applicant has not established the criticality (see next paragraph below) of the step of not forming a resistor in non-resistive area when forming a resistor in resistive area, it would have been obvious to one of ordinary skill in the art to selectively pattern a mask layer on the first metal layer to deposit the resistor and the second metal layer only in the resistive area and not in the non-resistive area to meet the circuit design requirements.
CRITICALITY
The specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934, 1936s (Fed. Cir. 1990).
Correspondence
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICE W TANG whose telephone number is (571)272-7227. The examiner can normally be reached Monday-Friday: 8:30 am to 5 pm..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571)272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALICE W TANG/Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814