Prosecution Insights
Last updated: April 19, 2026
Application No. 18/206,785

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME

Non-Final OA §112
Filed
Jun 07, 2023
Examiner
RAMALLO, GUSTAVO G
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
95%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
97%
With Interview

Examiner Intelligence

Grants 95% — above average
95%
Career Allow Rate
514 granted / 541 resolved
+27.0% vs TC avg
Minimal +2% lift
Without
With
+2.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
36 currently pending
Career history
577
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
50.9%
+10.9% vs TC avg
§102
30.1%
-9.9% vs TC avg
§112
15.4%
-24.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 541 resolved cases

Office Action

§112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on July 31, 2023. Information Disclosure Statement The information disclosure statement (IDS) submitted on June 7, 2023 is being considered by the examiner. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Three-Dimensional Semiconductor Memory Device With Dummy PAD for Short Circuit Prevention and Electronic System Including the Same Election/Restrictions Applicant’s election without traverse of device embodiment 1 (Fig. 6A, claims 1-12 and 19-20) in the reply filed on March 2, 2026 is acknowledged. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation "the pad portions of the gate electrodes" in line 13. There is insufficient antecedent basis for this limitation in the claim. For purposes of examination this will be interpreted as “the pad portion of each of the gate electrodes” Allowable Subject Matter Claims 1-12 would be allowed if rewritten to overcome the 112 rejection above. The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Kang (US 2017/0358590), Yun (US Pat. No. 9,343,452), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim: Regarding Claim 1 (from which claims 2-12 depend), the first pad portion and the second pad portion are spaced apart from the dummy pad, one of the interlayer insulating layers is interposed between the first pad portion and the dummy pad… Claims 19-20 are allowed. The following is an examiner’s statement of reasons for allowance: the closest prior art of record, Kang (US 2017/0358590), Yun (US Pat. No. 9,343,452), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim: Regarding Claim 19 (from which claim 20 depends), one of the interlayer insulating layers is interposed between the dummy pad and the first gate electrode Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kang (US 2017/0358590) discloses (Fig. 2N) a support insulating layer 300 dividing a gate electrode GL6 into two pad portions. However, Kang does not disclose the interlayer insulating layer interposed a pad portion and a dummy pad portion. Yun (US Pat. No. 9,343,452) discloses (Fig. 3) pads 120 with a gap between two portions. However, Yun does not disclose the interlayer insulating layer interposed a pad portion and a dummy pad portion. Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /G.G.R/Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jun 07, 2023
Application Filed
Mar 19, 2026
Non-Final Rejection — §112 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12596093
ORGANIC SEMICONDUCTOR DEVICE WITH PROTECTIVE SPINEL OXIDE LAYER
2y 5m to grant Granted Apr 07, 2026
Patent 12598745
DOUBLE PATTERNING METHOD OF MANUFACTURING SELECT GATES AND WORD LINES
2y 5m to grant Granted Apr 07, 2026
Patent 12593449
VERTICAL NONVOLATILE MEMORY DEVICE INCLUDING GATE ELECTRODES WITH METAL-DOPED GRAPHENE
2y 5m to grant Granted Mar 31, 2026
Patent 12593450
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
2y 5m to grant Granted Mar 31, 2026
Patent 12588201
MEMORY DEVICE WITH INCREASED DENSITY AND METHOD OF FABRICATING THE SAME
2y 5m to grant Granted Mar 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
95%
Grant Probability
97%
With Interview (+2.3%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 541 resolved cases by this examiner. Grant probability derived from career allow rate.

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