DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 12-19 in the reply filed on 9/22/25 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 is recited below (emphasis is added for purposes of clarity):
12. A semiconductor package structure, comprising:
a package substrate;
a first package layer formed on the package substrate; and
a die package device comprising a second package layer and a die device and in the package layer;
wherein the first package layer completely covers the die package device, and the die device is electrically connected with the package substrate.
Since Applicant previously recited both a first and second package layer- the package layer renders the claim indefinite. The meets and bounds of the claim cannot be determined- it is unclear whether the Applicant intends for the package layer to pertain to the first or second package layer.
Claims 13-19 depend from indefinite claim 12 and therefore are also rendered indefinite. For purposes of examination, the Examiner is interpreting that “the package layer” refers to the first package layer.
Moreover, please note that the phrasing: “a die package device comprising a second package layer and a die device and in the package layer;” is a bit awkward. The awkward phrasing does not give rise to a 112 problem (the Examiner can assess the meets/bounds of the language). However, the Examiner recommends (but does not require) that the Applicant revise this awkward phrasing.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 12-14 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Kelly et al (US 2014/0134804).
12. A semiconductor package structure, comprising:
a package substrate (Fig.1A (103) and [0023]);
a first package layer (Fig.1A (113) and [0023]) formed on the package substrate (Fig.1A (103) and [0023]); and
a die package device (Fig.1A (101) and [0023]) comprising a second package layer (Fig.1A (107) and [0023]) and a die device (Fig.1A (101) and [0023]) and in the package layer (Fig.1A (113) and [0023]);
wherein the first package layer (Fig.1A (113) and [0023]) completely covers the die package device (Fig.1A (101) and [0023]) , and the die device (Fig.1A (101) and [0023]) is electrically connected with the package substrate (Fig.1A (103) and [0023]).
13. The semiconductor package structure of claim 12, further comprising: first connection lines (Fig.1A (115) and [0025]) embedded in the second package layer (Fig.1A (107) and [0023]) and electrically connected with the die device (Fig.1A (101) and [0023-0024]); and second connection lines (Fig.1A (117/109) and [0024-0025]) and electrically connected between the first connection lines (Fig.1A (115) and [0025]) and the package substrate (Fig.1A (103) and [0023]).
14. The semiconductor package structure of claim 13, wherein the die device comprises: a plurality of dies stacked (Fig.1B-1E (DRAM/122/127) and [0030/0033]) with each other by first adhesive layers (Fig.1C-1E (129) and [0033]); and a plurality of connection pads [Fig.1B-1E (109/131) and 0033-0036]) on each of the plurality of dies and electrically connected with the first connection lines (Fig.1A (115) and [0025]) [see also 0036].
Claim(s) 12-16, 18-19 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Yap (US 2015/0076700).
12. A semiconductor package structure, comprising:
a package substrate (Fig.9 (114/118) and [0032]);
a first package layer (Fig.9 (112) and [0032]) formed on the package substrate (Fig.9 (114/118) and [0032]); and
a die package device (Fig.9 (100/108/120) and [0032]) comprising a second package layer (Fig.9 (106/118) and [0032]) and a die device (Fig.9 (108/120) and [0032]) and in the package layer (Fig.9 (106/118) and [0032]);
wherein the first package layer (Fig.9 (112) and [0032]) completely covers the die package device (Fig.9 (100/108/120) and [0032]) , and the die device (Fig.9 (108/120) and [0032]) is electrically connected with the package substrate (Fig.9 (114/118) and [0032]).
13. The semiconductor package structure of claim 12, further comprising: first connection lines (Fig.9 (110) and [0032]) embedded in the second package layer (Fig.9 (106/118) and [0032]) and electrically connected with the die device (Fig.9 (108/120) and [0032]); and second connection lines (Fig.9 (128/126) and [0032-0033]) and electrically connected between the first connection lines (Fig.9 (110) and [0032]) and the package substrate (Fig.9 (114/118) and [0032]).
14. The semiconductor package structure of claim 13, wherein the die device comprises: a plurality of dies stacked (Fig.9 (120/108) and [0032-0033]) with each other by first adhesive layers (Fig.9 (144) and [0034]); and a plurality of connection pads [Fig.9 (26- but unlabeled- see also Fig.1 (26)) and 0017]) on each of the plurality of dies (Fig.9 (120/108) and [0032-0033]) and electrically connected with the first connection lines (Fig.9 (110) and [0032]).
15. The semiconductor package structure of claim 14, wherein: the plurality of connection pads (Fig.9 (26- but unlabeled- see also Fig.1 (26)) and 0017]) face the package substrate (Fig.9 (114/118) and [0032]); the second package layer (Fig.9 (106/118) and [0032]) is attached to package substrate (Fig.9 (114/118) and [0032]) by a second adhesive layer (Fig.9 (144) and [0034]).
16. The semiconductor package structure of claim 15, further comprising: a residual adhesive layer (Fig.1 (24) and Fig. 9 (144) and [0018/0034]) on a first side of the die device (Fig.9 (108/120) and [0032]) away from the package substrate (Fig.9 (114/118) and [0032]), and sandwiched between the first package layer (Fig.9 (112) and [0032]) and the die device (Fig.9 (108/120) and [0032]).
18. The semiconductor package structure of claim 14, further comprising: a residual adhesive layer (Fig.1 (24) and Fig. 9 (144) and [0018/0034]) on a second side of the die device (Fig.9 (108/120) and [0032]) adjacent to the package substrate (Fig.9 (114/118) and [0032]); and a second adhesive layer (Fig. 9 (144) and [0034]) sandwiched between the package substrate (Fig.9 (114/118) and [0032]) and the die device (Fig.9 (108/120) and [0032]); wherein the residual adhesive layer is in contact with the adhesive layer (Fig.1 (24) and Fig. 9 (144) and [0018/0034]).
19. The semiconductor package structure of claim 18, wherein: the second connection lines (Fig.9 (128/126) and [0032-0033]) are embedded in the second adhesive layer (Fig. 9 (144) and [0034]); and the plurality of connection pads (Fig.9 (26- but unlabeled- see also Fig.1 (26)) and 0017]) face away the package substrate (Fig.9 (114/118) and [0032]).
Allowable Subject Matter
Prior art fails to teach nor suggest the limitations of claims 12, 13, 14, 15, 16 and 17 in combination as required by the dependency of claim 17. The 112 rejection of claim 17 still applies; however Applicant should note the existence of allowable subject matter, in the event that the 112 rejection is successfully resolved.
Claim 17 is recited below:
17. The semiconductor package structure of claim 16, wherein: the second connection lines are embedded in the first package layer; the first connection lines and the second connection lines are connected with each other at an interface between the first package layer and the second package layer; and a vertical distance from a highest point of the second connection lines to the package substrate is greater than a thickness of the die package device in a stacking direction.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Xu (CN 113013021); Iwamoto (US 20170271231) and Yeh et al (US 2022/0367311) teach similar structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA M MENZ whose telephone number is (571)272-1697. The examiner can normally be reached Monday-Friday 7:00-3:30.
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/LAURA M MENZ/Primary Examiner, Art Unit 2813
12/11/25