DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions & Claims’ Status
Applicant’s election without traverse of Group I (Claims 1-15 and 21-25) in the reply filed on 10/9/2025 is acknowledged.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention (Group II), there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 10/9/2025.
Claims 1-25 are currently pending, with Claims 1-15 and 21-25 being examined. No claims have been amended, cancelled, or newly added.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 6/7/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 1, 5, 9-10, 14, 21-22, and 25 are objected to because of the following informalities:
Claims 1, 10, and 21 all first make reference to “an insulation layer” and then “the insulating layer”, wherein “an insulating layer” is never previously established. For the purposes of examination, any reference to “the insulating layer” will be interpreted as referring to “the insulation layer”.
Claim 5 line 8 and Claim 11 line 8 include the wording “the width of the upper hole” and, wherein it is unclear if “the width of the upper hole” is referring to “a width”, “a first width”, or “a second width” established in lines 9-11 of Claim 1 and lines 10-11 of Claim 10, respectively. For the purposes of examination, the aforementioned “the width of the upper hole” will be interpreted as referring to the aforementioned “a width of the upper hole” established in line 9 of Claim 1 and line 10 of Claim 10, respectively.
Claim 9 lines 6-7 and Claim 14 lines 6-7 include the wording “the width of the upper hole in the first insulation layer” and “the width of the upper hole in the conductive layer”, wherein there is no “a width of the upper hole in the first insulation layer” previously established (improper antecedent basis) and it is unclear if “the width of the upper hole in the conductive layer” is referring to “a second width of the upper hole in the conductive layer” established in lines 11-12 of Claim 1 and lines 11-12 of Claim 10, respectively, or a different width. For the purposes of examination, the aforementioned “the width of the upper hole in the first insulation layer” and “the width of the upper hole in the conductive layer” will be interpreted, respectively, as “a width of the upper hole in the first insulation layer” and “a width of the upper hole in the conductive layer”.
Claim 21 lines 11-12 and Claim 22 lines 1-2 include the wording “a sidewall […] extend along/at”, where “extend” should be “extends”.
Claim 25 line 4 includes the wording “a cross-section of the sidewall of the middle hole”, wherein there is no “a sidewall of the middle hole” previously established (improper antecedent basis). For the purposes of examination, the aforementioned “the sidewall of the middle hole” will be interpreted as “a sidewall of the middle hole”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 10, 21-22, and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tay et al (US 2020/0253051 A1, hereafter Tay).
Re Claim 1, Tay discloses a substrate (FIG. 21; [0129]-[0135]) comprising:
an insulation layer (102; [0130]);
a conductive layer (100; [0130]) disposed on the insulation layer (102; [0130]); and
a via hole (132; [0131]) configured to include:
a lower hole (132, lower portion, see FIG. Z1 below; [0131]) disposed in a first portion of the insulation layer (102, portion housing the lower hole; [0131]), and
an upper hole (132, upper portion, see FIG. Z1 below; [0130]) disposed in a second portion of the insulating layer (102, portion housing the upper hole; [0130]) disposed above the first portion of the insulation layer (102, portion housing the lower hole; [0131]) and in the conductive layer (100; [0130]) and connected to the lower hole (132, lower portion; [0131]),
wherein a width of the upper hole (132, upper portion) is greater than that of the lower hole (132, lower portion; [0131]),
at least a portion of the upper hole (132, upper portion) in the second portion (102, portion housing the upper hole) has a first width that is substantially equal to a second width of the upper hole (132, upper portion) in the conductive layer (100; [0130], the upper hole’s width changes as it slopes downward, the width of the opening in the conductive layer 100 is within the width range of the upper hole), and
a first angle between a first direction (left to right across page of FIGS. 20-21; [0131]) that is parallel to a lower surface of the insulating layer (102, lower surface parallel with 112 upper surface; [0130]) and a sidewall of the lower hole (132, lower portion, right sidewall, angle counterclockwise from the first direction; [0131]) and a second angle between the first direction (left to right across page of FIGS. 20-21) and a sidewall of the upper hole (132, upper portion, right sidewall touching lateral sidewall of 100, right angle; [0130]) are different from each other ([0130]-[0131]).
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FIG. Z1: Annotated version of FIG. 21 of Tay
Re Claim 2, Tay discloses the substrate according to Claim 1, while further disclosing wherein:
the via hole (132) further includes a middle hole (132, middle portion, see FIG. Z1; [0130]-[0131]) disposed between the lower hole (132, lower portion) and the upper hole (132, upper portion; [0130]-[0131]),
wherein a third angle between the first direction (left to right across page of FIGS. 20-21) and a sidewall of the middle hole (132, middle portion, right sidewall touching upper hole, angle counterclockwise from the first direction; [0130]-[0131]) is different from the first angle (angle between first direction and 132, lower portion, right sidewall, angle counterclockwise from the first direction) and the second angle (angle between first direction and 132, upper portion, right sidewall touching lateral sidewall of 100, right angle; [0130]-[0131]).
Re Claim 3, Tay discloses the substrate according to Claim 2, while further disclosing wherein the first angle (angle between first direction and 132, lower portion, right sidewall, angle counterclockwise from the first direction) is smaller than the second angle (angle between first direction and 132, upper portion, right sidewall touching lateral sidewall of 100, right angle) and greater than the third angle (angle between the first direction and 132, middle portion, right sidewall touching upper hole, angle counterclockwise from the first direction; [0130]-[0131]).
Re Claim 4, Tay discloses the substrate according to Claim 2, while further disclosing wherein a cross-section of the sidewall of the middle hole (132, middle portion, right sidewall touching upper hole) has a curved shape ([0130]-[0131]).
Re Claim 10, Tay discloses a substrate (FIG. 21; [0129]-[0135]) comprising:
an insulation layer (102; [0130]);
a conductive layer (100; [0130]) disposed on the insulation layer (102; [0130]); and
a via hole (132; [0131]) configured to include:
a lower hole (132, lower portion, see FIG. Z1; [0131]) disposed in a first portion of the insulation layer (102, portion housing the lower hole; [0131]), and
an upper hole (132, upper portion, see FIG. Z1; [0130]) disposed in a second portion of the insulating layer (102, portion housing the upper hole; [0130]) disposed above the first portion of the insulation layer (102, portion housing the lower hole; [0131]) and in the conductive layer (100; [0130]), and
a middle hole (132, middle portion, see FIG. Z1; [0130]-[0131]) disposed between the lower hole (132, lower portion) and the upper hole (132, upper portion; [0130]-[0131]),
wherein a width of the upper hole (132, upper portion) is greater than that of the lower hole (132, lower portion; [0131]),
a first width of the upper hole (132, upper portion) in the second portion (102, portion housing the upper hole) and a second width of the upper hole (132, upper portion) in the conductive layer (100) are substantially equal to each other ([0130], the upper hole’s width changes as it slopes downward, the width of the opening in the conductive layer 100 is within the width range of the upper hole), and
a cross-section of a sidewall of the middle hole (132, middle portion, right sidewall touching upper hole) has a curved shape ([0130]-[0131]).
Re Claim 21, Tay discloses a substrate (FIG. 21; [0129]-[0135]) comprising:
an insulation layer (102; [0130]);
a conductive layer (100; [0130]) disposed on the insulation layer (102; [0130]); and
a via hole (132; [0131]) configured to include:
a lower hole (132, lower portion, see FIG. Z1; [0131]) disposed in a first portion of the insulation layer (102, portion housing the lower hole; [0131]), and
an upper hole (132, upper portion, see FIG. Z1; [0130]) disposed in a second portion of the insulating layer (102, portion housing the upper hole; [0130]) disposed above the first portion of the insulation layer (102, portion housing the lower hole; [0131]) and in the conductive layer (100; [0130]) and connected to the lower hole (132, lower portion; [0131]),
wherein a width of the upper hole (132, upper portion) is greater than that of the lower hole (132, lower portion; [0131]),
a sidewall of the upper hole (132, upper portion, left sidewall) in the second portion (102, portion housing the upper hole) and the conductive layer (100) extend along a thickness direction of the substrate ([0130], left sidewall of the upper hole in the second portion and the conductive layer can be considered a singular sidewall, in which it at least in part extends in the thickness direction via the lateral sidewall of conductive layer 100).
Re Claim 22, Tay discloses the substrate according to Claim 21, while further disclosing wherein a sidewall of the lower hole (132, lower portion, left sidewall) extend at an angle relative to the thickness direction ([0131]).
Re Claim 25, Tay discloses the substrate according to Claim 21, while further disclosing wherein:
the via hole (132) further includes a middle hole (132, middle portion, see FIG. Z1; [0130]-[0131]) disposed between the lower hole (132, lower portion) and the upper hole (132, upper portion; [0130]-[0131]),
a cross-section of the sidewall of the middle hole (132, middle portion, right sidewall touching upper hole) has a curved shape ([0130]-[0131]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Tay as applied to Claim 1 in view of Park et al (US 2015/0255301 A1, hereafter Park).
Re Claim 5, Tay discloses the substrate according to Claim 1, while further disclosing the substrate comprises:
a lower conduction pattern (114; [0130]) disposed below the first portion (102, portion housing the lower hole; [0131]); and
wherein the lower hole (132, lower portion) has a first width at a portion closer to the lower conductive pattern (114, first width is portion of lower hole in contact with the conductive pattern; [0131]) than a second width (second width is portion of lower hole in contact with middle hole; [0131]) that is greater than the first width (first width is portion of lower hole in contact with the conductive pattern; [0131]), the second width (second width is portion of lower hole in contact with middle hole) is disposed at a portion closer to the upper conductive pattern (upper conductive pattern taught below with Park, but second width would naturally be closer by being above first width) than the first width (first width is portion of lower hole in contact with the conductive pattern; [0131]), and
the width of the upper hole (132, upper portion) is greater than a maximum width of the lower hole (132, lower portion; [0130]-[0131]).
Tay does not explicitly disclose the substrate further comprises an upper conductive pattern disposed on the conductive layer (100).
However, Park teaches a substrate (FIG. 8; [0093]-[0098]) that comprises an upper conductive pattern (350; [0095]) disposed on the conductive layer (306; [0095]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate discussed for Claim 1 with the limitations taught by Park to include an upper conductive pattern (Park: 350) for the purposes of electrical signal transference as taught by Park ([0096]).
Re Claim 6, Tay and Park teach the substrate according to Claim 5, while Tay further teaches wherein:
the lower hole (132, lower portion) has a lower width at a portion in contact with the lower conductive pattern (114; [0131]), and the upper hole (132, upper portion) has an upper width at a portion in contact with the upper conductive pattern (upper conductive pattern taught with Park, but width of opening in layer 100 would be analogous “in contact” portion; [0130]), and
a ratio of the upper width to the lower width is greater than about 1 and equal to or smaller than about 3 ([0130]-[0131]).
Re Claim 7, Tay and Park teach the substrate according to Claim 5, while Park further teaches the substrate comprises a connection conductive pattern (341, 345; [0095]) disposed within the via hole (320; [0095]) and connected to the lower conductive pattern (348; [0095]) and the upper conductive pattern (350; [0095]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate discussed for Claim 5 with the limitations taught by Park to include a connection conductive pattern (Park: 350) for the purposes of electrical signal transference as taught by Park ([0096]).
Re Claim 8, Tay discloses the substrate according to Claim 1, but does not explicitly disclose wherein:
the insulation layer (102) further includes a first insulation layer disposed in the second portion (102, portion housing the upper hole),
wherein the upper hole (132, upper portion) is disposed in the first insulation layer and the conductive layer (100).
However, Park teaches a substrate (FIG. 5; [0078]-[0081]) wherein:
the insulation layer (100, 105; [0079], 100 is not explicitly an insulation layer, but the insulation layer teaching comes from Tay, Park is just adding a distinct insulation layer with a specific purpose) further includes a first insulation layer (105; [0079]) disposed in the second portion (100, 105, portion housing the upper hole 110; [0081]),
wherein the upper hole (110; [0081]) is disposed in the first insulation layer (105; [0081]) and the conductive layer (106; [0081]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate discussed for Claim 1 with the limitations taught by Park to include a first insulation layer to specifically protect the integrated circuit and/or insulating interlayer disposed between wiring layers as taught by Park ([0074]).
Re Claim 9, Tay discloses the substrate according to Claim 1, but does not explicitly disclose the substrate comprises:
a first insulation layer disposed between the insulation layer (102) and the conductive layer (100),
wherein the upper hole (132, upper portion) further includes a portion in the first insulation layer, and
the width of the upper hole (132, upper portion) in the first insulation layer is approximately equal to the width of the upper hole in the conductive layer (100).
However, Park teaches a substrate (FIG. 5; [0078]-[0081]) wherein:
a first insulation layer (105; [0079]) disposed between the insulation layer (100; [0079], 100 is not explicitly an insulation layer, but the insulation layer teaching comes from Tay, Park is just adding a separate insulation layer with a specific purpose) and the conductive layer (106; [0079]),
wherein the upper hole (110; [0081]) further includes a portion in the first insulation layer (105; [0079]), and
the width of the upper hole (110; [0081]) in the first insulation layer (105) is approximately equal to the width of the upper hole in the conductive layer (106; [0079]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate discussed for Claim 1 with the limitations taught by Park to include a first insulation layer to specifically protect the integrated circuit and/or insulating interlayer disposed between wiring layers as taught by Park ([0074]).
Claims 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Tay as applied to Claim 10 in view of Park.
Re Claim 11, Tay discloses the substrate according to Claim 10, while further disclosing the substrate comprises:
a lower conduction pattern (114; [0130]) disposed below the first portion (102, portion housing the lower hole; [0131]); and
wherein the lower hole (132, lower portion) has a first width at a portion closer to the lower conductive pattern (114, first width is portion of lower hole in contact with the conductive pattern; [0131]) than a second width (second width is portion of lower hole in contact with middle hole; [0131]) that is greater than the first width (first width is portion of lower hole in contact with the conductive pattern; [0131]), the second width (second width is portion of lower hole in contact with middle hole) is disposed at a portion closer to the upper conductive pattern (upper conductive pattern taught below with Park, but second width would naturally be closer by being above first width) than the first width (first width is portion of lower hole in contact with the conductive pattern; [0131]), and
the width of the upper hole (132, upper portion) is greater than a maximum width of the lower hole (132, lower portion; [0130]-[0131]).
Tay does not explicitly disclose the substrate further comprises an upper conductive pattern disposed on the conductive layer (100).
However, Park teaches a substrate (FIG. 8; [0093]-[0098]) that comprises an upper conductive pattern (350; [0095]) disposed on the conductive layer (306; [0095]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate discussed for Claim 10 with the limitations taught by Park to include an upper conductive pattern (Park: 350) for the purposes of electrical signal transference as taught by Park ([0096]).
Re Claim 12, Tay and Park teach the substrate according to Claim 11, while Tay further teaches wherein:
the lower hole (132, lower portion) has a lower width at a portion in contact with the lower conductive pattern (114; [0131]), and the upper hole (132, upper portion) has an upper width at a portion in contact with the upper conductive pattern (upper conductive pattern taught with Park, but width of opening in layer 100 would be analogous “in contact” portion; [0130]), and
a ratio of the upper width to the lower width is greater than about 1 and equal to or smaller than about 3 ([0130]-[0131]).
Re Claim 13, Tay discloses the substrate according to Claim 10, but does not explicitly disclose wherein:
the insulation layer (102) further includes a first insulation layer disposed in the second portion (102, portion housing the upper hole),
wherein the upper hole (132, upper portion) is disposed in the first insulation layer and the conductive layer (100).
However, Park teaches a substrate (FIG. 5; [0078]-[0081]) wherein:
the insulation layer (100, 105; [0079], 100 is not explicitly an insulation layer, but the insulation layer teaching comes from Tay, Park is just adding a distinct insulation layer with a specific purpose) further includes a first insulation layer (105; [0079]) disposed in the second portion (100, 105, portion housing the upper hole 110; [0081]),
wherein the upper hole (110; [0081]) is disposed in the first insulation layer (105; [0081]) and the conductive layer (106; [0081]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate discussed for Claim 10 with the limitations taught by Park to include a first insulation layer to specifically protect the integrated circuit and/or insulating interlayer disposed between wiring layers as taught by Park ([0074]).
Re Claim 14, Tay discloses the substrate according to Claim 10, but does not explicitly disclose the substrate comprises:
a first insulation layer disposed between the insulation layer (102) and the conductive layer (100),
wherein the upper hole (132, upper portion) further includes a portion in the first insulation layer, and
the width of the upper hole (132, upper portion) in the first insulation layer is approximately equal to the width of the upper hole in the conductive layer (100).
However, Park teaches a substrate (FIG. 5; [0078]-[0081]) wherein:
a first insulation layer (105; [0079]) disposed between the insulation layer (100; [0079], 100 is not explicitly an insulation layer, but the insulation layer teaching comes from Tay, Park is just adding a separate insulation layer with a specific purpose) and the conductive layer (106; [0079]),
wherein the upper hole (110; [0081]) further includes a portion in the first insulation layer (105; [0079]), and
the width of the upper hole (110; [0081]) in the first insulation layer (105) is approximately equal to the width of the upper hole in the conductive layer (106; [0079]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate discussed for Claim 10 with the limitations taught by Park to include a first insulation layer to specifically protect the integrated circuit and/or insulating interlayer disposed between wiring layers as taught by Park ([0074]).
Re Claim 15, Tay and Park teach the substrate according to Claim 14, but they do not explicitly disclose in their initially used embodiments wherein a central portion of the lower hole (Tay: 132, lower portion) and a central portion of the upper hole (Tay: 132, upper portion) are not vertically aligned.
However, Tay teaches in a separate embodiment (FIG. 28) wherein a central portion of the lower hole (132, lower portion, see FIG. Z2 below; [0157]) and a central portion of the upper hole (132, upper portion, see FIG. Z2 below; [0157]) are not vertically aligned ([0157]).
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Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate discussed for Claim 14 with the limitations taught by Tay to produce a simplified common laser through hole as taught by Tay ([0157]).
FIG. Z2: Annotated version of FIG. 28 of Tay
Claim 23 is rejected under 35 U.S.C. 103 as being unpatentable over Tay as applied to Claim 21 in view of Lee et al (US 2018/0242453 A1, hereafter Lee).
Re Claim 23, Tay discloses the substrate according to Claim 21, but does not explicitly disclose wherein the conductive layer (100) does not protrude toward an interior of the via hole (132).
However, Lee teaches a substrate (FIG. 4; [0049]) wherein the conductive layer (120; [0049]) does not protrude toward an interior of the via hole (112; [0049]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate discussed for Claim 21 with the limitations taught by Lee to remove the protrusion in the conductive layer (Tay: 100) to prevent structural defects as taught by Lee ([0032]).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Tay as applied to Claim 21 in view of Park.
Re Claim 24, Tay discloses the substrate according to Claim 21, but does not explicitly disclose wherein:
the insulation layer (102) further includes a first insulation layer disposed in the second portion (102, portion housing the upper hole),
wherein the upper hole (132, upper portion) is disposed in the first insulation layer and the conductive layer (100).
However, Park teaches a substrate (FIG. 5; [0078]-[0081]) wherein:
the insulation layer (100, 105; [0079], 100 is not explicitly an insulation layer, but the insulation layer teaching comes from Tay, Park is just adding a distinct insulation layer with a specific purpose) further includes a first insulation layer (105; [0079]) disposed in the second portion (100, 105, portion housing the upper hole 110; [0081]),
wherein the upper hole (110; [0081]) is disposed in the first insulation layer (105; [0081]) and the conductive layer (106; [0081]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate discussed for Claim 21 with the limitations taught by Park to include a first insulation layer to specifically protect the integrated circuit and/or insulating interlayer disposed between wiring layers as taught by Park ([0074]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892