DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 2/23/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment & Claims’ Status
The Amendment filed on 2/23/2026 has been entered. Claims 1-22 and 24-26 are currently pending. Claims 1-15, 21-22, and 24-26 are currently being examined, with Claims 16-20 being withdrawn due to the election without traverse on 10/9/2025. Claims 1, 9-10, 16, 19-21, and 25 have been amended. Claim 23 has been cancelled by the Applicant. Claim 26 has been newly added. Due to the amendments to the claims, the objections of Claims 1, 9-10, 21, and 25 of the previous Office Action (filed 11/25/2026) have been withdrawn.
Specification
The new title submitted 2/23/2026 is accepted by the Office.
Claim Objections
Claims 5, 11, 14 and 22 are objected to because of the following informalities:
Claim 5 line 7 and Claim 11 line 7 include the wording “the width of the upper hole” and, wherein it is unclear if “the width of the upper hole” is referring to “a width”, “a first width”, or “a second width” established in lines 9-11 of Claim 1 and lines 10-11 of Claim 10, respectively. For the purposes of examination, the aforementioned “the width of the upper hole” will be interpreted as “a width of the upper hole”.
Claim 14 lines 6-7 include the wording “the width of the upper hole in the first insulation layer” and “the width of the upper hole in the conductive layer”, wherein there is no “a width of the upper hole in the first insulation layer” previously established (improper antecedent basis) and it is unclear if “the width of the upper hole in the conductive layer” is referring to “a second width of the upper hole in the conductive layer” established in lines 11-12 of Claim 10 or a different width. For the purposes of examination, the aforementioned “the width of the upper hole in the first insulation layer” and “the width of the upper hole in the conductive layer” will be interpreted, respectively, as “a width of the upper hole in the first insulation layer” and “the second width of the upper hole in the conductive layer”.
Claim 22 lines 1-2 include the wording “a sidewall […] extend at”, where “extend” should be “extends”.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 4-8, 10-13, 21-22, and 24-26 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al (US 2015/0255301 A1, of record, hereafter Park) in view of Lee et al (US 2020/0163228 A1, hereafter Lee).
Re Claim 1, Park discloses a substrate (FIG. 5, with reference to FIG. 2; [0078]-[0081]) comprising:
an insulation layer (at least 105, hereafter 105; [0079]);
a conductive layer (106; [0079]) disposed on the insulation layer (105; [0079]); and
a via hole (120; [0079]) configured to include:
a lower hole (LH, see FIG. Z1 below, corresponding to D3; [0060]), and
an upper hole (UH, see FIG. Z1 below, corresponding in part to D1; [0058]) disposed in a second portion of the insulation layer (105, any portion; [0079]) and in the conductive layer (106; [0079]) and connected to the lower hole (LH; [0060]),
wherein a width of the upper hole (UH) is greater than that of the lower hole (LH; [0079]),
at least a portion of the upper hole (UH) in the second portion (105, any portion; [0079]) has a first width that is substantially equal to a second width of the upper hole (UH) in the conductive layer (106; [0079]),
a first angle between a first direction that is parallel to a lower surface of the insulation layer (105; [0079]) and a sidewall of the lower hole (LH; FIG. 2; [0079]) and a second angle between the first direction and a sidewall of the upper hole (UH; FIG. 2; [0079]) are different from each other (FIG. 2; [0079]), and
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the conductive layer (106) does not protrude toward an interior of the via hole (120; [0079]).
FIG. Z1: Annotated version of FIG. 5 of Park
Park does not explicitly disclose:
a lower hole (LH) disposed in a first portion of the insulation layer (105), and
an upper hole (UH) disposed in a second portion of the insulation layer (105, any portion) disposed above the first portion of the insulation layer (105).
Lee teaches a substrate (FIG. 3; [0084]-[0090]) comprising:
a lower hole (700, portion in 110; [0085]) disposed in a first portion of the insulation layer (110; [0085]), and
an upper hole (700, portion in at least part of 120; [0085]) disposed in a second portion of the insulation layer (120; [0085]) disposed above the first portion of the insulation layer (110; [0085]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Park with the limitations taught by Lee to include the lower hole (Park: LH) in the insulation layer, specifically in a lower insulating layer (Lee: 110, first portion of insulation layer) to have said lower insulating layer (Lee: 110) serve as an insulating bonding sheet for a lower conducting pad (Lee: 300) as taught by Lee ([0085]-[0086]).
Re Claim 2, Park and Lee teach the substrate according to Claim 1, while Park further teaches wherein:
the via hole (120) further includes a middle hole (MH, see FIG. Z1, corresponding to D2; [0058]) disposed between the lower hole (LH) and the upper hole (UH; [0060]),
wherein a third angle between the first direction and a sidewall of the middle hole (MH) is different from the first angle and the second angle (FIG. 2; [0060]).
Re Claim 4, Park and Lee teach the substrate according to Claim 2, while Park further teaches wherein a cross-section of the sidewall of the middle hole (MH) has a curved shape (FIG. 1B; [0059]).
Re Claim 5, Park and Lee teach the substrate according to Claim 1, while Park further teaches the substrate comprises:
an upper conductive pattern (150; [0069]) disposed on the conductive layer (106; [0079]); and
the width of the upper hole (UH) is greater than a maximum width of the lower hole (LH; [0060]).
Lee further teaches the substrate comprises:
a lower conduction pattern (300; [0085]) disposed below the first portion (110; [0085]); and
wherein the lower hole (700, portion in 110) has a first width at a portion closer to the lower conductive pattern (300; [0085]) than a second width that is greater than the first width ([0085], second width being any width above the first, as both Park and Lee have sloping sidewalls), the second width is disposed at a portion closer to the upper conductive pattern than the first width ([0085], Park teaches the upper conductive pattern, but this limitation would be met by nature of the second width being above the first width).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate according to Claim 1 with the limitations taught by Lee to include the a lower conduction pattern (Lee: 300) for the purposes of electrical signal transference as taught by Lee ([0085]-[0086]).
Re Claim 6, Park and Lee teach the substrate according to Claim 5, while Park further teaches wherein:
the lower hole (LH) has a lower width (width in Region I; FIG. 3; [0075]) at a portion in contact with the lower conductive pattern (Lee teaches the lower conductive pattern 300, but analogous contact point would be bottom flat surface in Region I, see FIG. 8; FIG. 3; [0075]), and the upper hole (UH) has an upper width at a portion in contact with the upper conductive pattern (150; [0079]), and
a ratio of the upper width to the lower width is greater than about 1 and equal to or smaller than about 3 (FIG. 2; [0057]).
Re Claim 7, Park and Lee teach the substrate according to Claim 5, while Park further teaches the substrate comprises a connection conductive pattern (140, 145; [0069]) disposed within the via hole (120; [0069]) and connected to the lower conductive pattern and the upper conductive pattern (150; [0069], Lee teaches the lower conductive pattern, which would be attached to the bottom of the connection conductive pattern, see FIG. 8).
Re Claim 8, Park and Lee teach the substrate according to Claim 1, while Park further teaches wherein:
the insulation layer (105) further includes a first insulation layer (“insulating interlayer”; [0074]) disposed in the second portion (105, any portion; [0074]),
wherein the upper hole (UH) is disposed in the first insulation layer (“insulating interlayer”) and the conductive layer (106; [0079]).
Re Claim 10, Park discloses a substrate (FIG. 5, with reference to FIG. 2; [0078]-[0081]) comprising:
an insulation layer (at least 105, hereafter 105; [0079]);
a conductive layer (106; [0079]) disposed on the insulation layer (105; [0079]); and
a via hole (120; [0079]) configured to include:
a lower hole (LH, see FIG. Z1, corresponding to D3; [0060]), and
an upper hole (UH, see FIG. Z1, corresponding in part to D1; [0058]) disposed in a second portion of the insulation layer (105, any portion; [0079]) and in the conductive layer (106; [0079]), and
a middle hole (MH, see FIG. Z1, corresponding to D2; [0058]) disposed between the lower hole (LH) and the upper hole (UH; [0060])
wherein a width of the upper hole (UH) is greater than that of the lower hole (LH; [0079]),
a first width of the upper hole (UH) in the second portion (105, any portion; [0079]) and a second width of the upper hole (UH) in the conductive layer (106; [0079]) are substantially equal to each other ([0079]),
a cross-section of the sidewall of the middle hole (MH) has a curved shape (FIG. 1B; [0059]), and
the conductive layer (106) does not protrude toward an interior of the via hole (120; [0079]).
Park does not explicitly disclose:
a lower hole (LH) disposed in a first portion of the insulation layer (105), and
an upper hole (UH) disposed in a second portion of the insulation layer (105, any portion) disposed above the first portion of the insulation layer (105).
Lee teaches a substrate (FIG. 3; [0084]-[0090]) comprising:
a lower hole (700, portion in 110; [0085]) disposed in a first portion of the insulation layer (110; [0085]), and
an upper hole (700, portion in at least part of 120; [0085]) disposed in a second portion of the insulation layer (120; [0085]) disposed above the first portion of the insulation layer (110; [0085]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Park with the limitations taught by Lee to include the lower hole (Park: LH) in the insulation layer, specifically in a lower insulating layer (Lee: 110, first portion of insulation layer) to have said lower insulating layer (Lee: 110) serve as an insulating bonding sheet for a lower conducting pad (Lee: 300) as taught by Lee ([0085]-[0086]).
Re Claim 11, Park and Lee teach the substrate according to Claim 10, while Park further teaches the substrate comprises:
an upper conductive pattern (150; [0069]) disposed on the conductive layer (106; [0079]); and
the width of the upper hole (UH) is greater than a maximum width of the lower hole (LH; [0060]).
Lee further teaches the substrate comprises:
a lower conduction pattern (300; [0085]) disposed below the first portion (110; [0085]); and
wherein the lower hole (700, portion in 110) has a first width at a portion closer to the lower conductive pattern (300; [0085]) than a second width that is greater than the first width ([0085], second width being any width above the first, as both Park and Lee have sloping sidewalls), the second width is disposed at a portion closer to the upper conductive pattern than the first width ([0085], Park teaches the upper conductive pattern, but this limitation would be met by nature of the second width being above the first width).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the substrate according to Claim 10 with the limitations taught by Lee to include the a lower conduction pattern (Lee: 300) for the purposes of electrical signal transference as taught by Lee ([0085]-[0086]).
Re Claim 12, Park and Lee teach the substrate according to Claim 11, while Park further teaches wherein:
the lower hole (LH) has a lower width (width in Region I; FIG. 3; [0075]) at a portion in contact with the lower conductive pattern (Lee teaches the lower conductive pattern 300, but analogous contact point would be bottom flat surface in Region I, see FIG. 8; FIG. 3; [0075]), and the upper hole (UH) has an upper width at a portion in contact with the upper conductive pattern (150; [0079]), and
a ratio of the upper width to the lower width is greater than about 1 and equal to or smaller than about 3 (FIG. 2; [0057]).
Re Claim 13, Park and Lee teach the substrate according to Claim 10, while Park further teaches wherein:
the insulation layer (105) further includes a first insulation layer (“insulating interlayer”; [0074]) disposed in the second portion (105, any portion; [0074]),
wherein the upper hole (UH) is disposed in the first insulation layer (“insulating interlayer”) and the conductive layer (106; [0079]).
Re Claim 21, Park discloses a substrate (FIG. 5, with reference to FIG. 2; [0078]-[0081]) comprising:
an insulation layer (at least 105, hereafter 105; [0079]);
a conductive layer (106; [0079]) disposed on the insulation layer (105; [0079]); and
a via hole (120; [0079]) configured to include:
a lower hole (LH, see FIG. Z1, corresponding to D3; [0060]), and
an upper hole (UH, see FIG. Z1, corresponding in part to D1; [0058]) disposed in a second portion of the insulation layer (105, any portion; [0079]) and in the conductive layer (106; [0079]) and connected to the lower hole (LH; [0060]),
wherein a width of the upper hole (UH) is greater than that of the lower hole (LH; [0079]),
at least a portion of the upper hole (UH) in the second portion (105, any portion; [0079]) has a first width that is substantially equal to a second width of the upper hole (UH) in the conductive layer (106; [0079]),
a sidewall of the upper hole (UH) in the second portion (105, any portion; [0079]) and the conductive layer (106; [0079]) extends along a thickness direction of the substrate (100, 105; [0079]), and
the conductive layer (106) does not protrude toward an interior of the via hole (120; [0079]).
Park does not explicitly disclose:
a lower hole (LH) disposed in a first portion of the insulation layer (105), and
an upper hole (UH) disposed in a second portion of the insulation layer (105, any portion) disposed above the first portion of the insulation layer (105).
Lee teaches a substrate (FIG. 3; [0084]-[0090]) comprising:
a lower hole (700, portion in 110; [0085]) disposed in a first portion of the insulation layer (110; [0085]), and
an upper hole (700, portion in at least part of 120; [0085]) disposed in a second portion of the insulation layer (120; [0085]) disposed above the first portion of the insulation layer (110; [0085]).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the limitations taught by Park with the limitations taught by Lee to include the lower hole (Park: LH) in the insulation layer, specifically in a lower insulating layer (Lee: 110, first portion of insulation layer) to have said lower insulating layer (Lee: 110) serve as an insulating bonding sheet for a lower conducting pad (Lee: 300) as taught by Lee ([0085]-[0086]).
Re Claim 22, Park and Lee teach the substrate according to Claim 21, while Park further teaches wherein a sidewall of the lower hole (LH) extend at an angle relative to the thickness direction (of 100, 105; [0079]).
Re Claim 24, Park and Lee teach the substrate according to Claim 21, while Park further teaches wherein:
the insulation layer (105) further includes a first insulation layer (“insulating interlayer”; [0074]) disposed in the second portion (105, any portion; [0074]),
wherein the upper hole (UH) is disposed in the first insulation layer (“insulating interlayer”) and the conductive layer (106; [0079]).
Re Claim 25, Park and Lee teach the substrate according to Claim 21, while Park further teaches wherein:
the via hole (120) further includes a middle hole (MH, see FIG. Z1, corresponding to D2; [0058]) disposed between the lower hole (LH) and the upper hole (UH; [0060]), and
a cross-section of a sidewall of the middle hole (MH) has a curved shape (FIG. 1B; [0059]).
Re Claim 26, Park and Lee teach the substrate according to Claim 2, while Park further teaches wherein the third angle is between the first direction and a lowest portion of the sidewall of the middle hole (MH; [0058]).
Allowable Subject Matter
Claims 3, 9, and 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable (for Claims 14-15, assuming that the objection to Claim 14 is addressed) if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Re Claim 3, the prior art cannot anticipate, or render obvious, the limitations of: the first angle is smaller than the second angle and greater than the third angle, in combination with the additionally claimed features of Claim 3.
Re Claim 9, the prior art cannot anticipate, or render obvious, the limitations of: a width of the upper hole in the first insulation layer is approximately equal to the second width of the upper hole in the conductive layer, in combination with the additionally claimed features of Claim 9.
Re Claim 14, the prior art cannot anticipate, or render obvious, the limitations of: the width of the upper hole in the first insulation layer is approximately equal to the second width of the upper hole in the conductive layer, in combination with the additionally claimed features of Claim 14.
In Re Claim 15, it is objected to due to its dependence on Claim 14.
Response to Arguments
Applicant’s arguments, see Remarks pg. 2, para. 9 to pg. 4, para. 1, filed 2/23/2026, with respect to the rejection(s) of Claims 1, 10, and 21 (in light of the new amendments) under 35 U.S.C. 102(a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Park and Lee under 35 U.S.C. 103. Applicant’s aforementioned arguments with respect to Claims 1, 10, and 21 have been reconsidered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLIN RUSSELL MCCUTCHEON whose telephone number is (703)756-1897. The examiner can normally be reached Monday-Friday, 12:30-9:30 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DREW N RICHARDS can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COLIN RUSSELL MCCUTCHEON/Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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