DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments, see pages 6-9, filed September 07, 2026, with respect to the 1, 6-11 and 16-20 rejection(s) of claims have been fully considered and are
persuasive. Therefore, the rejection has been withdrawn. A new ground(s) of rejection is necessitated by the amendment. Peng in view of He. Applicant’s arguments with respect to claims 1, 6-11 and 16-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 8-9, 11, 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Peng et al. US6,028,994 A in view of He et al. CN112415365A.
Claim 1, Peng discloses a die-level electrical parameter extraction method comprising: obtaining electrical parameters of a plurality of transistor types (fig. 1, 9, step 12, col. 3, ln. 45-54, col. 4, ln. 19-21) estimating a mapping relationship between the electrical parameters of the plurality of transistor types and the measurement results of the plurality of logic blocks (fig. 1, step 24, 30 and 40, col. 4, ln. 43-50, col. 6, ln. 57-67, fig. 9, step.66, performance Prediction Model (PPM) for use in predicting the performance of actual microelectronic devices, col. 9, ln. 4-7) and generating die-level electrical parameters of the plurality of transistor types according to the mapping relationship and the die-level measurement results (fig. 1, step 38, col. 6, ln. 61-66, fig. 9, step. 68, col. 8, ln. 41-44).
Peng does not disclose a wafer acceptance test (WAT) process; obtaining measurement results of a plurality of logic blocks from a die-level measurement that is part of a chip probing (CP) process; regarding a specific die of a wafer: obtaining die-level measurement results of the plurality of logic blocks; wherein the WAT process is applied to dies at WAT sites on the wafer, and the specific die is not at any of the WAT sites on the wafer.
He discloses a wafer acceptance test (WAT) process (fig. 1, par. [0025], [0040]); obtaining measurement results of a plurality of logic blocks (chips, par. [0043]) from a die-level (fig. 1, step S101, chip to be tested, par. [0025], [0040]-[0045]) measurement that is part of a chip probing (CP) process (fig. 1, 102a, S103, par. [0025], [0057]-[0064]); regarding a specific die (chip not selected for the acceptance test is the sampled chip, par. [0040]-[0043]) of a wafer (fig. 2 Step. 106, target wafer, par. [0085]-[0094]):obtaining die-level measurement results of the plurality of logic blocks (fig. 4, [0096]-[0099] [0115]-[0122]); wherein the WAT process is applied to dies at WAT sites on the wafer process (fig. 1, par. [0025], [0040]), and the specific die (chip not selected for the acceptance test is the sampled chip, par. [0040]-[0043]) is not at any of the WAT sites on the wafer (par. [0085]-[0094]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to obtain sampling information of target wafers selected to receive the wafer acceptance test. The chip identification information of at least one chip to be tested on a target wafer can then be used to determine whether to perform the Circuit Probing testing on each chip under test in the target wafer according to the sampling information, as taught in He in modifying the apparatus of Peng. The motivation would be any mass production test after the wafer acceptance test, additional tests other than the Circuit Probing testing can be performed on the chips sampled in the wafer verification test without interrupting the mass production process. (see He: par. [0025]).
Regarding claim 8, Peng and He discloses the die-level electrical parameter extraction method of claim 1, Peng discloses wherein the plurality of transistor types are differentiated by different threshold voltages (fig. 1, step 12, col. 3, ln. 45-54), (col. 8, ln. 49-53).
Regarding claim 9, Peng and He discloses the die-level electrical parameter extraction method of claim 1, Peng discloses wherein estimating the mapping relationship between the electrical parameters of the plurality of transistor types and the measurement results of the plurality of logic blocks comprises: using an artificial intelligence (AT) model for learning the mapping relationship (fig. 6, step 12, col. 5, ln. 61-col. 6, ln. 67).
Regarding claim 11, Peng discloses a non-transitory machine-readable medium for storing a program code, wherein when loaded and executed by a processor, the program code instructs the processor (computer program which produces a computer model that implements a function relating outputs to inputs, and run the program on a digital computer, col. 5, ln. 61-66, clm. 1) to perform following steps: obtaining electrical parameters of a plurality of transistor types (fig. 1, 9, step 12, col. 3, ln. 45-54, col. 4, ln. 19-21); estimating a mapping relationship between the electrical parameters of the plurality of transistor types and the measurement results of the plurality of logic blocks (fig. 1, step 24, 30 and 40, col. 4, ln. 43-50, col. 6, ln. 57-67, fig. 9, step.66, performance Prediction Model (PPM) for use in predicting the performance of actual microelectronic devices, col. 9, ln. 4-7); and regarding a specific die of a wafer: obtaining die-level measurement results of the plurality of logic blocks (fig. 1, step 36, col. 6, ln. 57-61, fig. 9, step. 22); and generating die-level electrical parameters of the plurality of transistor types according to the mapping relationship and the die-level measurement results (fig. 1, step 38, col. 6, ln. 61-66, fig. 9, step. 68, col. 8, ln. 41-44).
Peng does not disclose a wafer acceptance test (WAT) process;
obtaining measurement results of a plurality of logic blocks from a die-level measurement that is part of a chip probing (CP) process, wherein the WAT process is applied to dies at WAT sites on the wafer, and the specific die is not at any of the WAT sites on the wafer.
He discloses a wafer acceptance test (WAT) process (fig. 1, par. [0025], [0040]); obtaining measurement results of a plurality of logic blocks (chips, par. [0043]) from a die-level (fig. 1, step S101, chip to be tested, par. [0025], [0040]-[0045]) measurement that is part of a chip probing (CP) process (fig. 1, 102a, S103, par. [0025], [0057]-[0061], [0064]); regarding a specific die (chip not selected for the acceptance test is the sampled chip, par. [0040]-[0043]) of a wafer (fig. 2 Step. 106, target wafer, par. [0085]-[0094]):obtaining die-level measurement results of the plurality of logic blocks (fig. 4, [0096]-[0099] [0115]-[0122]); wherein the WAT process is applied to dies at WAT sites on the wafer process (fig. 1, par. [0025], [0040]); and the specific (chip not selected for the acceptance test is the sampled chip, par. [0040]-[0043]) is not at any of the WAT sites on the wafer (par. [0085]-[0094]).
The references are combined for the same reason already applied in the rejection of claim 7.
Regarding claim 18, Peng and He discloses the non-transitory machine-readable medium of claim 11, Peng discloses wherein the plurality of transistor types are differentiated by different threshold voltages (fig. 1, step 12, col. 3, ln. 45-54), (col. 8, ln. 49-53).
Regarding claim 19, Peng and He discloses the non-transitory machine-readable medium of claim 11, Peng discloses wherein estimating the mapping relationship between the electrical parameters of the plurality of transistor types and the measurement results of the plurality of logic blocks comprises: using an artificial intelligence (AT) model for learning the mapping relationship (fig. 6, col. 5, ln. 61-67-col. 6, ln 1-5).
Claims 6 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of He as applied to claim 1 or 11 above, and further in view of SU US 2020/0309843 A1.
Regarding claim 6, Peng and He discloses the die-level electrical parameter extraction method of claim 1, Peng and He do not disclose wherein each of the electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type; and each of the measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block.
SU discloses wherein each of the electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type; and each of the measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block (fig. 4, par. [0065]) (clm. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to (provide a method involving performing acceptability testing operation on wafers using WAT (Wafer Acceptance Test) to obtain a transistor device test parameters turn-on voltage, puncture voltage, saturation current, quiescent current, turn-off current as taught in SU in modifying the apparatus of Peng and He. The motivation would be to quickly and accurately determine if a wafer is compliant, thereby enabling the subsequent targeted parameter analysis and improving the efficiency of optimizing the process scheme. (see SU: par. [0006]).
Regarding claim 16, Peng and He discloses the non-transitory machine-readable medium of claim 11, Peng and He do not disclose wherein each of the electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type; and each of the measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block.
SU discloses wherein each of the electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type; and each of the measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block (fig. 4, par. [0065]) (clm. 6).
The references are combined for the same reason already applied in the rejection of claim 3.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of He as applied to claim 1 or 11 above, and further in view of Barnett et al. US 2009/0234777 A1 (hereinafter referred to as Barnett).
Regarding claim 7, Peng and He discloses the die-level electrical parameter extraction method of claim 1, Peng and He do disclose wherein each of the die-level measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block, and each of the die-level electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type.
Barnett discloses wherein each of the die-level measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block, and each of the die-level electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type (fig. 2, par, [0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform leakage current measurement using IDDQ testing and correlate leakage model to an on-chip measurement, as taught in Barnett in modifying the apparatus of Peng and He. The motivation would be to predict yield loss associated with performance screens or leakage screens (see abs.).
Regarding claim 17, Peng and He discloses the non-transitory machine-readable medium of claim 11, Peng and He do not disclose wherein each of the die-level measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block, and each of the die-level electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type.
Barnett discloses wherein each of the die-level measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block, and each of the die-level electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type (fig. 2, par, [0026]).
The references are combined for the same reason already applied in the rejection of claim 7.
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Peng in view of He as applied to claim 1 or 11 above, and further in view of Tsai et al. US 2012/0054709 A1 (hereinafter referred to as Tsai).
Regarding claim 10, Peng and He discloses the die-level electrical parameter extraction method of claim 1, Peng and He do not explicitly disclose wherein the mapping relationship is represented by a matrix; and generating the die-level electrical parameters of the plurality of transistor types comprises: performing matrix multiplication upon the matrix and the die-level measurement results to generate the die-level electrical parameters.
Tsai discloses wherein the mapping relationship is represented by a matrix (fig. 5A, par. [0025]-[0026]); and generating the die-level electrical parameters of the plurality of transistor types comprises: performing matrix multiplication upon the matrix and the die-level measurement results to generate the die-level electrical parameters (fig. 5A, par. [0025]-[0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide method to determine a mapping between model parameters and electrical parameters of integrated circuits, as taught in Tsai in modifying the apparatus of Peng and He. The motivation would be to quickly generate real-time model parameters from new target electrical parameter be used by a simulation tool. (see par. [0005]).
Regarding claim 20, Peng discloses the non-transitory machine-readable medium of claim 11, Peng and He do not explicitly disclose wherein the mapping relationship is represented by a matrix; and generating the die-level electrical parameters of the plurality of transistor types comprises: performing matrix multiplication upon the matrix and the die-level measurement results to generate the die-level electrical parameters.
Tsai discloses wherein the mapping relationship is represented by a matrix (fig. 5A, par. [0025]-[0026]); and generating the die-level electrical parameters of the plurality of transistor types comprises: performing matrix multiplication upon the matrix and the die-level measurement results to generate the die-level electrical parameters (fig. 5A, par. [0025]-[0026]).
The references are combined for the same reason already applied in the rejection of claim 10.
Conclusion
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/COURTNEY G MCDONNOUGH/ Examiner, Art Unit 2858
/FARHANA A HOQUE/ Primary Examiner, Art Unit 2858
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