DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 23 January 2026 have been fully considered but they are not persuasive. On page 6 applicant recites “Peng's computer correlation model/PPM fails to anticipate the claimed mapping relationship due to the fact that inputs of Peng's computer correlation model/PPM are parametric test values that are mapped to electrical parameters of transistor types being outputs of the claimed mapping relationship, and outputs of Peng's computer correlation model/PPM are
performance values that are mapped to measurement results of logic block being
inputs of the claimed mapping relationship. The examiner disagrees, claim 1, recites “… obtaining measurement results of a plurality of logic blocks…” , claim 1 does not make any distinction in type of measurement results of a plurality of logic blocks or its testing, the claim does not define the typed of logic blocks. The examiner equates the logic blocks to packages or integrated circuit chips of prior art Peng, which subject to functional and performance testing. (fig. 1, 9, package testing, step 20 and 22, col. 3, ln. 62-col. 4, ln. 1-4). Applicant further asserts “ that Peng's computer correlation model/PPM and the claimed mapping relationship have different functions and operations, and generating predicted performance values according to the computer correlation model/PPM and parametric test values as taught by Peng fails to disclose the following claimed limitations: “. The examiner disagrees, claim 1, recites “estimating a mapping relationship between the electrical parameters of the plurality of transistor types and the measurement results of the plurality of logic blocks” . Claim 1 does not define nor does it expand what “estimating a mapping relationship” is, the examiner equates estimating a mapping relationship with the correlation the parametric and performance values of step 24 of prior art Peng. Applicant further asserts “obtaining die-level measurement results of the plurality of logic blocks” the examiner equates estimating step 36 to determine how well it predicts performance values in response to input parametric values. Applicant further asserts “generating die-level electrical parameters of the plurality of transistor types according to the mapping relationship and the die-level measurement results” the examiner equates to evaluation made to decide if the correlation model is good enough for its intended use. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 9, 11-14 and 18-19 are rejected under 35 U.S.C. 102(a)(1) as being clearly anticipated by Peng et al. US6,028,994 A.
Regarding claim 1, Peng discloses a die-level electrical parameter extraction method comprising: obtaining electrical parameters of a plurality of transistor types (fig. 1, 9, step 12, col. 3, ln. 45-54, col. 4, ln. 19-21); obtaining measurement results of a plurality of logic blocks (fig. 1, 9, package testing, step 20 and 22, col. 3, ln. 62-col. 4, ln. 1-4); estimating a mapping relationship between the electrical parameters of the plurality of transistor types and the measurement results of the plurality of logic blocks (fig. 1, step 24, 30 and 40, col. 4, ln. 43-50, col. 6, ln. 57-67, fig. 9, step.66, performance Prediction Model (PPM) for use in predicting the performance of actual microelectronic devices, col. 9, ln. 4-7); and regarding a specific die of a wafer: obtaining die-level measurement results of the plurality of logic blocks (fig. 1, step 36, col. 6, ln. 57-61, fig. 9, step. 22); and generating die-level electrical parameters of the plurality of transistor types according to the mapping relationship and the die-level measurement results (fig. 1, step 38, col. 6, ln. 61-66, fig. 9, step. 68, col. 8, ln. 41-44).
Regarding claim 2, Peng discloses die-level electrical parameter extraction method of claim 1, wherein obtaining the electrical parameters of the plurality of transistor types (fig. 1, 9, step 12, col. 3, ln. 45-54, col. 4, ln. 19-21) comprises: obtaining the electrical parameters of the plurality of transistor types from a wafer-level process (wafers are subjected to Wafer Electrical Testing (WET) to obtain electrical circuit parameters or parametric test values col. 3, ln. 43-54).
Regarding claim 3, Peng discloses the die-level electrical parameter extraction method of claim 2, wherein the wafer-level process is a wafer acceptance test (WAT) process (fig. 1, step 28, col. 5, ln. 61-67).
Regarding claim 4, Peng discloses the die-level electrical parameter extraction method of claim 1, wherein obtaining the measurement results of the plurality of logic blocks comprises: obtaining the measurement results of the plurality of logic blocks from a die-level measurement (fig. 1, 9, step 22, col. 3, ln. 62-col. 4, ln. 1-4).
Regarding claim 8, Peng discloses the die-level electrical parameter extraction method of claim 1, wherein the plurality of transistor types are differentiated by different threshold voltages (fig. 1, step 12, col. 3, ln. 45-54), (col. 8, ln. 49-53).
Regarding claim 9, Peng discloses the die-level electrical parameter extraction method of claim 1, wherein estimating the mapping relationship between the electrical parameters of the plurality of transistor types and the measurement results of the plurality of logic blocks comprises: using an artificial intelligence (AT) model for learning the mapping relationship (fig. 6, step 12, col. 5, ln. 61-col. 6, ln. 67).
Regarding claim 11, Peng discloses a non-transitory machine-readable medium for storing a program code, wherein when loaded and executed by a processor, the program code instructs the processor (computer program which produces a computer model that implements a function relating outputs to inputs, and run the program on a digital computer, col. 5, ln. 61-66, clm. 1) to perform following steps: obtaining electrical parameters of a plurality of transistor types (fig. 1, 9, step 12, col. 3, ln. 45-54, col. 4, ln. 19-21); obtaining measurement results of a plurality of logic blocks (fig. 1, 9, step 20 and 22, col. 3, ln. 62-col. 4, ln. 1-4); estimating a mapping relationship between the electrical parameters of the plurality of transistor types and the measurement results of the plurality of logic blocks (fig. 1, step 24, 30 and 40, col. 4, ln. 43-50, col. 6, ln. 57-67, fig. 9, step.66, performance Prediction Model (PPM) for use in predicting the performance of actual microelectronic devices, col. 9, ln. 4-7); and regarding a specific die of a wafer: obtaining die-level measurement results of the plurality of logic blocks (fig. 1, step 36, col. 6, ln. 57-61, fig. 9, step. 22); and generating die-level electrical parameters of the plurality of transistor types according to the mapping relationship and the die-level measurement results (fig. 1, step 38, col. 6, ln. 61-66, fig. 9, step. 68, col. 8, ln. 41-44).
Regarding claim 12,The non-transitory machine-readable medium of claim 11, wherein obtaining the electrical parameters of the plurality of transistor types comprises: obtaining the electrical parameters of the plurality of transistor types (fig. 1, 9, step 12, col. 3, ln. 45-54, col. 4, ln. 19-21) from a wafer-level process (wafers are subjected to Wafer Electrical Testing (WET) to obtain electrical circuit parameters or parametric test values col. 3, ln. 43-54).
Regarding claim 13, Peng discloses the non-transitory machine-readable medium of claim 12, wherein the wafer-level process is a wafer acceptance test (WAT) process (fig. 1, step 28, col. 5, ln. 61-67).
Regarding claim 14, Peng discloses the non-transitory machine-readable medium of claim 11, wherein obtaining the measurement results of the plurality of logic blocks comprises: obtaining the measurement results of the plurality of logic blocks from a die-level measurement (fig. 1, 9, step 22, col. 3, ln. 62-col. 4, ln. 1-4).
Regarding claim 18, Peng discloses the non-transitory machine-readable medium of claim 11, wherein the plurality of transistor types are differentiated by different threshold voltages (fig. 1, step 12, col. 3, ln. 45-54), (col. 8, ln. 49-53)..
Regarding claim 19, Peng discloses the non-transitory machine-readable medium of claim 11, wherein estimating the mapping relationship between the electrical parameters of the plurality of transistor types and the measurement results of the plurality of logic blocks comprises: using an artificial intelligence (AT) model for learning the mapping relationship (fig. 6, col. 5, ln. 61-67-col. 6, ln 1-5).
Claims 6, 13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Peng as applied to claim 2 or 11 above, and further in view of SU US 2020/0309843 A1.
Regarding claim 6, Peng discloses the die-level electrical parameter extraction method of claim 1, Peng does not disclose wherein each of the electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type; and each of the measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block.
SU discloses wherein each of the electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type; and each of the measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block (fig. 4, par. [0065]) (clm. 6).
The references are combined for the same reason already applied in the rejection of claim 3.
Regarding claim 13, Peng discloses the non-transitory machine-readable medium of claim 12, wherein the wafer-level process is a wafer acceptance test (WAT) process.
Peng does not disclose wherein the wafer-level process is a wafer acceptance test (WAT) process.
SU discloses wherein the wafer-level process is a wafer acceptance test (WAT) process (par. [0045]).
The references are combined for the same reason already applied in the rejection of claim 3.
Regarding claim 16, Peng discloses the non-transitory machine-readable medium of claim 11, Peng does not disclose wherein each of the electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type; and each of the measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block.
SU discloses wherein each of the electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type; and each of the measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block (fig. 4, par. [0065]) (clm. 6).
The references are combined for the same reason already applied in the rejection of claim 3.
Claim(s) 5 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Peng as applied to claim 4 or 14 above, and further in view of Lai et al. US 2022/0336295 A1.
Regarding claim 5, Peng discloses the die-level electrical parameter extraction method of claim 4, Peng does not disclose the die-level electrical parameter extraction method of wherein the die-level measurement is a part of a chip probing (CP) process.
Lai discloses the die-level electrical parameter extraction method of wherein the die-level measurement is a part of a chip probing (CP) process (fig. 3, stop. S32, par. [0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply wafer-level chip probing process to the wafer to determine reliabilities of the group III-V semiconductor die, as taught in Lai in modifying the apparatus of Peng. The motivation would be wafer to determine reliabilities of group III-V semiconductor dies, and/or to recognize the reliable known good dies (KGDs. (see par. [0044]).
Regarding claim 15, Peng discloses the non-transitory machine-readable medium of claim 14, Peng does not disclose wherein the die-level measurement is a part of a chip probing (CP) process.
Lai discloses the die-level electrical parameter extraction method of wherein the die-level measurement is a part of a chip probing (CP) process (fig. 3, stp. S32, par. [0044]).
The references are combined for the same reason already applied in the rejection of claim 5.
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Peng as applied to claim 1 or 11 above, and further in view of Barnett et al. US 2009/0234777 A1 (hereinafter referred to as Barnett).
Regarding claim 7, Peng discloses the die-level electrical parameter extraction method of claim 1, Peng does not disclose wherein each of the die-level measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block, and each of the die-level electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type.
Barnett discloses wherein each of the die-level measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block, and each of the die-level electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type (fig. 2, par, [0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to perform leakage current measurement using IDDQ testing and correlate leakage model to an on-chip measurement, as taught in Barnett in modifying the apparatus of Peng. The motivation would be to provide predict yield loss associated with performance screens or leakage screens (see abs.).
Regarding claim 17, Peng discloses the non-transitory machine-readable medium of claim 11, Peng does not disclose wherein each of the die-level measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block, and each of the die-level electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type.
Barnett discloses wherein each of the die-level measurement results of the plurality of logic blocks is a block leakage current of a corresponding logic block, and each of the die-level electrical parameters of the plurality of transistor types is an integrated circuit quiescent current (IDDQ) of a corresponding transistor type (fig. 2, par, [0026]).
The references are combined for the same reason already applied in the rejection of claim 7.
Claims 10 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Peng as applied to claim 1 or 11 above, and further in view of Tsai et al. US 2012/0054709 A1 (hereinafter referred to as Tsai).
Regarding claim 10, Peng discloses the die-level electrical parameter extraction method of claim 1, Peng does not explicitly disclose wherein the mapping relationship is represented by a matrix; and generating the die-level electrical parameters of the plurality of transistor types comprises: performing matrix multiplication upon the matrix and the die-level measurement results to generate the die-level electrical parameters.
Tsai discloses wherein the mapping relationship is represented by a matrix (fig. 5A, par. [0025]-[0026]); and generating the die-level electrical parameters of the plurality of transistor types comprises: performing matrix multiplication upon the matrix and the die-level measurement results to generate the die-level electrical parameters (fig. 5A, par. [0025]-[0026]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide method to determine a mapping between model parameters and electrical parameters of integrated circuits, as taught in Tsai in modifying the apparatus of Peng. The motivation would be to quickly generate real-time model parameters from new target electrical parameter be used by a simulation tool. (see par. [0005]).
Regarding claim 20, Peng discloses the non-transitory machine-readable medium of claim 11, Peng does not explicitly disclose wherein the mapping relationship is represented by a matrix; and generating the die-level electrical parameters of the plurality of transistor types comprises: performing matrix multiplication upon the matrix and the die-level measurement results to generate the die-level electrical parameters.
Tsai discloses wherein the mapping relationship is represented by a matrix (fig. 5A, par. [0025]-[0026]); and generating the die-level electrical parameters of the plurality of transistor types comprises: performing matrix multiplication upon the matrix and the die-level measurement results to generate the die-level electrical parameters (fig. 5A, par. [0025]-[0026]).
The references are combined for the same reason already applied in the rejection of claim 10.
Applicant's arguments do not comply with 37 CFR 1.111(c) because they do not clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. Further, they do not show how the amendments avoid such references or objections.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY G MCDONNOUGH whose telephone number is (571)272-6552. The examiner can normally be reached M-F 8 am-5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EMAN ALKAFAWI can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/COURTNEY G MCDONNOUGH/Examiner, Art Unit 2858
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 5/29/2026
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