DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 9 and 11-13 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Geipel, Jr. et al. US 4,462,151.
Regarding claim 1, Geipel, Jr. et al. discloses in Figs. 1-6, a semiconductor device manufacturing method comprising:
performing a well implant process 22 on a region of a substrate 10, col. 3, lines 31-35;
performing a source/drain implant process 26, 28 on the region of the substrate 10, col. 3, lines 37-55;
defining an active area on the region of the substrate 10;
forming shallow trench isolations (STI) 66 in the active area, col. 4, lines 9-25; and
performing an annealing process to the region of the substrate 10, col. 4, lines 18-25.
Regarding claim 2, Geipel, Jr. et al. discloses in Figs. 1-6, the method of claim 1, wherein the source/drain implant process 26, 28 is performed after performing the well implant process 22.
Regarding claim 3, Geipel, Jr. et al. discloses in Figs. 1-6, the method of claim 1, wherein the active area is defined after performing the source/drain implant process, col. 4, lines 9-25.
Regarding claim 9, Geipel, Jr. et al. discloses in Figs. 1-6, the method of claim 1, wherein forming the STI 66 comprises etching the region to form trenches and forming insulation materials in the trenches (note: that while the trenches are formed before the source/drain implant process, the trenches are not filled with isolation until after the source/drain implant process.)
Regarding claim 11, Geipel, Jr. et al. discloses in Figs. 1-6, a semiconductor device manufacturing method comprising:
performing a dopant implant process on a region of a substrate 10, col. 3, lines 31-55;
forming an active area and shallow trench isolations on the region of the substrate 10 after performing the dopant implant process, col. 4, lines 9-25; and
performing an annealing process to the region of the substrate 10, col. 4, lines 18-25.
Regrading claim 12, Geipel, Jr. et al. discloses in Figs. 1-6 the method of claim 11, wherein performing the dopant implant process comprises performing a well implant process and performing a source/drain implant process, col. 3, lines 31-55.
Regarding claim 13, Geipel, Jr. et al. discloses in Figs. 1-6 the method of claim 11, wherein the annealing process is performed after forming the shallow trench isolations, col. 4, lines 18-25.
Claim(s) 1, 2, 4, 6-9, 11, 13 and 15-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Saha US 2023/0042167.
Regarding claim 1, Saha discloses in Figs. 3A-3T, a semiconductor device manufacturing method comprising:
performing a well implant process on a region of a substrate 302, Figs. 3B-3C;
performing a source/drain implant process on the region of the substrate 302, Figs. 3N-3R;
defining an active area on the region of the substrate;
forming shallow trench isolations (STI) 322 in the active area, Fig. 3K; and
performing an annealing process to the region of the substrate 302, [0072],
wherein the annealing process comprises a first annealing step using a first annealing temperature and a second annealing step using a second annealing temperature, the first annealing temperature is lower than the second annealing temperature. Saha teaches in Fig. 3S and [0072], performing a rapid thermal anneal process. By definition, an annealing process involves a heating process, from a first temperature to a second temperature, followed by a cooling process. Therefore, it is inherent that there will be a first temperature lower than a second temperature.
Regarding claim 2, Saha discloses in Figs. 3A-3T, the method of claim 1, wherein the source/drain implant process Figs. 3N-3R is performed after performing the well implant process Figs. 3B-3C.
Regarding claim 4, Saha discloses in Figs. 3A-3T, the method of claim 1, wherein the annealing process is performed after forming the STI, [0072].
Regarding claim 6, Saha discloses in Figs. 3A-3T and [0072] discloses the method of claim 1, wherein the first annealing step is a shallow-trench-isolation annealing. Saha teaches in Fig. 3S and [0072], performing a rapid thermal anneal process at the end of the processing of the device and would inherently anneal the STI.
Regarding claim 7, Saha discloses in Figs. 3A-3T and [0072] discloses the method of claim 1, wherein the second annealing step is a dopant-activation annealing. Saha teaches in Fig. 3S and [0072], performing a rapid thermal anneal process at the end of the processing of the device and would inherently activate a dopant.
Regarding claim 8, Saha discloses in Figs. 3A-3T and [0072] discloses the method of claim 7, wherein the dopant-activation annealing is performed by a rapid thermal annealing system [0072].
Regarding claim 9, Saha discloses in Figs. 3A-3T, the method of claim 1, wherein forming the STI 322 comprises etching the region to form trenches and forming insulation materials in the trenches [0058], Fig. 3K
Regarding claim 11, Saha discloses in Figs. 3A-3T, a semiconductor device manufacturing method comprising:
performing a dopant implant process on a region of a substrate 302 Figs. 3B-3C;
forming an active area and shallow trench isolations on the region of the substrate 302 Fig. 3K after performing the dopant implant process, Figs. 3B-3C; and
performing an annealing process to the region of the substrate [0072],
wherein the annealing process comprises a first annealing step using a first annealing temperature and a second annealing step using a second annealing temperature, the first annealing temperature is lower than the second annealing temperature. Saha teaches in Fig. 3S and [0072], performing a rapid thermal anneal process. By definition, an annealing process involves a heating process, from a first temperature to a second temperature, followed by a cooling process. Therefore, it is inherent that there will be a first temperature lower than a second temperature.
Regarding claim 13, Saha discloses in Figs. 3A-3T, the method of claim 11, wherein the annealing process is performed after forming the shallow trench isolations, [0072].
Regarding claim 15, Saha discloses in Figs. 3A-3T and [0072] discloses the method of claim 11, wherein the first annealing step is a shallow-trench-isolation annealing. Saha teaches in Fig. 3S and [0072], performing a rapid thermal anneal process at the end of the processing of the device and would inherently anneal the STI.
Regarding claim 16, Saha discloses in Figs. 3A-3T and [0072] discloses the method of claim 11, wherein the second annealing step is a dopant-activation annealing. Saha teaches in Fig. 3S and [0072], performing a rapid thermal anneal process at the end of the processing of the device and would inherently anneal the dopant-activation.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Geipel, Jr. et al. US 4,462,151 as applied to claim 9 above, and further in view of Cheng et al. US 2017/0170178.
Regarding claim 10, Geipel, Jr. et al. discloses in Figs. 1-6, the method of claim 9 wherein the insulation material is an oxide. Geipel, Jr. et al. does not expressly disclose wherein the insulation materials comprise oxide and nitride materials.
Cheng et al. in [0063] teaches trench isolation 140 filled with dielectric materials such as SiO2, TEOS oxide, HARP oxide, HTO, HDP oxides, silicon nitride, silicon oxynitride.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to substitute the silicon oxynitride of Cheng et al. because they have equivalent properties as recognized by Cheng et al. as a material for the STI.
It has been held that the substitution of one prior teaching by another art supports an obviousness rejection, as in the instant case, the equivalency is being recognized in the prior art, and the substitution is then within the level of ordinary skill in the art. [MPEP 2144.06.II]. See also MPEP § 2143(B), wherein it has been held that simple substitution of one known element for another to obtain predictable results is obvious. See MPEP § 2143(B). It is further held that, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
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/Sonya McCall-Shepard/Primary Examiner, Art Unit 2898