DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 6, and 7 are rejected under U.S.C. 103 as being unpatentable over Purushothaman et al.; US 2010/0078770 A1; 09/2008 in view of Trickett et al.; US 2010/0255682 A1; 03/2010
Claim 1: Purushothaman discloses a wafer bonding method, said method comprising: forming a patterned layer ( Fig. 5 (D) interconnect ensemble region #1100 and #1200, and #1300 ) on a substrate layer ( Fig. 5 (D) #1000 ), wherein the forming the patterned layer ( Fig. 5 (D) #1100, #1200, and #1300 ) comprises; planarizing the patterned layer formed by the conductive material and the dielectric material to form a planarized surface ( Fig. 5 (D) #1300 ); bonding a first wafer ( Fig. 5 (D) bottom portion of figure ) to the planarized surface ( Fig. 5 (D) #1300 ), wherein the first wafer comprises a first front surface layer ( Fig. 4(I) interconnect ensemble 1200 ) and a first back surface layer ( Fig. 4(I) sacrificial dielectric 1410 ), wherein the first front surface layer ( Fig. 4 (I) #1200 ) bonds to the planarized surface ( Fig. 4 (I) #1300 ); removing the first back surface layer ( Fig. 4 (I) #1410 sections removed for #1401 and #1402) of the first wafer bonded to the planarized surface ( Fig. 5(D) #1300 ) to expose a first etch stop layer in the first wafer ( [0050] etching a first set of deep openings for vias and alignment marks that extend through the device layer and interconnects to a certain depth into the first substrate ); removing the first etch stop layer to expose a first device layer in the first wafer ( Fig. 4 (I) #1410 ); applying a first protective mask ( [0074] a set of conducting studs #1401 and #1402 are formed in a sacrificial dielectric medium #1410 ) on the first device layer ( Fig. 5 (D) interconnect layer #1200 ) in a first pattern ( Fig. 5 (D) #1300 ) to form a first masked portion ( Fig. 4(I) #1410) and a first unmasked portion on the first device layer ( Fig. 4 (I) area not covered by #1410 ); etching the first unmasked portion on the first device layer to form a first ridge ( Fig. 5 (D) #1401 ), wherein the etching the first unmasked portion of the first device layer ( Fig. 5(D) #1200 ) to form the first ridge exposes the planarized surface ( Fig. 5(D) #1401 and #1402 ); bonding a second wafer ( Fig. 5(D) top portion ) to the planarized surface ( Fig. 5(D) #1300 ), wherein a second front surface of the second wafer comprises a pocket ( Fig. 5(D) #2431, and #2131 ) to receive the first ridge ( Fig. 5(D) #1401 and #1402 ), wherein the pocket ( Fig. 5(D) #2431 and #2131) is positioned on the second front surface of the second wafer to substantially match the location of the first ridge ( Fig. 5 (D) #1401 and #1402) on the planarized surface ( Fig. 5(D) #1300 ); removing a second back surface layer ( Fig. 5(G) #2510 ) of the second wafer ( Fig. 5(D) top portion) to expose a second etch stop layer ( [0065] a through via pattern is transferred from the resist into the hard mask layers from the resist and then etched into the layers) in the second wafer ( Fig. 5(D) top portion); removing the second etch stop layer to expose a third back surface layer of the second wafer ( [0056] After the via etch, the resist is stripped using a suitable dry or wet strip or a combination thereof.); removing the third back surface layer of the second wafer to expose a third etch stop layer in the second wafer ( Fig. 4(A) etching of #2130 ); removing the third etch stop layer to expose a second device layer in the second wafer ( Fig. 4(B) etching of #2121 ); applying a second protective mask ( Fig. 4 (A) #2130 ) on the second device layer ( Fig. 4(A) #2120 ) in a second pattern ( Fig. 4(A) #2110 ) to form a second masked portion ( Fig. 4(A) remaining portion of #2130 ) and a second unmasked portion ( Fig. 4(A) removed portion of #2130 where #2131 is formed ) on the second device layer ( Fig. 4(A) #2120 ); and etching the second unmasked portion of the second device layer to form a second ridge ( Fig. 4(C) edges of #2121 ), wherein the etching the second unmasked portion of the second device layer to form the second ridge exposes the planarized surface ( Fig. 4(C) #2100) , wherein the second ridge ( Fig. 5(D) #1402 ) is formed in proximity to the first ridge ( Fig. 5(D) #1401 ) on the planarized surface ( Fig. 5(D) #1300).
Purushothaman does not appear to disclose forming a first layer of a dielectric material on a top surface of the substrate layer; forming a plurality of openings having a first depth on the first layer of dielectric material; depositing a conductive material to fill the plurality of openings formed on the first layer of the dielectric material.
However, Trickett teaches forming a first layer of a dielectric material ( Fig. 1A bonding layer 104 ) on a top surface of the substrate layer ( Fig. 1A handling wafer 100 ); forming a plurality of openings ( Fig. 1A metal filled vias 106 ) having a first depth on the first layer of dielectric material ( [0014] The silicon bonding wafer 102 further contains a plurality of metal filled vias (holes) 106 in contact with the bonding layer 104 ); depositing a conductive material ( [0014] the metal filled vias 106 can contain or consist of Cu metal ) to fill the plurality of openings ( Fig. 1A #106 ) formed on the first layer of the dielectric material ( Fig. 1A #104 );
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Trickett with Purushothaman to implement forming a first layer of a dielectric material on a top surface of the substrate layer; forming a plurality of openings having a first depth on the first layer of dielectric material; depositing a conductive material to fill the plurality of openings formed on the first layer of the dielectric material because this sequence is fundamental for creating vias or contacts.
Claim 2: Purushothaman and Trickett disclose the wafer bonding method of claim 1 ( as discussed above).
Purushothaman teaches forming a first insulating layer ( [0051] providing a first insulating lining to protect the sidewalls of the first set of openings for via and alignment marks ) on the first ridge ( Fig. 5(D) #1401) and a second insulating layer ( Fig. 5 (C) conformal passivation coating #1449 ) on the second ridge ( Fig. 5 (D) #1402 ).
Claim 6: Purushothaman and Trickett disclose the wafer bonding method of claim 1 ( as discussed above).
Purushothaman teaches the forming the patterned layer ( Fig. 5 (D) #1100, #1200, and #1300 ) on the substrate layer ( Fig. 5(D) #1000 ) further comprises: forming the dielectric layer ( Fig. 5(D) #1300 ) on the substrate layer ( Fig. 5 (D) #1000 ); forming a plurality of openings ( [0025] This first substrate further comprises an upper insulator #1300 through which studs #1400 are provided ) on the dielectric layer ( Fig. 5(D) #1300 ), wherein each of the plurality of the openings has a third pattern ( Fig. 5(D) openings in #1300 ); and depositing the conductive material ( Fig. 5(D) #1401 and #1402 ) to fill the plurality of the openings formed on the dielectric layer ( Fig. 5( D) #1300) to form the patterned layer ( Fig. 5 (D) #1401 and #1402 alignment studs).
Claim 7: Purushothaman and Trickett disclose the wafer bonding method of claim 1 ( as discussed above).
Purushothaman teaches the forming the patterned layer ( Fig. 5(D) #1100, #1200, and #1300) on the substrate layer ( Fig. 5(D) #1000 ) further comprises: depositing the conductive material ( Fig. 5(D) #1100 and #1200) on the substrate layer ( Fig. 5(D) #1000); etching the conductive material deposited on the substrate layer in a third pattern with a plurality of openings to expose a top surface of the substrate layer ( [0053] etching a second set of deep via openings that extend all the way into some depth of the first substrate ); and depositing the dielectric material to fill the plurality of the openings formed to expose the top surface of the surface layer to form the patterned layer ( [0059] disposing a second insulating lining to protect the side walls of the second set of deep via openings and filling and planarizing the via openings with a second conductive material).
Claims 3-5 are rejected under U.S.C. 103 as being unpatentable over Purushothaman et al.; US 2010/0078770 A1; 09/2008 in view of Trickett et al.; US 2010/0255682 A1; 03/2010 as it relates to claim 1 and further in view of Keller et al.; US 2024/0063340 A1; 09/2010
Claim 3: Purushothaman and Trickett disclose the wafer bonding method of claim 1 ( as discussed above).
Purushothaman discloses the bonding the first wafer ( Fig. 5 (D) to the planarized surface ( Fig. 5 (D) #1300 ) comprises: positioning a front surface of the first wafer ( Fig. 5 (D) bottom portion) to face the planarized surface ( Fig. 5 (D) #1300); aligning the front surface of the first wafer with the planarized surface ( [0028] An art-known adhesive or equivalent is applied on the bottom wafer and studs are fabricated on that wafer ); applying a first pressure ( [0070] Material for the adhesive layer #2500 in some embodiments comprises a thermoset or thermoplastic polymer which has a good adhesion to the passivation dielectric #2300 and is capable of forming a strong bond to the second wafer under a lamination process involving elevated temperature and pressure ) to contact the front surface of the first wafer with the planarized surface at a center zone ( [0028] The two wafers are aligned with the studs in the bottom wafer aligned and contained in the via pockets in the upper wafer and laminated together using the adhesive bonding ); applying a second pressure to contact the front surface of the first wafer ( Fig. 5 (D) bottom portion) with the planarized surface ( Fig. 5(D) #1300) at a first annular zone ( [0070] The lamination is performed using one of a parallel plate platen pressure and isostatic gas pressure applied using a flexible conformal diaphragm, all of which is generally known in the art ); applying a third pressure to contact the front surface of the first wafer with the planarized surface at a second annular zone ( isostatic gas pressure as mentioned above );
Purushothaman does not appear to disclose exposing the contacted front surface of the first wafer and the planarized surface to a first heat treatment, wherein the exposing the contacted front surface of the first wafer and the planarized surface to the first heat treatment bonds the front surface of the first wafer to the planarized surface.
However, Keller teaches exposing the contacted front surface of the first wafer ( [0284] First sacrificial layer may be used for original substrate removal similar to processes as described above (Fig. 4 and Fig. 5) ) and the planarized surface to a first heat treatment ( [0284] The second layer is sued to facilitate relaxation of the strained layer post bonding. This can be done in conjunction with etching or/and heat treatment as desired ), wherein the exposing the contacted front surface of the first wafer and the planarized surface to the first heat treatment bonds the front surface of the first wafer to the planarized surface ( [0285] Following full or partial relaxation through porous GaN, the wafer is further bonded to a host substrate ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Keller with Purushothaman and Trickett to implement exposing the contacted front surface of the first wafer and the planarized surface to a first heat treatment, wherein the exposing the contacted front surface of the first wafer and the planarized surface to the first heat treatment bonds the front surface of the first wafer to the planarized surface because using a heat treatment creates a more robust, permanent bond between the two surfaces.
Claim 4: Purushothaman, Trickett, and Keller disclose the wafer bonding method of claim 3 ( as discussed above).
Purushothaman discloses the bonding the second wafer ( Fig. 5(D) top portion) to the planarized surface ( Fig. 5(D) #1300 ) comprises: etching a front surface of the second wafer to form the pocket ( Fig. 5(D) #2431 and #2131 ), wherein the pocket has a shape and dimensions to receive the first ridge ( as shown in Fig. 5(D)); positioning the front surface of the second wafer to face the planarized surface ( as shown in Fig. 5 (D)); adjusting the position of the front surface of the second wafer to align the pocket formed on the second wafer to receive the first ridge on the planarized surface ( Fig. 5(D) shows #2431 and #2131 receiving the posts #1401 and #1402); applying a fourth pressure to contact the front surface of the second wafer ( Fig. 5(D) #2500 ) and the planarized surface at the center zone ( Fig. 5(D) #2500 ); applying a fifth pressure ( [0070] Material for the adhesive layer #2500 in some embodiments comprises a thermoset or thermoplastic polymer which has a good adhesion to the passivation dielectric #2300 and is capable of forming a strong bond to the second wafer under a lamination process involving elevated temperature and pressure ) to contact the front surface of the second wafer ( Fig. 5(D) #2500 ) and the planarized surface at the first annular zone ( Fig. 5 (D) #2500 ); applying a sixth pressure to contact the front surface of the second wafer ( [0077] In the next step the two wafers are brought into physical contact and subjected to an isostatic pressure lamination process at an elevated temperature to enable bonding ) and the planarized surface at the second annular zone ( Fig. 5(D) studs #1402 get bonded to #2400 );
Purushothaman does not appear to disclose exposing the contacted front surface of the second wafer and the planarized surface to a second heat treatment, wherein the exposing the contacted front surface of the second wafer and the planarized surface to the second heat treatment bonds the front surface of the second wafer to the planarized surface.
However, Keller teaches exposing the contacted front surface of the second wafer ( [0282] Prior to bonding, both wafers may undergo surface treatments to promote high quality bonding ) and the planarized surface to a second heat treatment ( [0283] additional etching (wet/dry or combination) or/and heat treatment can be performed post process) , wherein the exposing the contacted front surface of the second wafer and the planarized surface to the second heat treatment bonds the front surface of the second wafer to the planarized surface ( [0285] Following full or partial relaxation through porous GaN, the wafer is further bonded to a host substrate ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Keller with Purushothaman and Trickett to implement exposing the contacted front surface of the second wafer and the planarized surface to a second heat treatment, wherein the exposing the contacted front surface of the second wafer and the planarized surface to the second heat treatment bonds the front surface of the second wafer to the planarized surface because using a heat treatment creates a more robust, permanent bond between the two surfaces.
Claim 5: Purushothaman, Trickett, and Keller disclose the wafer bonding method of claim 4 ( as discussed above ).
Neither Purushothaman nor Trickett appear to disclose the first and the second heat treatments comprise thermal annealing.
However, Keller teaches the first and the second heat treatments ( [0283] additional etching (wet/dry or combination) or/and heat treatment can be performed post process ) comprise thermal annealing ( [0287] Post bonding, the original substrate can be removed via wet etch. The p-type layer is now the top layer with polarity flipped. The p-type layer can now be activated by annealing ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Keller with Purushothaman and Trickett to implement the first and the second heat treatments comprise thermal annealing because the first heat treatment in a two-step annealing process relieves internal stresses and defects. The second heat treatment allows for the formation of new, strain free grains to replace the deformed ones.
Claims 10-13 are rejected under U.S.C. 103 as being unpatentable over Purushothaman et al.; US 2010/0078770 A1; 09/2008 in view of Lui et al.; US 2020/0212004 A1; 03/2019
Claim 10: Purushothaman discloses a wafer bonding method, said method comprising: providing a substrate layer ( Fig. 5(D) #1000); forming a dielectric layer ( Fig. 5(D) #1300) on the substrate layer ( Fig. 5(D) #1000); forming a plurality of openings ( Fig. 5(D) openings near #1401 and #1402 ) on the dielectric layer ( Fig. 5(D) #1300 ), wherein each of the plurality of the openings has a first pattern ( Fig. 5(D) #1400); depositing a conductive material to fill the plurality of the openings formed on the dielectric layer to form a patterned surface ( Fig. 5(D) #1401 and #1402) ; planarizing the patterned surface formed by the conductive material and the dielectric layer to form a planarized surface ( Fig. 5(D) #1300); bonding a first wafer to the planarized surface ( Fig. 5(D) bottom half of figure), wherein the first wafer comprises a first front surface layer ( Fig. 4(I) interconnect ensemble 1200 ) and a first back surface layer ( Fig. 4(I) sacrificial dielectric 1410 ), wherein the first front surface layer ( Fig. 4 (I) #1200 ) bonds to the planarized surface ( Fig. 4 (I) #1300 );removing the first back surface layer ( Fig. 4(I) #1410 sections removed for #1401 and 1402 ) of the first wafer bonded to the planarized surface ( Fig. 5(D) #1300 ) to expose a first etch stop layer ( [0050] etching a first set of deep openings for vias and alignment marks that extend through the device layer and interconnects to a certain depth into the first substrate ) in the first wafer ( Fig. 5(D) bottom portion of figure ); removing the first etch stop layer to expose a first device layer ( Fig. 5 (D) #1200 ) in the first wafer ( Fig. 5(D) bottom portion of figure ); applying a first protective mask on the first device layer ( Fig. 5(D) #1410 not listed but shown surrounding #1401 and #1402 ) in a second pattern to form a first masked portion ( Fig. 5(D) #1410 not listed but shown surrounding #1401 and #1402 ) and a first unmasked portion ( Fig. 5 (D) area not covered by #1410 ) on the first device layer ( Fig. 5(D) #1200 ); etching the first unmasked portion on the first device layer to form a first ridge (Fig. 5(D) #1401 ), wherein the etching the first unmasked portion of the first device layer to form the first ridge exposes the planarized surface ( Fig. 5(D) #1300 ); forming a first insulating layer on the first ridge ( [0051] providing a first insulating lining to protect the sidewalls of the first set of openings for via and alignment marks ); bonding a second wafer ( Fig. 5(D) top portion ) to the planarized surface ( Fig. 5(D) #1300 ), wherein the bonding the second wafer to the planarized surface comprises: etching a second front surface of the second wafer to form a pocket ( Fig. 5(D) #2431, and #2131 ), wherein the pocket has a shape and dimensions to receive the first ridge ( as shown in Fig. 5(D)); contacting the second front surface of the second wafer ( Fig. 5(D) #2500) with the planarized surface ( Fig. 5(D) #1300 ); removing a second back surface layer ( Fig. 5(G) #2510 ) of the second wafer ( Fig. 5(D) top portion) to expose a second etch stop layer ( [0065] a through via pattern is transferred from the resist into the hard mask layers from the resist and then etched into the layers) in the second wafer ( Fig. 5(D) top portion); removing the third back surface layer of the second wafer to expose a third etch stop layer in the second wafer ( Fig. 4(A) etching of #2130 ); removing the third etch stop layer to expose a second device layer in the second wafer ( Fig. 4(B) etching of #2121 ); applying a second protective mask ( Fig. 4 (A) #2130 ) on the second device layer ( Fig. 4(A) #2120 ) in a third pattern ( Fig. 4(A) #2110 ) to form a second masked portion ( Fig. 4(A) remaining portion of #2130 ) and a second unmasked portion ( Fig. 4(A) removed portion of #2130 where #2131 is formed ) on the second device layer ( Fig. 4(A) #2120 ); etching the second unmasked portion of the second device layer to form a second ridge ( Fig. 4(C) two #2121) , wherein the etching the second unmasked portion of the second device layer exposes the planarized surface ( Fig. 4(C) #2110 ), wherein the second ridge ( Fig. 4(C) #2121 ) is formed in proximity to the first ridge ( Fig. 4(C) #2121) on the planarized surface ( Fig. 4(C) #2110 ); and forming a second insulating layer( Fig. 4(C) #2122 ) on the second ridge ( Fig. 4 (C) #2121).
Purushothaman does not appear to discloses exposing the contacted second front surface of the second wafer and the planarized surface to a first heat treatment, wherein the exposing the contacted front surface of the second wafer and the planarized surface to the first heat treatment bonds the front surface of the second wafer to the planarized surface.
However, Lui teaches exposing the contacted second front surface of the second wafer and the planarized surface to a first heat treatment ( [0027] Plasma activation bonding method includes surface activation using oxygen or inert gas plasma, surface cleaning using deonized water, followed by preliminary bonding, and finally a heat treatment to bond the two wafers ), wherein the exposing the contacted front surface of the second wafer and the planarized surface to the first heat treatment bonds the second front surface of the second wafer to the planarized surface ( [0027] During the heat treatment, water molecules are removed in condensation reactions to form covalent bonds between front surfaces of the first and second wafers to achieve a stabilized bonding ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Keller with Purushothaman to implement exposing the contacted second front surface of the second wafer and the planarized surface to a first heat treatment, wherein the exposing the contacted front surface of the second wafer and the planarized surface to the first heat treatment bonds the second front surface of the second wafer to the planarized surface because using heat treatment creates stronger bonds between the surfaces.
Claims 11-13 are rejected under U.S.C. 103 as being unpatentable over Purushothaman et al.; US 2010/0078770 A1; 09/2008 in view of Lui et al.; US 2020/0212004 A1; 03/2019 as it applies to claim 10 and further in view of Keller et al.; US 2024/0063340 A1; 09/2010
Claim 11: Purushothaman and Liu disclose the wafer bonding method of claim 10 ( as discussed above).
Purushothaman discloses the bonding the first wafer ( Fig. 5 (D) bottom portion of figure ) to the planarized surface ( Fig. 5 (D) #1300 ) comprises: positioning a front surface of the first wafer ( Fig. 5 (D) bottom portion) to face the planarized surface ( Fig. 5 (D) #1300); aligning the front surface of the first wafer with the planarized surface ( [0028] An art-known adhesive or equivalent is applied on the bottom wafer and studs are fabricated on that wafer ); applying a first pressure to contact the front surface of the first wafer with the planarized surface at a center zone ( [0028] The two wafers are aligned with the studs in the bottom wafer aligned and contained in the via pockets in the upper wafer and laminated together using the adhesive bonding ); applying a second pressure to contact the front surface of the first wafer with the planarized surface at a first annular zone ( [0070] The lamination is performed using one of a parallel plate platen pressure and isostatic gas pressure applied using a flexible conformal diaphragm, all of which is generally known in the art ); applying a third pressure to contact the front surface of the first wafer with the planarized surface at a second annular zone ( isostatic gas pressure as mentioned above );
Purushothaman does not appear to disclose exposing the contacted front surface of the first wafer and the planarized surface to a second heat treatment, wherein the exposing the contacted front surface of the first wafer and the planarized surface to the second heat treatment bonds the front surface of the first wafer to the planarized surface.
However, Keller teaches exposing the contacted front surface of the first wafer ( [0284] First sacrificial layer may be used for original substrate removal similar to processes as described above (Fig. 4 and Fig. 5) ) and the planarized surface to a second heat treatment ( [0284] The second layer is used to facilitate relaxation of the strained layer post bonding. This can be done in conjunction with etching or/and heat treatment as desired ), wherein the exposing the contacted front surface of the first wafer and the planarized surface to the second heat treatment bonds the front surface of the first wafer to the planarized surface ( [0285] Following full or partial relaxation through porous GaN, the wafer is further bonded to a host substrate ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Keller with Purushothaman and Liu to implement exposing the contacted front surface of the first wafer and the planarized surface to a second heat treatment, wherein the exposing the contacted front surface of the first wafer and the planarized surface to the second heat treatment bonds the front surface of the first wafer to the planarized surface because using heat treatment creates stronger bonds between the two surfaces.
Claim 12: Purushothaman, Liu, and Keller disclose the wafer bonding method of claim 11( as discussed above).
Purushothaman does not appear to disclose the first and the second heat treatment comprises a thermal annealing.
Liu discloses the first heat treatment comprises thermal annealing ( [0058] the heat treatment can include thermally annealing first and second wafers 202 and 204 under nitrogen atmosphere, with an annealing temperature between about 200 ̊ C and about 450 ̊ C ).
Liu does not appear to disclose a second heat treatment.
However, Keller teaches the second heat treatment ( [0283] additional etching (wet/dry or combination) or/and heat treatment can be performed post process ) comprise thermal annealing ( [0287] Post bonding, the original substrate can be removed via wet etch. The p-type layer is now the top layer with polarity flipped. The p-type layer can now be activated by annealing ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Keller with Purushothaman and Liu to implement the first and the second heat treatment comprises a thermal annealing because the first heat treatment in a two-step annealing process relieves internal stresses and defects while the second heat treatment creates new strain-free grains to replace the deformed ones.
Claim 13: Purushothaman, Liu, and Keller disclose the wafer bonding method of claim 11 (as discussed above).
Purushothaman teaches contacting the front surface of the second wafer ( Fig. 5(D) top portion) with the planarized surface ( Fig. 5(D) #1300) comprises: positioning the second front surface of the second wafer to face the planarized surface ( as shown in Fig. 5 (D)); adjusting the position of the second front surface of the second wafer to align the pocket formed on the second wafer to receive the first ridge formed on the planarized surface ( Fig. 5(D) shows #2431 and #2131 receiving the posts #1401 and #1402); applying a fourth pressure ( [0070] Material for the adhesive layer #2500 in some embodiments comprises a thermoset or thermoplastic polymer which has a good adhesion to the passivation dielectric #2300 and is capable of forming a strong bond to the second wafer under a lamination process involving elevated temperature and pressure ) to contact the second front surface of the second wafer ( Fig. 5(D) #2500 ) and the planarized surface at the center zone ( Fig. 5(D) #2500 ); applying a fifth pressure ( [0070] The lamination is performed using one of a parallel plate platen pressure and isostatic gas pressure applied using a flexible conformal diaphragm, all of which is generally known in the art) to contact the second front surface of the second wafer ( Fig. 5(D) #2500 ) and the planarized surface at the first annular zone ( Fig. 5(D) #2500 ); and applying a sixth pressure ( [0077] In the next step the two wafers are brought into physical contact and subjected to an isostatic pressure lamination process at an elevated temperature to enable bonding ) to contact the second front surface of the second wafer and the planarized surface at the second annular zone.
Claims 16-18 are rejected under U.S.C. 103 as being unpatentable over Purushothaman et al.; US 2010/0078770 A1; 09/2008 in view of Trickett et al.; US 2010/0255682 A1; 03/2010 and Lui et al.; US 2020/0212004 A1; 03/2019 and further in view of Keller et al.; US 2024/0063340 A1; 09/2010
Claim 16: Purushothaman discloses a wafer bonding method, said method comprising: forming a patterned layer ( Fig. 5 (D) interconnect ensemble region #1100 and #1200, and #1300 ) on a substrate layer( Fig. 5 (D) #1000 ), wherein the forming the patterned layer ( Fig. 5 (D) #1100, #1200, and #1300 ) comprises: planarizing the patterned layer formed by the conductive material and the dielectric material to form a planarized surface ( Fig. 5 (D) #1300 ); bonding a first wafer ( Fig. 5 (D) bottom portion ) to the planarized surface ( Fig. 5 (D) #1300 ), wherein the first wafer comprises a first front surface layer ( Fig. 4(I) interconnect ensemble 1200 ) and a first back surface layer ( Fig. 4(I) sacrificial dielectric 1410 ), wherein the bonding the first wafer ( Fig. 4(I) #1200 ) to the planarized surface ( Fig. 4(I) #1300 ) comprises: positioning the first front surface ( Fig. 5(D) #1300 ) of the first wafer ( Fig. 5(D) bottom portion ) to face the planarized surface ( Fig. 5(D) #1300 ); aligning the first front surface ( Fig. 5(D) #1300) of the first wafer ( Fig. 5(D) bottom portion ) with the planarized surface ( Fig. 5(D) #1300 ) ; contacting the first front surface of the first wafer with the planarized surface ( Fig. 5 (D) bottom portion ); removing the first back surface layer ( Fig. 4 (I) #1410 sections removed for #1401 and #1402) of the first wafer bonded to expose a first etch stop layer ( [0050] etching a first set of deep openings for vias and alignment marks that extend through the device layer and interconnects to a certain depth into the first substrate ) in the first wafer ( Fig. 5(D) bottom portion ); removing the first etch stop layer to expose a first device layer in the first wafer ( Fig. 4 (I) #1410 ); applying a first protective mask ( [0074] a set of conducting studs #1401 and #1402 are formed in a sacrificial dielectric medium #1410 ) on the first device layer ( Fig. 5(D) #1200) in a first pattern ( Fig. 5(D) #1300 ) to form a first masked portion ( Fig. 4(I) #1410) and a first unmasked portion on the first device layer ( Fig. 4 (I) area not covered by #1410 ); etching the first unmasked portion on the first device layer to form a first ridge ( Fig. 5 (D) #1401 ), wherein the etching the first unmasked portion of the first device layer ( Fig. 5(D) #1200 ) to form the first ridge ( Fig. 5(D) #1401) exposes the planarized surface ( Fig. 5(D) #1300 ); forming a first insulating layer ( Fig. 5(C) #1449 ) on the first ridge ( Fig. 5(D) #1401); bonding a second wafer ( Fig. 5(D) top portion ) to the planarized surface ( Fig. 5(D) #1300), wherein the bonding the second wafer to the planarized surface comprises: etching a second front surface ( Fig. 4(A) etching of #2130) of the second wafer( Fig. 5(D) top portion ) to form a pocket ( Fig. 5(D) #2431 ), wherein the pocket ( Fig. 5(D) #2431) has a shape and dimensions to receive the first ridge ( Fig. 5(D) #1401), wherein the pocket ( Fig. 5(D) #2431) is positioned on the second front surface ( Fig. 5(D) #2500) of the second wafer ( Fig. 5(D) top portion ) to substantially match the location of the first ridge ( Fig. 5(D) #1401 formed on the planarized surface ( as shown in Fig. 5(D)); positioning the second front surface of the second wafer ( Fig. 5(D) top portion ) to face the planarized surface ( Fig. 5(D) #1300); adjusting the position of the second front surface of the second wafer to align the pocket ( Fig. 5(D) #2431) formed on the second wafer (Fig. 5(D) top portion ) to receive the first ridge ( Fig. 5(D) #1401 ) formed on the planarized surface; contacting the second front surface ( Fig. 5(D) #2500) of the second wafer ( Fig. 5(D) top portion ) and the planarized surface ( Fig. 5(D) #1300 ); removing a second back surface layer ( Fig. 5(G) #2510 ) of the second wafer ( Fig. 5(D) top portion) bonded to expose a second etch stop layer ( [0065] a through via pattern is transferred from the resist into the hard mask layers from the resist and then etched into the layers ) in the second wafer ( Fig. 5(D) top portion); removing the second etch stop layer to expose a third back surface layer of the second wafer ( [0056] After the via etch, the resist is stripped using a suitable dry or wet strip or a combination thereof ); removing the third back surface layer of the second wafer to expose a third etch stop layer in the second wafer ( Fig. 4(A) etching of #2130 ); removing the third etch stop layer to expose a second device layer in the second wafer ( Fig. 4(B) etching of #2121); applying a second protective mask ( Fig. 4 (A) #2130 ) on the second device layer ( Fig. 4(A) #2120) in a second pattern ( Fig. 4(A) #2110 ) to form a second masked portion ( Fig. 4(A) remaining portion of #2130 ) and a second unmasked portion ( Fig. 4(A) removed portion of #2130 where #2131 is formed ) on the second device layer ( Fig. 4(A) #2120 ); etching the second unmasked portion of device layer to form a second ridge ( Fig. 4(C) edges of #2121 ), wherein the etching the second unmasked portion of the second device layer exposes the planarized surface ( Fig. 4(C) #2100 ), wherein the second ridge (Fig. 5(D) #1402 ) is formed in proximity to the first ridge ( Fig. 5(D) #1401 ) on the planarized surface ( Fig. 5(D) #1300 ); and forming a second insulating layer ( Fig. 5 (C) conformal passivation coating #1449 ) on the second ridge ( Fig. 5(D) #1402 ).
Purushothaman does not appear to disclose forming a first layer of a dielectric material on a top surface of the substrate layer; forming a plurality of openings having a first depth on the first layer of dielectric material; depositing a conductive material to fill the plurality of openings formed on the first layer of the dielectric material; exposing the contacted first front surface of the first wafer and the planarized surface to a first thermal annealing, wherein the exposing the contacted first front surface of the first wafer and the planarized surface to the first thermal annealing bonds the first front surface of the first wafer to the planarized surface; and exposing the contacted second front surface of the second wafer and the planarized surface to a second thermal annealing, wherein the exposing the contacted second front surface of the second wafer and the planarized surface to the second thermal annealing bonds the second front surface of the second wafer to the planarized surface.
However, Trickett discloses forming a first layer of a dielectric material ( Fig. 1A bonding layer 104 ) on a top surface of the substrate layer ( Fig. 1A handling wafer 100 ); forming a plurality of openings ( Fig. 1A metal filled vias 106 ) having a first depth on the first layer of dielectric material ( [0014] The silicon bonding wafer 102 further contains a plurality of metal filled vias (holes) 106 in contact with the bonding layer 104 ); depositing a conductive material ( [0014] the metal filled vias 106 can contain or consist of Cu metal ) to fill the plurality of openings ( Fig. 1A #106 ) formed on the first layer of the dielectric material ( Fig. 1A #104 );
Trickett does not appear to disclose exposing the contacted first front surface of the first wafer and the planarized surface to a first thermal annealing, wherein the exposing the contacted first front surface of the first wafer and the planarized surface to the first thermal annealing bonds the first front surface of the first wafer to the planarized surface; and exposing the contacted second front surface of the second wafer and the planarized surface to a second thermal annealing, wherein the exposing the contacted second front surface of the second wafer and the planarized surface to the second thermal annealing bonds the second front surface of the second wafer to the planarized surface.
Liu discloses exposing the contacted first front surface of the first wafer ( Fig. 2D #202 ) and the planarized surface ( Fig. 2D #204 ) to a first thermal annealing ( [0058] the heat treatment can include thermally annealing first and second wafers 202 and 204 under nitrogen atmosphere, with an annealing temperature between about 200 ̊ C and about 450 ̊ C), wherein the exposing the contacted first front surface of the first wafer ( Fig. 2D #202 ) and the planarized surface ( Fig. 2D #204 ) to the first thermal annealing ( as discussed above) bonds the first front surface of the first wafer ( Fig. 2D #202 ) to the planarized surface ( Fig. 2D #204 );
Liu does not appear to disclose exposing the contacted second front surface of the second wafer and the planarized surface to a second thermal annealing, wherein the exposing the contacted second front surface of the second wafer and the planarized surface to the second thermal annealing bonds the second front surface of the second wafer to the planarized surface.
However, Keller teaches exposing the contacted second front surface ( Fig. 5(D) #2500 ) of the second wafer ( Fig. 5(D) top portion ) and the planarized surface ( Fig. 5(D) #1300 ) to a second thermal annealing ( [0287] Post bonding, the original substrate can be removed via wet etch. The p-type layer is now the top layer with polarity flipped. The p-type layer can now be activated by annealing ), wherein the exposing the contacted second front surface ( Fig. 5(D) #2500 ) of the second wafer ( Fig. 5(D) top portion ) and the planarized surface ( Fig. 5(D) #1300 ) to the second thermal annealing ( [0285] Following full or partial relaxation through porous GaN, the wafer is further bonded to a host substrate ) bonds the second front surface ( Fig. 5(D) #2500 ) of the second wafer ( Fig. 5(D) top portion ) to the planarized surface ( Fig. 5(D) #1300 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Keller with Purushothaman and Trickett to implement exposing the contacted first front surface of the first wafer and the planarized surface to a first thermal annealing, wherein the exposing the contacted first front surface of the first wafer and the planarized surface to the first thermal annealing bonds the first front surface of the first wafer to the planarized surface; and exposing the contacted second front surface of the second wafer and the planarized surface to a second thermal annealing, wherein the exposing the contacted second front surface of the second wafer and the planarized surface to the second thermal annealing bonds the second front surface of the second wafer to the planarized surface because the first heat treatment in a two-step annealing process relieves internal stresses and defects while the second heat treatment forms new strain-free grains to replace the deformed ones.
Claim 17: Purushothaman, Trickett, and Keller disclose the wafer bonding method of claim 16 ( as discussed above).
Purushothaman teaches the forming the patterned layer ( Fig. 5(D) interconnect ensemble region #1100 and #1200, and #1300 ) on the substrate layer ( Fig. 5(D) #1000 ) further comprises: forming the first layer of dielectric material layer ( Fig. 5 (D) #1300 ) on the substrate layer ( Fig. 5(D) #1000 ); forming a plurality of openings on the first layer of dielectric material layer ( Fig. 5(D) openings for #1401 and #1402 ), wherein each of the plurality of the openings has a third pattern ( Fig. 5(D) pattern filled by#1230 ); and depositing the conductive material ( Fig. 5 #1210, #1215, #1220, and #1230 ) to fill the plurality of the openings ( Fig. 5(D) openings for #1401 and #1402 ) formed on the first layer of dielectric material layer to form the patterned layer ( Fig. 5(D) #1300 ).
Claim 18: Purushothaman, Trickett, and Keller disclose the wafer bonding method of claim 16 ( as discussed above).
Purushothaman teaches the forming the patterned layer ( Fig. 5(D) interconnect ensemble region #1100 and #1200, and #1300 ) on the substrate layer ( Fig. 5(D) #1000 ) further comprises: depositing the conductive material ( Fig. 5(D) #1210, #1215, #1220, and #1230 ) on the substrate ( Fig. 5(D) #1000 ); etching the conductive material deposited on the substrate layer ( [0053] etching a second set of deep via openings that extend all the way into some depth of the first substrate ) in a third pattern ( Fig. 5(D) pattern filled by#1230 ) with a plurality of openings ( Fig. 5(D) openings for #1401 and #1402 ) to expose a top surface of the substrate layer ( Fig. 5(D) #1000 ); and depositing a first layer of dielectric material ( Fig. 5(D) #1300 ) to fill the plurality of the openings ( Fig. 5(D) #1401 and #1402) formed to expose the top surface of the surface layer to form the patterned layer ( Fig. 5(D) #1300 ).
Claim 8 is rejected under U.S.C. 103 as being unpatentable over Purushothaman et al.; US 2010/0078770 A1; 09/2008 in view of Trickett et al.; US 2010/0255682 A1; 03/2010 as it relates to claim 1 and further in view of Lee et al.; US 2015/0060843 A1; 02/2014
Claim 8: Purushothaman and Trickett disclose the wafer bonding method of claim 1 ( as discussed above).
Neither Purushothaman nor Trickett appear to disclose the first, the second and the third back surface layers are removed using backside exposure process.
However, Lee teaches the first, the second and the third back surface layers are removed using backside exposure process ( [0063] the photoresist layer #150 may be exposed by a backside exposure process).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Purushothaman and Trickett to implement the first, the second and the third back surface layers are removed using backside exposure process because this can enhance electrical performance and prevent contamination by removing residual photoresist, polymers, or other films that may have migrated to the backside during front-side processing.
Claims 9 is rejected under U.S.C. 103 as being unpatentable over Purushothaman et al.; US 2010/0078770 A1; 09/2008 in view of Trickett et al.; US 2010/0255682 A1; 03/2010 as it relates to claim 1 and further in view of Kuo et al.; US 2015/0001593 A1; 06/2013
Claim 9: Purushothaman and Trickett disclose the wafer bonding method of claim 1 ( as discussed above).
Neither Purushothaman nor Trickett appear to disclose the first, the second and the third etch stop layers are removed using hydrogen fluoride.
However, Kuo teaches the first, the second and the third etch stop layers are removed using hydrogen fluoride ( [0058] Formation of the source recesses #1302a and the drain recesses #1302b may be performed using one or more etching processes comprising a dry etching process and/or a wet etching process. The etching process may use a wet etchant comprising carbon tetrafluoride, hydrogen fluoride, tetramethylammonium hydroxide, potassium hydroxide, ethylene diamine pyrocatechol, etc. ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kuo with Purushothaman and Trickett to implement the first, the second and the third etch stop layers are removed using hydrogen fluoride because hydrogen fluoride is used to remove etch stop layers, typically made of silicon dioxide due to its high selectivity.
Claims 14 and 19 are rejected under U.S.C. 103 as being unpatentable over Purushothaman et al.; US 2010/0078770 A1; 09/2008 in view of Keller et al.; US 2024/0063340 A1; 09/2010 with regard to claim 10 and 16 and further in view of Lee et al.; US 2015/0060843 A1; 02/2014
Claim 14: Purushothaman and Keller disclose the wafer bonding method of claim 10 ( as discussed above).
Neither Purushothaman nor Keller appear to disclose the first, the second and the third back surface layers are removed using backside exposure process.
However, Lee teaches the first, the second and the third back surface layers are removed using backside exposure process ( [0063] the photoresist layer #150 may be exposed by a backside exposure process).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Purushothaman and Keller to implement the first, the second and the third back surface layers are removed using backside exposure process because this can enhance electrical performance and prevent contamination by removing residual photoresist, polymers, or other films that may have migrated to the backside during front-side processing.
Claim 19: Purushothaman and Keller discloses the wafer bonding method of claim 16 ( as discussed above).
Neither Purushothaman nor Keller appear to disclose the first, the second and the third back surface layers are removed using backside exposure process.
However, Lee teaches the first, the second and the third back surface layers are removed using backside exposure process ( [0063] the photoresist layer #150 may be exposed by a backside exposure process).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lee with Purushothaman and Keller to implement the first, the second and the third back surface layers are removed using backside exposure process because this can enhance electrical performance and prevent contamination by removing residual photoresist, polymers, or other films that may have migrated to the backside during front-side processing.
Claims 15 and 20 are rejected under U.S.C. 103 as being unpatentable over Purushothaman et al.; US 2010/0078770 A1; 09/2008 in view of Keller et al.; US 2024/0063340 A1; 09/2010 with regard to claims 10 and 16 and further in view of Kuo et al.; US 2015/0001593 A1; 06/2013
Claim 15: Purushothaman and Keller disclose the wafer bonding method of claim 10 ( as discussed above).
Neither Purushothaman nor Keller appear to disclose the first, the second and the third etch stop layers are removed using hydrogen fluoride.
However, Kuo teaches the first, the second and the third etch stop layers are removed using hydrogen fluoride ( [0058] Formation of the source recesses #1302a and the drain recesses #1302b may be performed using one or more etching processes comprising a dry etching process and/or a wet etching process. The etching process may use a wet etchant comprising carbon tetrafluoride, hydrogen fluoride, tetramethylammonium hydroxide, potassium hydroxide, ethylene diamine pyrocatechol, etc. ) .
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kuo with Purushothaman and Keller to implement the first, the second and the third etch stop layers are removed using hydrogen fluoride because hydrogen fluoride is used to remove etch stop layers, typically made of silicon dioxide due to its high selectivity.
Claim 20: Purushothaman and Keller disclose the wafer bonding method of claim 16 ( as discussed above).
Neither Purushothaman nor Keller appear to disclose the first, the second and the third etch stop layers are removed using hydrogen fluoride.
However, Kuo teaches the first, the second and the third etch stop layers are removed using hydrogen fluoride ( [0058] Formation of the source recesses #1302a and the drain recesses #1302b may be performed using one or more etching processes comprising a dry etching process and/or a wet etching process. The etching process may use a wet etchant comprising carbon tetrafluoride, hydrogen fluoride, tetramethylammonium hydroxide, potassium hydroxide, ethylene diamine pyrocatechol, etc. ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kuo with Purushothaman and Keller to implement the first, the second and the third etch stop layers are removed using hydrogen fluoride because hydrogen fluoride is used to remove etch stop layers, typically made of silicon dioxide due to its high selectivity.
Response to Amendment/Arguments
Applicant’s arguments, see pages 1-4 of remarks, filed 02/06/2026, with respect to the rejection of claim 1 under 35 USC 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Trickett.
Applicant's arguments, see pages 4-5 of remarks, filed 02/06/2026, with respect to the rejection of claim 10 under 35 USC 103 have been fully considered but they are not persuasive. Applicant mentions Kellerman in the remarks but the rejection lists Purushothaman. A new ground of rejection is made in view of Liu.
Applicant’s arguments, see pages 4-5 of remarks, filed 02/06/2026, with respect to the rejection of claim 16 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Trickett and Liu.
Applicant’s arguments, see pages 5-6 of remarks, filed 02/06/2026, with respect to the rejection of claim 8 under 35 USC 103 have been fully considered but they are not persuasive. Purushothaman discloses the first, the second and the third back surface layers while Lee teaches a backside exposure process.
Applicant’s arguments, see page 6 of remarks, filed 02/06/2026, with respect to the rejection of claim 9 under 35 USC 103 have been fully considered but they are not persuasive. Purushothaman discloses the first, the second and the third back surface layers while Kuo teaches using hydrogen fluoride.
Applicant’s arguments, see pages 6-7 of remarks, filed 02/06/2026, with respect to the rejection of claims 14 and 19 under 35 USC 103 have been fully considered but they are not persuasive. Purushothaman discloses the first, the second and the third back surface layers while Lee teaches a backside exposure process.
Applicant’s arguments, see page 7 of remarks, filed 02/06/2026, with respect to the rejection of claims 15 and 20 under 35 USC 103 have been fully considered but they are not persuasive. Purushothaman discloses the first, the second and the third back surface layers while Kuo teaches using hydrogen fluoride.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817