DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on July 31, 2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 9, 2023, May 1, 2024 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Semiconductor Devices With Horizontal Conductive Layers Comprising Seams and Data Storage Systems Including The Same.
Election/Restrictions
Applicant’s election of species 3 (Fig. 5B) in the reply filed on January 30, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7, 11, 14, and 19 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Han (US 2021/0384217).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Claim 1, Han discloses (see annotated Fig. 7 below and 2B) a semiconductor device, comprising: a source structure (101/104/105, substrate/first conductive pattern/second conductive pattern may function as common source, Para [0046]) including a plate layer (101 is considered plate layer as it holds 104 and 105) and first (104) and second horizontal conductive layers (105) stacked in order on the plate layer (104 and 105 are stacked in order on 101); gate electrodes (130, gate electrodes, Para [0023]) stacked and spaced apart from each other (130s are stacked and spaced apart from each other in Z-direction) in a first direction (Z-direction) perpendicular to an upper surface of the source structure (Z-direction is perpendicular to an upper surface of 101/104/105); a channel structure (CH, channel structures, Para [0023]) penetrating through the gate electrodes (CH penetrated 130 in Z-direction), extending in the first direction (Z-direction), and including a channel layer (labeled in Fig. 2B, 140, channel layer, Para [0023]) in contact with the first horizontal conductive layer (140 is in contact with 104); and a separation region (SR, separation regions, Para [0023]) penetrating through the gate electrodes (SR penetrates 130) and extending in the first direction (SR extends in Z-direction and X-direction) and in a second direction (X-direction) perpendicular to the first direction (X-direction is perpendicular to Z-direction), wherein the first horizontal conductive layer extends horizontally below the separation region (104 extends horizontally below SR) and has a seam (under broadest reasonable interpretation (BRI) seam is considered opening between two portions of 104) overlapping the separation region in the first direction (seam overlaps SR in Z-direction).
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Claim 7, Han discloses (see annotated Fig. 7 above and 2B) the semiconductor device as claimed in claim 1, wherein the second horizontal conductive layer (105) has an opening (opening in 105, hereinafter “opening”) overlapping the separation region in the first direction (opening overlaps SR in Z-direction). Claim 11, Han discloses (see annotated Fig. 7 above and 2B) the semiconductor device as claimed in claim 1, wherein, in the first horizontal conductive layer (104), the seam has a first length in the first direction (vertical length in Z-direction) and has a second length (horizontal length in X-direction) greater than the first length in a horizontal direction (X-direction) perpendicular to the first direction (since seam is a rectangular it would have larger horizontal length than vertical length). Claim 14, Han discloses (see annotated Fig. 7 above and 2B) the semiconductor device as claimed in claim 1, further comprising: a peripheral circuit structure (PERI, peripheral circuit region, Para [0063]) below the source structure (PERI is below 101/104/105) and including a substrate (201, base substrate, Para [0064]) and circuit devices (220, circuit elements, Para [0064]) on the substrate (220 is on 201). Claim 19, Han discloses (see annotated Fig. 7 below and 2B) a data storage system, comprising: a semiconductor storage device (100h, semiconductor device, Para [0068]) including a substrate (201, base substrate, Para [0065]), circuit devices (220, circuit elements, Para [0066]) on the substrate (220 on 201), lower interconnection lines (280, circuit wiring lines, Para [0064]) on the circuit devices (280 on 220), and input/output pads (280 has lateral pads, hereinafter ”i/o”) electrically connected to the circuit devices (i/o are connected to 220); and a controller (270, circuit contact plugs, Para [0067]) electrically connected to the semiconductor storage device (270 controls 220 which is then connected to CELL of 100h, Para [0067] – [0068]) through the input/output pads and configured to control the semiconductor storage device (270 is connected through i/o and can control 100h), wherein the semiconductor storage device (100h) further includes: a source structure (101/104/105, substrate/first conductive pattern/second conductive pattern may function as common source, Para [0046]) including a plate layer (101 is considered plate layer as it holds 104 and 105) and a horizontal conductive layer (104) on the plate layer (104 is on 101); gate electrodes (130, gate electrodes, Para [0023]) stacked and spaced apart from each other (130s are stacked and spaced apart from each other in Z-direction) in a first direction (Z-direction) perpendicular to an upper surface of the source structure (Z-direction is perpendicular to an upper surface of 101/104/105); a channel structure (CH, channel structures, Para [0023]) penetrating through the gate electrodes (CH penetrated 130 in Z-direction), extending in the first direction (Z-direction), and including a channel layer (labeled in Fig. 2B, 140, channel layer, Para [0023]) in contact with the horizontal conductive layer (140 is in contact with 104); and a separation region (SR, separation regions, Para [0023]) penetrating through the gate electrodes (CH penetrated 130 in Z-direction) and extending in the first direction and in (SR extends in Z-direction and X-direction) a second direction (X-direction) perpendicular to the first direction (X-direction is perpendicular to Z-direction), and wherein the horizontal conductive layer extends horizontally below the separation region (104 extends horizontally below SR) to overlap the separation region in the first direction (seam of 104 overlaps SR in Z-direction).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 15-18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jung (US 2019/0333931).
Claim 15, Jung discloses (Fig. 3) a semiconductor device, comprising: a source structure (SC, source structure, Para [0040]) including a plate layer (SCP1, first source conductive pattern considered plate as it holds SCP2, Para [0040]) and a horizontal conductive layer (SCP2, second source conductive pattern, Para [0040]) on the plate layer (SCP2 is on SCP1); gate electrodes (EGE/GGE/CGE/SGE, electrodes, Para [0044], hereinafter “gate”) stacked and spaced apart from each other in (each gate is stacked and spaced apart from each other in d1) a first direction (vertical direction, hereinafter “d1”) perpendicular to an upper surface of the source structure (d1 is perpendicular to upper surface of SC); a channel structure (DSP/VS, data storage pattern/vertical semiconductor patterns, Para [0049]) penetrating through the gate electrodes (DSP/VS penetrates gate) , extending in the first direction (DSP/VS extends in d1), and including a channel layer (VS) in contact with the horizontal conductive layer (VS is in electrical contact with SCP2 through SCP1); and a separation region (opening where CPLG/SS formed, hereinafter “SR”) penetrating through the gate electrodes and extending in the first direction (SR penetrates gate and extends in d1 and d2) and in a second direction (horizontal direction, hereinafter “d2”) perpendicular to the first direction (d2 is perpendicular to d1), and wherein the horizontal conductive layer (SCP2) has a lower protrusion (vertical protrusion of SCP2 protruding through SCP1, hereinafter “pro”) overlapping the separation region in the first direction (pro overlaps SR in d1) and protruding into the plate layer from a lower surface of the horizontal conductive layer (pro protrudes into SCP1 from a lower surface of SCP2). Claim 16, Jung discloses (Fig. 3) the semiconductor device as claimed in claim 15, wherein a portion of an upper surface of the horizontal conductive layer (portion of upper surface of SCP2 overlapping pro, hereinafter “portion”) overlapping the lower protrusion in the first direction (d1) is in contact with a lower surface of the separation region (portion can be considered in contact with a lower surface of SR as SCP2 extends to lower surface of SR). Claim 17, Jung discloses (Fig. 3) the semiconductor device as claimed in claim 15, wherein the horizontal conductive layer (SCP2) extends horizontally below the separation region (SCP2 extends horizontally below SR). Claim 18, Jung discloses (Fig. 3) the semiconductor device as claimed in claim 15, wherein the horizontal conductive layer (SCP2) has a seam (portion of SCP2 which has an opening considered seam, hereinafter “seam”) overlapping the separation region in the first direction (seam overlaps SR in d1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Han (US 2021/0384217) as applied to claim 7 above, and further in view of Zhang (US 2021/0159248).
Claim 9, Han discloses the semiconductor device as claimed in claim 7. Han does not explicitly disclose wherein a width of the opening ranges from about 60 nm to about 100 nm.
However, Zhang discloses (Fig. 9) a width (width of 79) of an opening (79, backside trench, Para [0092]) ranges from about 60 nm to about 100 nm (distance of trench can be from 20 nm to 100 nm). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the width ranges of Zhang as it allows for control of whether semiconductor channel sidewalls will be physically exposed to source layers (Zhang, Para [0092])
Allowable Subject Matter
Claims 2-6, 8, 10, 12-13, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Han (US 2021/0384217), Jung (US 2019/0333931), Zhang (US 2021/0159248), Lee (US 2019/0326315), Hada (US Pat. No. 10,224,340), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 2 (from which claims 3-5 depend), wherein the first horizontal conductive layer has a lower protrusion overlapping the separation region in the first direction, extending from a lower surface of the first horizontal conductive layer, and protruding into the plate layer.
Regarding Claim 6, wherein the first horizontal conductive layer has an upper curved portion on an upper surface thereof and the upper curved portion is curved downwardly toward the plate layer.
Regarding Claim 8, wherein the separation region has a first width on the opening of the second horizontal conductive layer in a third direction perpendicular to the first and second directions and has a second width smaller than the first width within the opening in the third direction.
Regarding Claim 10, wherein the separation region is bent along an end of the second horizontal conductive layer.
Regarding Claim 12 (from which claim 13 depends), a source insulating layer extending along a circumference of the seam and exposed through an upper surface of the first horizontal conductive layer.
Regarding Claim 20, the second level being above the first level in a vertical direction, and a lower end in a third region between the first region and the second region is on a third level, the third level being above the second level in
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 2019/0326315) discloses (Fig. 6A) a source layer SCP1 with a seam portion 342, but Lee does not disclose a plate underneath the source layer.
Hada (US Pat. No. 10,224,340) discloses (Fig. 14) a separation region 79 with insulating layer 46L but Hada does not disclose a source layer 38 overlapping the separation region 79.
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/G.G.R/ Examiner, Art Unit 2812
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