DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Status of the application
This office Action is in response to Applicant's Application filled on 02/12/2026. Claims 1-19 are pending for this examination.
Priority
Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C. 119(a)-(d). The certified copy has been filed on 08/10/2023.
Oath/Declaration
The oath or declaration filed on 06/09/2023 is acceptable.
Election/Restrictions
Applicant’s remarks,” provisionally elects Species MI, Figure 1A. Claims 1-9 and 18 read on the elected species. Further, claims 10-16 and 19 are dependent from claim 1. Therefore, if claim 1 is allowed, claims 10-16 and 19 should be rejoined and likewise allowed”, in the “Response to Election / Restriction Filed” filed on 02/12/2026 is acknowledged.
Applicant arguments regarding restriction between Species M. I and M. II (Figures lA and 1C) and Species M.III and M.IV (Figures 2A and 2C) found persuasive. Therefore, restriction between Species M. I and M. II (Figures lA and 1C) and Species M.III and M.IV is withdrawn.
This office action considers claims 1-19 are thus pending for prosecution, of which, claims 10-18 and 20 are withdrawn, and claims 1-9 and 19 are examined on their merits.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “wherein the gate insulating film, the at least one hole blocking layer, and the at least one oxide semiconductor layer are partly arranged side by side in a horizontal direction in plan view” Claim 5, lines 1-3, must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 19 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Claim 19, The instant claims recite limitation “a p-type layer, wherein the at least one hole blocking layer is an n-type hole blocking layer, the at least one oxide semiconductor layer comprises a p-type oxide layer and an n-type oxide layer, the n-type hole blocking layer is in contact with the gate insulating film” is not clear because at least one oxide semiconductor layer both of a p-type oxide layer and an n-type oxide layer is not defined. Therefore, the resulting claim is indefinite and is failing to particularly point out and distinctly claim the subject matter. Appropriate corrections defining these limitations within metes and bounds of the claimed invention are required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 3-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ji et al (US 2014/0291669 A1; hereafter Ji).
PNG
media_image1.png
370
517
media_image1.png
Greyscale
Regarding claim 1. Ji discloses a semiconductor device comprising:
a gate insulating film (Fig 1, insulating film 162A, Para [ 0081]);
at least one hole blocking layer (Fig 1, second active layer 150A, made with same oxide material, construed as hole blocking layer, Para [ 0072,0075]) placed in contact with the gate insulating film (Fig 1, insulating film 162A, Para [ 0081]); and
at least one oxide semiconductor layer (Fig 1,first active layer 140A, made with oxide material, Para [ 0066]) placed in contact with the at least one hole blocking layer (Fig 1,second active layer 150A, made with oxide material, Para [ 0072]), wherein the at least one hole blocking layer (second active layer 150A, made with oxide material) is located between the gate insulating film (Fig 1, 162A) and the at least one oxide semiconductor layer (Fig 1, first active layer 140A, made with oxide material).
Regarding claim 3. Ji discloses the semiconductor device according to claim 1, Ji further discloses wherein the band gap of the at least one hole blocking layer and the band gap of the at least one oxide semiconductor layer are different (Fig 1, based on the different material).
Regarding claim 4. Ji discloses the semiconductor device according to claim 1, Ji further discloses wherein the at least one hole blocking layer is an oxide layer (Fig 1, second active layer 150A, made with oxide material, Para [ 0072]).
Regarding claim 5. Ji discloses the semiconductor device according to claim 1, Ji further discloses wherein the gate insulating film (Fig 1, 162A, at least a portion), the at least one hole blocking layer (Fig 1, second active layer 150A, made with oxide material, Para [ 0072]), and the at least one oxide semiconductor layer (Fig 1, first active layer 140A, made with oxide material, Para [ 0066]) are partly arranged side by side in a horizontal direction in plan view (1A).
Claims 2 and 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al (US 2014/0291669 A1; hereafter Ji) as applied claims above and further in view of Han et al (US 2016/0315104 A1; hereafter Han).
Regarding claim 2. Ji discloses the semiconductor device according to claim 1, But, Lee does not disclose explicitly wherein the at least one hole blocking layer has a first conductivity type and the at least one oxide semiconductor layer has a second conductivity type that differs from the first conductivity type.
In a similar field of endeavor, Han discloses wherein the at least one hole blocking layer has a first conductivity type (Para [0052, 0054]) and the at least one oxide semiconductor layer has a second conductivity type that differs from the first conductivity type (Para [0052, 0054]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ji in light of Han teaching “wherein the at least one hole blocking layer has a first conductivity type (Para [0052, 0054]) and the at least one oxide semiconductor layer has a second conductivity type that differs from the first conductivity type (Para [0052, 0054])” for further advantage such as reducing the space of the circuit arrangement in condition of ensuring the circuit function to increase the aperture ratio of the display panel and satisfying the demands of the narrow frame and high resolution to the display panel.
Regarding claim 6. Ji and Han disclose the semiconductor device according to claim 2, Han further discloses wherein the at least one hole blocking layer has n-type conductivity (Para [0052, 0054]) and the at least one oxide semiconductor layer has p-type conductivity (Para [0052, 0054]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ji in light of Han teaching “wherein the at least one hole blocking layer has n-type conductivity (Para [0052, 0054]) and the at least one oxide semiconductor layer has p-type conductivity (Para [0052, 0054])” for further advantage such as reducing the space of the circuit arrangement in condition of ensuring the circuit function to increase the aperture ratio of the display panel and satisfying the demands of the narrow frame and high resolution to the display panel.
Regarding claim 7. Ji and Han disclose the semiconductor device according to claim 6, Ji further disclose wherein the at least one oxide semiconductor layer (first active layer 140A, made with oxide material, Para [ 0066]) contains at least one metal selected from gallium, iridium, nickel, rhodium, and chromium (Para [ 0057-0058]).
Regarding claim 8. Ji and Han disclose the semiconductor device according to claim 6, Ji further disclose wherein an interface between the at least one oxide semiconductor layer (second active layer 150A, made with oxide material, Para [ 0072,0075]) and the at least one hole blocking layer forms a barrier (intermediate region, barrier layer 152A) that prevents injection of holes (Para [ 0074-0075]) from the at least one oxide semiconductor layer (first active layer 140A, made with oxide material, Para [ 0066]).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ji et al (US 2014/0291669 A1; hereafter Ji) and Han et al (US 2016/0315104 A1; hereafter Han) as applied claims above and further in view of YAMAZAKI (US 2014/0110706 A1; hereafter YAMAZAKI).
Regarding claim 9. Ji and Han disclose the semiconductor device according to claim 6, But, Ji and Han do not disclose explicitly wherein a barrier height to holes at the interface between the at least one oxide semiconductor layer and the at least one hole blocking layer is 1.0eV or more.
In a similar field of endeavor, YAMAZAKI discloses wherein a barrier height to holes at the interface between the at least one oxide semiconductor layer and the at least one hole blocking layer is 1.0eV or more (Para [0073]).
Therefore, it would have been obvious to one of the ordinary skilled in the art before the effective filing date of the invention to combine Ji and Han in light of YAMAZAKI teaching “wherein a barrier height to holes at the interface between the at least one oxide semiconductor layer and the at least one hole blocking layer is 1.0eV or more (Para [0073])” for further advantage such as providing effective in reduction of power consumption.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOIN M RAHMAN whose telephone number is (571)272-5002. The examiner can normally be reached 8:30-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOIN M RAHMAN/Primary Examiner, Art Unit 2898
Prosecution Insights