Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
The requirement for election of species mailed 8/18/2025 is WITHDRAWN.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1- are rejected under 35 U.S.C. 102(a)(2) as being anticipated by U.S. Pat. Pub. No. 20220399369 to Son et al. (Son).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding Claim 1, Son teaches in Fig. 7 at least, a semiconductor device, comprising:
a first gate stack structure (above 125) including a first dielectric pattern 120 and a first conductive pattern 130 that are alternately stacked with each other;
a memory channel structure CH including a first memory portion that penetrates the first gate stack structure;
a through contact 170 including a first through portion at a level the same as a level of the first memory portion; and
a connection contact 175 including a first connection portion at a level the same as the level of the first memory portion and the level of the first through portion,
wherein a minimum width of the first memory portion is less than a minimum width of the first through portion and a minimum width of the first connection portion (see Fig. 17, minimum widths of CH are clearly less than 170 or 175).
Regarding Claim 2, Son teaches the semiconductor device as claimed in claim 1, wherein a width of the first memory portion decreases as the level of the first memory portion becomes lower (see Fig. 7).
Regarding Claim 4, Son teaches the semiconductor device as claimed in claim 1, further comprising a second gate stack structure (below 125) below the first gate stack structure, the second gate stack structure including a second dielectric pattern and a second conductive pattern that are alternately stacked with each other, wherein a level of each of the first memory portion, the first through portion, and the first connection portion is higher than a level of the second gate stack structure (see Fig. 7).
Regarding Claim 5, Son teaches the semiconductor device as claimed in claim 4, wherein:
the memory channel structure further includes a second memory portion (below 125) that penetrates the second gate stack structure, the through contact further includes a second through portion (below 125) at a level the same as a level of the second memory portion, the connection contact further includes a second connection portion (below 125) at a level that is the same as the level of the second memory portion and the level of the second through portion, and a minimum width of the second memory portion is less than a minimum width of the second through portion and a minimum width of the second connection portion (see Fig. 7).
Regarding Claim 6, Son teaches the semiconductor device as claimed in claim 5, wherein the second memory portion and the second through portion penetrate the second gate stack structure (see Fig. 7).
Regarding Claim 7, Son teaches the semiconductor device as claimed in claim 4, wherein the first dielectric pattern includes a connection dielectric pattern 125 connected to the second gate stack structure, wherein the connection dielectric pattern includes a connection dielectric curved surface in contact with the first through portion of the through contact (surface of 125 contacting 170 is considered a curved surface).
Regarding Claim 9, Son teaches the semiconductor device as claimed in claim 7, wherein the first through portion includes a through curved surface in contact with the connection dielectric curved surface (surfaces of both the through portion and connection dielectric are curved when viewed from plan).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Son.
Regarding Claim 3, Son teaches the semiconductor device as claimed in claim 1, but does not explicitly teach that a difference between the minimum width of the first memory portion and the minimum width of the first through portion is in a range equal to or greater than about 80 nm. However, where the only difference between the prior art and the claims is a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device is not patentably distinct from the prior art device (MPEP 2144.04(IV)(A). In this case, nothing on the record suggests the claimed device would operate differently from the prior art device.
Allowable Subject Matter
Claim 8 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the cited prior art does not teach that the connection dielectric curved surface is convex toward the through contact.
Claims 10-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 10, Son teaches a semiconductor device, comprising:
a first gate stack structure above 125 including a first dielectric pattern 120 and a first conductive pattern 130 that are alternately stacked with each other;
a second gate stack structure below 125 below the first gate stack structure, the second gate stack structure including a second dielectric pattern 120 and a second conductive pattern 130 that are alternately stacked with each other;
a memory channel structure CH including a first memory portion above 125 that penetrates the first gate stack structure and a second memory portion below 125 that penetrates the second gate stack structure; and
a through contact 170 including a first through portion at a level the same as a level of the first memory portion and a second through portion at a level the same as a level of the second memory portion, but does not teach that the first through portion includes a first through curved surface connected to the second through portion, and wherein a distance between facing segments of the first through curved surface increases as a level of the first through curved surface becomes lower.
Regarding Claim 19, Son teaches an electronic system, comprising:
a main board 2100;
a semiconductor device 3210 on the main board; and
a controller 2002 on the main board and electrically connected to the semiconductor device, wherein the semiconductor device includes:
a first gate stack structure including a first dielectric pattern and a first conductive pattern that are alternately stacked with each other;
a memory channel structure including a first memory portion that penetrates the first gate stack structure;
a through contact including a first through portion at a level the same as a level of the first memory portion;
a connection contact including a first connection portion at a level the same as the level of the first memory portion and the level of the first through portion (see above rejection of Claim 1); but does not teach
a support structure including a first support portion at a level the same as the level of the first through portion and the level of the first connection portion, wherein a minimum width of the first memory portion is less than a minimum width of the first through portion, a minimum width of the first connection portion, and a minimum width of the first support portion, wherein a level of an uppermost portion of the memory channel structure is lower than a level of an uppermost portion of the support structure, and wherein the level of the uppermost portion of the support structure is lower than a level of an uppermost portion of the through contact and a level of an uppermost portion of the connection contact.
Claims 11-18 and 19 are allowable as being dependent on an allowable base claim.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EVREN SEVEN whose telephone number is (571)270-5666. The examiner can normally be reached Mon-Fri 8:00- 5:00 Pacific.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EVREN SEVEN/Primary Examiner, Art Unit 2812