DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species D in the reply filed on 1/15/2026 is acknowledged.
Claims 2-7, 10, 12-17, 19-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/15/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 8-9, 11, 18-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Qin et al (US 2023/0029972; hereinafter Qin).
Regarding claim 1, Figs 1-2 of Qin discloses a display panel comprising a plurality of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) arranged in an array (Figs 1-2) and each of the light-emitting chips comprising an N pole (negative electrode; Figs 1-2; ¶ [0072]-[0074]) and a P pole (positive electrode; Figs 1-2; ¶ [0072]-[0074]),
wherein the light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) in a same column (First column; Fig 2) are arranged to share a common N pole (negative electrode; Figs 1-2; ¶ [0072]-[0074]) or a common P pole;
at least one column of the light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) are arranged in a first light-emitting area (¶ [0072] discloses the light-emitting portion includes n×m light-emitting unit groups distributed in the form of a matrix; Therefore there are more than one light emitting areas);
at least one column of the light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) are arranged in a second light-emitting area (¶ [0072] discloses the light-emitting portion includes n×m light-emitting unit groups distributed in the form of a matrix; Therefore there are more than one light emitting areas) adjacent to the first light-emitting area; and
the light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) in the first light-emitting area and the light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) in the second light-emitting area are mirror-symmetrical (Figs 1-2).
Regarding claim 8, Figs 1-2 of Qin discloses the light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) arranged chips arranged in the first light-emitting area (¶ [0072] discloses the light-emitting portion includes n×m light-emitting unit groups distributed in the form of a matrix; Therefore there are more than one light emitting areas) comprise a first column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) and a fifth column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) adjacent to each other, and the light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) arranged in the second light-emitting area (¶ [0072] discloses the light-emitting portion includes n×m light-emitting unit groups distributed in the form of a matrix; Therefore there are more than one light emitting areas) comprise a second column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) and a sixth column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) adjacent to each other;
an arrangement of P poles (positive electrode; Figs 1-2; ¶ [0072]-[0074]) and N poles (negative electrode; Figs 1-2; ¶ [0072]-[0074]) of the fifth column of light-emitting chips and an arrangement of P poles and N poles of the first column of light-emitting chips are same (Figs 1-2);
an arrangement of P poles and N poles of the second column of light-emitting chips and an arrangement of P poles and N poles of the sixth column of light-emitting chips are same (Figs 1-2);
the fifth column of light-emitting chips and the sixth column of light-emitting chips are mirror-symmetrical (Figs 1-2); and
the first column of light-emitting chips and the second column of light-emitting chips are mirror-symmetrical (Figs 1-2).
Regarding claim 9, Figs 1-2 of Qin discloses a minimum distance between each of the N poles (negative electrode; Figs 1-2; ¶ [0072]-[0074]) of the fifth column of light-emitting chips and each of the P poles (positive electrode; Figs 1-2; ¶ [0072]-[0074]) of the first column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) is less than a minimum distance between each of the N poles of the fifth column of light-emitting chips and each of the N poles of the first column of light emitting chips (Figs 1-2); and
a minimum distance between each of the N poles (negative electrode; Figs 1-2; ¶ [0072]-[0074]) of the second column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) and each of the P poles (positive electrode; Figs 1-2; ¶ [0072]-[0074]) of the sixth column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) is less than a minimum distance between each of the N poles of the second column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) and each of the N poles of the sixth column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]).
Regarding claim 11, Figs 1-2 of Qin discloses a display panel comprising a plurality of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) arranged in an array (Figs 1-2) and each of the light-emitting chips comprising an N pole (negative electrode; Figs 1-2; ¶ [0072]-[0074]) and a P pole (positive electrode; Figs 1-2; ¶ [0072]-[0074]),
wherein the light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) in a same column (First column; Fig 2) are arranged to share a common N pole (negative electrode; Figs 1-2; ¶ [0072]-[0074]) or a common P pole;
at least one column of the light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) are arranged in a first light-emitting area (¶ [0072] discloses the light-emitting portion includes n×m light-emitting unit groups distributed in the form of a matrix; Therefore there are more than one light emitting areas);
at least one column of the light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) are arranged in a second light-emitting area (¶ [0072] discloses the light-emitting portion includes n×m light-emitting unit groups distributed in the form of a matrix; Therefore there are more than one light emitting areas) adjacent to the first light-emitting area; and
the light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) in the first light-emitting area and the light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) in the second light-emitting area are mirror-symmetrical (Figs 1-2).
Regarding claim 18, Figs 1-2 of Qin discloses the light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) arranged chips arranged in the first light-emitting area (¶ [0072] discloses the light-emitting portion includes n×m light-emitting unit groups distributed in the form of a matrix; Therefore there are more than one light emitting areas) comprise a first column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) and a fifth column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) adjacent to each other, and the light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) arranged in the second light-emitting area (¶ [0072] discloses the light-emitting portion includes n×m light-emitting unit groups distributed in the form of a matrix; Therefore there are more than one light emitting areas) comprise a second column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) and a sixth column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) adjacent to each other;
an arrangement of P poles (positive electrode; Figs 1-2; ¶ [0072]-[0074]) and N poles (negative electrode; Figs 1-2; ¶ [0072]-[0074]) of the fifth column of light-emitting chips and an arrangement of P poles and N poles of the first column of light-emitting chips are same (Figs 1-2);
an arrangement of P poles and N poles of the second column of light-emitting chips and an arrangement of P poles and N poles of the sixth column of light-emitting chips are same (Figs 1-2);
the fifth column of light-emitting chips and the sixth column of light-emitting chips are mirror-symmetrical (Figs 1-2); and
the first column of light-emitting chips and the second column of light-emitting chips are mirror-symmetrical (Figs 1-2).
Regarding claim 19, Figs 1-2 of Qin discloses a minimum distance between each of the N poles (negative electrode; Figs 1-2; ¶ [0072]-[0074]) of the fifth column of light-emitting chips and each of the P poles (positive electrode; Figs 1-2; ¶ [0072]-[0074]) of the first column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) is less than a minimum distance between each of the N poles of the fifth column of light-emitting chips and each of the N poles of the first column of light emitting chips (Figs 1-2); and
a minimum distance between each of the N poles (negative electrode; Figs 1-2; ¶ [0072]-[0074]) of the second column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) and each of the P poles (positive electrode; Figs 1-2; ¶ [0072]-[0074]) of the sixth column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) is less than a minimum distance between each of the N poles of the second column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]) and each of the N poles of the sixth column of light-emitting chips (B1/G1/R1; Fig 1; ¶ [0072]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Wang et al (US 2024/0047469; This prior art discloses a display panel comprising plurality of light emitting chips)
Tsai et al (US 2023/0238390; This prior art discloses a display panel comprising plurality of light emitting chips)
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/RATISHA MEHTA/Primary Examiner, Art Unit 2817