DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/23/2026. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (2021/0074914 as disclosed in previous Office Action) in view of Lee (US 2022/0077182).
As for claims 1 and 12, Lee et al. disclose in Figs. 1-3 and the related text a semiconductor memory device, comprising:
a peripheral circuit structure 207; and
a cell structure 503 stacked on a top surface of the peripheral circuit structure (Fig. 12C), wherein the cell structure includes:
a cell substrate 315 including a first (lower) face facing the peripheral circuit structure and a second (upper) face opposite the first face;
a first mold stack 318 including a plurality of first gate electrodes 324 sequentially stacked on the first face (Fig. 12C);
a channel hole (where 333 formed in) extending through the plurality of first gate electrodes (Fig. 12C); and
a channel structure 333 including a gate dielectric film 336, a semiconductor film 338, and a variable resistance film 346 sequentially stacked in the channel hole, wherein the semiconductor film 338 includes:
a sidewall portion intersecting the first face and the plurality of first gate electrodes (Fig. 12C); and
a top plate (upper) portion extending from the sidewall portion in the cell substrate in a parallel manner to the first face,
wherein the sidewall portion of the semiconductor film 338 extends linearly through the cell substrate and the first mold stack (Fig. 12C), and
wherein the top plate (upper) portion of the semiconductor film 338 is exposed through the gate dielectric film 336 and is connected to the cell substrate 315 (Fig. 12C),
wherein the gate dielectric film 336 extending along an outer side surface of the semiconductor film 338 and between the semiconductor film 338 and the plurality of gate electrodes 324;
wherein the variable resistance film 346 extending along an inner side surface of the semiconductor film 338,
wherein the gate dielectric film 336 does not extend along a (upper) surface of the semiconductor film 338 parallel to the first face (Fig. 12C),
wherein the channel structure further includes a filling insulating film 355 in the channel hole and the variable resistance film 346 is disposed between the filling insulating film 355 and the semiconductor film 336 (Fig. 12C), or wherein the filling insulating filling a space defined by an inner side surface of the variable resistance film 346, wherein the variable resistance film is disposed between the filling insulating film and the semiconductor film (Fig. 12C).
Lee et al. do not disclose a topmost surface of the filling insulating film is higher than a topmost surface of the gate dielectric film relative to the top surface of the peripheral circuit structure.
Lee teaches in Fig. 1-3 and the related text a topmost surface of the filling insulating film CO is higher than a topmost surface of the gate dielectric film BI relative to the top surface of the peripheral circuit structure 50 (Fig. 3A).
Lee et al. and Lee are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee because they are from the same field of endeavor.
It would have been obvious to one of ordinary skills in the art at the time the invention was made to modify Lee et al. to include the limitations as taught by Lee in order to improve performance of the device.
As for claim 2, Lee et al. disclose the semiconductor memory device as claimed in claim 1, wherein each of the gate dielectric film 336, the semiconductor film 338, and the variable resistance film 346 conformally extends along a profile of the channel hole (Fig. 12C).
As for claim 3, Lee et al. disclose the semiconductor memory device as claimed in claim 1, wherein the cell substrate 315 includes poly-Si doped with N-type impurities [0160].
As for claim 4, Lee et al. disclose the semiconductor memory device as claimed in claim 1, wherein the variable resistance film 346 includes a transition metal oxide ([0059] and [0165]).
As for claim 6, Lee et al. disclose the semiconductor memory device as claimed in claim 1, wherein the topmost surface of the filling insulating film 355 is higher than the first face of the cell substrate relative to the top surface of the peripheral circuit structure (Fig. 12C).
As for claim 8, Lee et al. disclose the semiconductor memory device as claimed in claim 1, further comprising an input/output wiring structure 476/479 on the second face and electrically connected to the cell substrate 315 (Fig. 12C).
As for claim 9, Lee et al. disclose the semiconductor memory device as claimed in claim 1, wherein the cell structure further includes a conductive plate 479 extending along the second face (Fig. 12C).
As for claim 15, Lee et al. disclose the semiconductor memory device as claimed in claim 12, wherein a vertical level of a topmost surface of the gate dielectric film 336 is higher than a vertical level of the first face (Fig. 12C).
As for claim 16, Lee et al. in view of Lee disclosed the semiconductor memory device as claimed in claim 12, Lee further teaches wherein a vertical level of the topmost surface of the gate dielectric film BI is lower than a vertical level of the first face (lower surface of 181) (Fig. 3A).
As for claim 17, Lee et al. disclose the semiconductor memory device as claimed in claim 16, wherein the cell substrate 315 includes a protrusion protruding from the first face toward the gate dielectric film (Fig. 12C).
As for claim 18, Lee et al. disclose the semiconductor memory device as claimed in claim 12, wherein: the semiconductor film 338 has a cup shape (Fig. 12C), and the cell structure further includes a filling insulating film 355 filling an inner space defined by the variable resistance film 346 (Fig. 12C).
As for claim 19, Lee et al. disclose the semiconductor memory device as claimed in claim 18, wherein the filling insulating film 355 extends through the variable resistance film 346 (Fig. 12C).
As for claim 20, Lee et al. disclose the semiconductor memory device as claimed in The semiconductor memory device as claimed in wherein a topmost surface of the filling insulating film 355 is positioned within the cell substrate 315 (Fig. 12C).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Lee and further in view of Jeong et al. (US 2023/0189527 as disclosed in previous Office Action).
As for claims 10-11, Lee et al. disclosed the semiconductor memory device as claimed in claim 1, the semiconductor film has a cup shape.
Lee et al. do not disclose the cell structure further includes a second mold stack including a plurality of second gate electrodes sequentially stacked between the peripheral circuit structure 6and the first mold stack, and the channel hole extends through the plurality of first gate electrodes and the plurality of second gate electrodes; wherein the channel hole has a step between the first mold stack and the second mold stack.
Jeong et al. teach in Fig. 1-3 and the related text a cell structure further includes a second mold stack S1/S2 including a plurality of second gate electrodes 245 sequentially stacked between the peripheral circuit structure D1 and the first mold stack S2/S1, and the channel hole extends through the plurality of first gate electrodes and the plurality of second gate electrodes (Fig. 3); wherein the channel hole has a step between the first mold stack S2 and the second mold stack S1 (Fig. 3).
Lee et al. and Jeong et al. are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Lee et al. to include the limitations as taught by Jeong et al., in order to expose electric element (Jeong et al. [0006]).
Claim(s) 14 and 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Maejim et al. (US 2021/0118862 as disclosed in previous Office Action).
As for claims 14 and 21, Lee et al. disclose the semiconductor memory device as claimed in claim 12, wherein the cell structure includes: a bit-line 379/376 between the peripheral circuit structure 207 and the semiconductor film 338, the bit-line being connected to the semiconductor film (Fig. 12C);a plurality of source/drain contacts 209/212 between the peripheral circuit structure 207 and the plurality of gate electrodes 324, the plurality of source/drain contacts 209/212 being respectively (electrically) connected to the plurality of gate electrodes 324; and a cell wiring structure 385/390 bonded onto the peripheral circuit structure 207, the cell wiring structure being electrically connected to the bit-line and the plurality of gate contacts.
Lee et al. do not teach wherein a topmost surface of the gate dielectric film is coplanar with the first face; and a plurality of gate contacts between the peripheral circuit structure and the plurality of gate electrodes, the plurality of gate contacts being respectively connected to the plurality of gate electrodes.
Maejima et al. teach in Fig. 23 and the related text a topmost surface of the gate dielectric film 43 is coplanar with the first face (surface of 30); and a plurality of gate contacts C0/CS between the peripheral circuit structure (lower portion) and the plurality of gate electrodes 32, the plurality of gate contacts C0/CS being respectively (electrically) connected to the plurality of gate electrodes 32.
Lee et al. and Maejima et al. are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Lee et al. to include the limitations as taught by Maejima et al., in order to provide interconnections.
As for claim 22, Lee et al. disclose the semiconductor memory device as claimed in claim 21, wherein the peripheral circuit structure includes:
a peripheral circuit substrate 205;
a peripheral circuit element TR on the peripheral circuit substrate; and a peripheral circuit wiring structure 209/212 on the peripheral circuit substrate electrically connecting the cell wiring structure 385/390 and the peripheral circuit element TR (Fig. 12C).
Claim(s) 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. in view of Kim et al. (US 2015/0340370, as disclosed in previous Office Action) and Lee.
As for claim 27 , Lee et al. disclose in Fig. 12C and the related text an electronic system, comprising:
a semiconductor memory device including a peripheral circuit structure 207 and a cell structure 503 stacked on the peripheral circuit structure (Fig. 12C), wherein the cell structure includes:
a cell substrate 315 including a first (lower) face facing the peripheral circuit structure 207 and a second (upper) face opposite to the first face and the first face is closer to the peripheral circuit structure than the second face (Fig. 12C);
a plurality of gate electrodes 324 sequentially stacked on the first face (Fig. 12C);
a semiconductor film 338 intersecting the plurality of gate electrodes 324 and connected to the cell substrate (Fig.12C);
a gate dielectric film 336 extending along an outer side surface of the semiconductor film and between the semiconductor film and the plurality of gate electrodes (Fig. 12C);
a variable resistance film 346 extending along an inner side surface of the semiconductor film 338, wherein the gate dielectric film 336 does not extend along a surface of the semiconductor film 338 parallel to the first face (Fig. 12C).
Lee et al. does not disclose a controller on the main substrate, the controller electrically connected to the semiconductor memory device; and the cell substrate being electrically connected to the controller.
Kim et al. teach in Fig. 1-3 and the related text a controller 1200 on a main substrate (1000, Kim does not clearly show the main substrate, however it is well known in the semiconductor art to include the main substrate to support the devices) the controller 1200 electrically connected to the semiconductor memory device 1100 [0023]; and the cell substrate 101 being electrically connected to the controller (Fig. 1).
Lee teaches in Fig. 1-3 and the related text wherein a topmost surface of the gate dielectric film BI is lower than the first face (lower surface of 181) relative to the second face (Fig. 3A).
Lee et al. and Lee are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee because they are from the same field of endeavor.
Lee et al. and Kim et al. are analogous art because they both are directed memory devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Lee et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify Lee et al. to include the limitations as taught by Kim et al. and Lee in order to control the operation of the semiconductor device (Kim et al.: [0023]) and improve performance of the device.
Response to Arguments
Applicant’s arguments with respect to claim(s) above have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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