Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 13, 2023 was in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Species II (claims 1-4, 6-15 & 17-20) in the reply filed on 11/07/2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 6-7 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nowak et al. (Pub. No.: US 2005/0073005 A1).
Regarding Claim 1, Nowak et al. discloses a structure comprising: at least one fin structure composed of semiconductor material and comprising a channel region between a source region and a drain region (Par. 0005-0016; 0050-0064; Fig. 30 in conjunction with Figs. 16-29 – fin structure 18 composed of semiconductor material; source region and drain region 112; channel region 114 (Fig. 27)); and
PNG
media_image1.png
168
314
media_image1.png
Greyscale
PNG
media_image2.png
328
696
media_image2.png
Greyscale
a gated body under the channel region of the at least one fin structure (Par. 0005-0016; 0050-0064; Fig. 30 in conjunction with Figs. 16-29 – gated body 164 (conductive well region)).
Regarding Claim 2, Nowak et al., as applied to claim 1, discloses the structure, wherein the gated body comprises the semiconductor material (Par. 0054).
Regarding Claim 6, Nowak et al., as applied to claim 1, discloses the structure, wherein the gated body is asymmetrical (Fig. 30 – with respect to the rightmost or leftmost fin 18, the gated body 164 is asymmetrical).
Regarding Claim 7, Nowak et al., as applied to claim 1, discloses the structure, wherein the source region and the drain region comprise epitaxial semiconductor material on the at least one fin structure (Par. 0050; 0060-0062; Fig. 30 in conjunction with Figs. 16-29).
Regarding Claim 20, Nowak et al. discloses a method comprising: forming at least one fin structure composed of semiconductor material and comprising a channel region between a source region and a drain region (Par. 0005-0016; 0050-0064; Fig. 30 in conjunction with Figs. 16-29 – fin structure 18 composed of semiconductor material; source region and drain region 112; channel region 114 (Fig. 27)); and
PNG
media_image1.png
168
314
media_image1.png
Greyscale
PNG
media_image2.png
328
696
media_image2.png
Greyscale
forming a gated body under the channel region of the at least one fin structure (Par. 0005-0016; 0050-0064; Fig. 30 in conjunction with Figs. 16-29 – gated body 164 (conductive well region)).
Claims 1-4, 6-8 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cheng et al. (Pub. No.: US 2014/0117462 A1).
Regarding Claim 1, Cheng et al. discloses a structure comprising: at least one fin structure composed of semiconductor material and comprising a channel region between a source region and a drain region (Par. 0027-0033; Fig. 8 – fin structure comprising upper portion 818 and lower portion 819); and
PNG
media_image3.png
320
466
media_image3.png
Greyscale
a gated body under the channel region of the at least one fin structure (Par. 0025-0033; Fig. 8 –e gated body 814).
Regarding Claim 2, Cheng et al., as applied to claim 1, discloses the structure, wherein the gated body comprises the semiconductor material (Par. 0025-0033).
Regarding Claim 3, Cheng et al., as applied to claim 2, discloses the structure, wherein the semiconductor material of the gated body comprises P+ semiconductor material extending to underneath the channel region (Par. 0027, 0033; Fig. 8 – this prior teaches fin-type nFET and/or pFET; if it is an nFET, the source/drain region is supposed to be n-type and channel p-type; the gated body 814 in this case is also p-doped; now P+ is a relative term and at least under BRI, the p-type gated body 814 could be considered to comprise of P+ semiconductor material).
Regarding Claim 4, Cheng et al., as applied to claim 3, discloses the structure, further comprising a deep N-well and P-well under the gated body (Par. 0027, 0033; Fig. 8 – under BRI, the lower portion of the punch-through stopper layer 814 could be considered as the P-well; and upper part of substrate could be considered to comprise N-well).
Regarding Claim 6, Cheng et al., as applied to claim 1, discloses the structure, wherein the gated body is asymmetrical (Par. 0027, 0033; Fig. 8 – with respect to the rightmost or leftmost fin, the gated body 814 could be considered to be asymmetrical).
Regarding Claim 7, Cheng et al., as applied to claim 1, discloses the structure, wherein the source region and the drain region comprise epitaxial semiconductor material on the at least one fin structure (Par. 0027, 0033; Fig. 8).
Regarding Claim 8, Cheng et al., as applied to claim 7, discloses the structure, further comprising a shallow trench isolation structure above the gated body and surrounding the at least one fin structure (Par. 0027, 0033; Fig. 8 – shallow trench isolation structure 810).
Regarding Claim 20, Cheng et al. discloses a method comprising: forming at least one fin structure composed of semiconductor material and comprising a channel region between a source region and a drain region (Par. 0027-0033; Fig. 8 – fin structure comprising upper portion 818 and lower portion 819); and
PNG
media_image3.png
320
466
media_image3.png
Greyscale
forming a gated body under the channel region of the at least one fin structure (Par. 0025-0033; Fig. 8 –e gated body 814).
Allowable Subject Matter
Claims 12-15 & 17-19 are allowed. The following is an examiner's statement of reasons for allowance:
Regarding Claim 1: The prior art of record to the examiner’s knowledge does not teach or render obvious the instant invention, particularly characterized by a structure comprising: at least one fin structure comprising a channel region of a first type of impurity; a source region and a drain region on opposing ends of the channel region; a gated body comprising semiconductor material with a second impurity type and which extends underneath the channel region; a shallow trench isolation structure above the gated body; and a deep well of the first type of impurity under the gated body.
The most relevant prior art reference due to Cheng et al. (Pub. No.: US 2014/0117462 A1) substantially discloses a structure comprising: at least one fin structure comprising a channel region of a first type of impurity (Par. 0027; Fig. 8 – this prior teaches fin-type nFET and/or pFET; if it is an nFET, the channel is supposed to be p-doped, i.e., doped with first type impurity); a source region and a drain region on opposing ends of the channel region (Par. 0027; Fig. 8); a gated body comprising semiconductor material with a first Par. 0027, 0033; Fig. 8 – this prior teaches fin-type nFET and/or pFET; if it is an nFET, the source/drain region is supposed to be n-type and channel p-type; the gated body 814 in this case is also p-doped; i.e., doped with first type impurity instead of second type impurity); a shallow trench isolation structure above the gated body (Par. 0027, 0033; Fig. 8 – shallow trench isolation structure 810); and a deep well of the first type of impurity under the gated body (Par. 0027, 0033; Fig. 8 – under BRI, the lower portion of the punch-through stopper layer 814 could be considered as the deep well).
Additionally, the prior arts made of record and not relied upon are considered pertinent to applicant's disclosure. See form PTO-892.
However, none of these prior art references indicated above or the prior arts made of record in form PTO-892, disclose all the limitations of claim 12 (the individual limitations may be found in a plurality of prior arts but there is no motivation to combine). Because no reference alone teaches all the limitations, nor is there any motivation to combine the prior arts to construct all the limitations of this independent claim, claim 12 is deemed patentable over the prior arts.
Regarding Claims 13-15 & 17-19: these claims are allowed because of their dependency status from claim 12.
Regarding Claims 9-11: These claims are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Bernard et al. (Pub. No. US 2009/0212330 A1) – This prior art teaches a semiconductor device that includes a semiconductive channel region and a gate region with the gate region has at least one buried part extending under the channel region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SYED I GHEYAS whose telephone number is (571)272-0592. The examiner can normally be reached on Monday-Friday from 8:30 AM - 5:30 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley, can be reached at telephone number (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://portal.uspto.gov/external/portal. Should you have questions about access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
11/29/2025
/SYED I GHEYAS/Primary Examiner, Art Unit 2893