DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of species A, claims 1-5, 7-16 and 19-20 in the reply filed on 9/30/25 is acknowledged.
Claims 6, 17 and 18 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9/30/25.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al., US Publication No. 2014/0091471.
Chen anticipates:
1. A semiconductor package comprising (see figs. 1 and 14):
a redistribution layer comprising (113):
a plurality of conductive lines (e.g. horizontal 114);
a plurality of conductive vias (e.g. vertical 114), each of the plurality of conductive vias being connected to at least one of the plurality of conductive lines; and
a plurality of lower pads 9115), each of the plurality of lower pads being connected to one of the plurality of conductive vias;
a semiconductor chip (120) provided on the redistribution layer;
a plurality of external connection terminals (130) attached to the plurality of lower pads; and
a plurality of electrical paths (e.g. See para. [0036] disclosing the electrical path tested in fig. 14.) configured for testing the plurality of conductive lines and the plurality of conductive vias, each of the plurality of electrical paths comprising at least one of the plurality of conductive lines and at least one of the plurality of conductive vias, and
wherein each of the plurality of electrical paths is connected to at least four external connection test terminals (130) from among the plurality of external connection terminals. See Chen at para. [0001] – [0044], figs. 1-16.
Claim(s) 1-3 and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liu et al., US Publication No. 2012/0305916 A1.
Liu anticipates:
1. A semiconductor package comprising (see fig. 43-44, also see figs. 41 and 45-48):
a redistribution layer (646; 660) comprising:
a plurality of conductive lines (e.g. upper horizontal traces);
a plurality of conductive vias (e.g. vertical vias), each of the plurality of conductive vias being connected to at least one of the plurality of conductive lines; and
a plurality of lower pads (e.g. lower horizontal traces), each of the plurality of lower pads being connected to one of the plurality of conductive vias;
a semiconductor chip (620) provided on the redistribution layer;
a plurality of external connection terminals (624, 626; 652; 662) attached to the plurality of lower pads; and
a plurality of electrical paths (e.g. See electrical paths at para. [0123], para. [0130]) configured for testing the plurality of conductive lines and the plurality of conductive vias, each of the plurality of electrical paths comprising at least one of the plurality of conductive lines and at least one of the plurality of conductive vias, and
wherein each of the plurality of electrical paths is connected to at least four external connection test terminals (624, 626; 652; 662 in figs. 47-48) from among the plurality of external connection terminals. See Liu at para. [0001] – [0138], figs. 1-49.
2. The semiconductor package of claim 1, wherein the external connection test terminals comprise:
at least two first test terminals configured to input a test input signal; and
at least two second test terminals configured to output a test output signal (e.g. “The probe pad 628 of one of the sense BPBs 626 and one of the probe pads 628 of the BPB under test 624 are used to apply a current through the BPB under test 624. The probe pad 628 of the other sense BPBs 626 and the other probe pad 628 of the BPB under test 624 are used to measure a voltage drop across the BPB under test 624.” , para. [0123])
3. The semiconductor package of claim 2, wherein the at least two first test terminals are electrically connected to each other through a lowermost conductive line (e.g. see 632 in figs. 45-48) of the plurality of conductive lines, and
wherein the at least two second test terminals are electrically connected to each other through a lowermost conductive line (e.g. see 632 in figs. 45-48) of the plurality of conductive lines.
5. The semiconductor package of claim 1, wherein the external connection test terminals are provided in a plurality of first areas (e.g. see corner region in figs. 38 and 41), and
wherein each of the plurality of first areas is adjacent to one of a plurality of vertices of the redistribution layer, para. [0119] – [0124].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-16 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., US Publication No. 2014/0091471 in view of Liu et al., US Publication No. 2012/0305916 A1.
Chen teaches:
14. A package-on-package comprising (see figs. 1 and 14):
a first semiconductor package (113/120); and
a second semiconductor package (116/140 or 162/161),
wherein the first semiconductor package comprises:
a first redistribution layer (113) comprising:
a plurality of first conductive lines (e.g. horizontal 114);
a plurality of first conductive vias (e.g. vertical 114), each of the plurality of first conductive vias being connected to at least one of the plurality of first conductive lines; and
a plurality of first lower pads (115), each of the plurality of first lower pads being connected to one of the plurality of first conductive vias;
a first semiconductor chip (120) provided on the first redistribution layer and comprising chip pads (e.g. 132 in fig. 3);
connection structures (111) provided on the first redistribution layer and spaced apart from the first semiconductor chip (120) in a horizontal direction;
a plurality of external connection terminals (130) attached to the plurality of first lower pads (115);
a second redistribution layer (116; 162) provided on the connection structures, the second redistribution layer comprising:
a plurality of second conductive lines (e.g. horizontal 119; horizontal 165);
a plurality of second conductive vias (e.g. 117; vertical 115), each of the plurality of second conductive vias being connected to at least one of the plurality of second conductive lines;
a plurality of second lower pads (e.g. lowest 119; lowest 165), each of the plurality of second lower pads being connected to one of the plurality of second conductive vias, and
a plurality of second upper pads (e.g. topmost 119; topmost 165),
wherein the second semiconductor package (116/140 or 162/161) is provided on the first semiconductor package (113/120),
wherein the second semiconductor package (116/140 or 162/161) comprises:
a second semiconductor chip (140 or 161); and
package connection terminals (141; 164) configured to electrically connect the second semiconductor chip to the second redistribution layer (116; 162);
(see fig. 14) wherein the package-on-package further comprises a plurality of electrical paths (e.g. See para. [0036] disclosing the electrical path tested in fig. 14.) configured for testing (i) the plurality of first lower pads, the plurality of first conductive lines, and the plurality of first conductive vias, or (ii) the plurality of second lower pads, the plurality of second conductive lines, and the plurality of second conductive vias,
wherein each of the plurality of electrical paths comprises at least one of the plurality of first conductive lines (e.g. horizontal 114); and at least one of the plurality of first conductive vias (e.g. vertical 114),
wherein each of the plurality of electrical paths is connected to at least four external connection test terminals (130) from among the plurality of external connection terminals,
wherein the external connection test terminals comprise:
at least two first test terminals (130 input) configured to input a test input signal (e.g. Fig. 14 shows multiple test terminals receiving input); and
second test terminals configured to output a test output signal (e.g. Because the testing is performed to determine the functionality of chip 140, it is inherent or obvious to one of ordinary skill in the art to output an output test signal, para. [0036].)…
wherein the at least two first test terminals (130 input) are electrically connected to each other through a lowermost conductive line (114) of the plurality of first conductive lines, …See Chen at para. [0001] – [0044], figs. 1-16.
Regarding claim 14:
Chen does not expressly teach:
at least two second test terminals configured to output a test output signal,…
wherein the at least two second test terminals are electrically connected to each other through a lowermost conductive line of the plurality of first conductive lines…
wherein the external connection test terminals are provided in a plurality of first areas that are respectively adjacent to a plurality of vertices of the first redistribution layer, or are provided in a second area adjacent to a center of the first semiconductor chip,
In an analogous art, Liu teaches (see figs. 45-46, also see figs. 40 and 42):
wherein the external connection test terminals (624, 626) comprise:
at least two second test terminals (626, sense) configured to output a test output signal (642c, 642d) …
wherein the at least two second test terminals (626, sense) are electrically connected to each other through a lowermost conductive line (632) of the plurality of first conductive lines. See Liu at para. [0121] – [0130].
Liu also teaches “wherein the external connection test terminals comprise at least two first test terminals configured to input a test input signal; wherein the at least two first test terminals are electrically connected to each other through a lowermost conductive line of the plurality of first conductive lines” in the disclosure at para. [0123]: “The probe pad 628 of one of the sense BPBs 626 and one of the probe pads 628 of the BPB under test 624 are used to apply a current through the BPB under test 624. The probe pad 628 of the other sense BPBs 626 and the other probe pad 628 of the BPB under test 624 are used to measure a voltage drop across the BPB under test 624.”
Liu further teaches:
(see figs. 38 and 41) wherein the external connection test terminals (606, 608) are provided in a plurality of first areas (e.g. see corner region) that are respectively adjacent to a plurality of vertices of the first redistribution layer, or are provided in a second area (e.g. see center region) adjacent to a center of the first semiconductor chip (e.g. 604 is die attach area), para. [0119] – [0124].
Regarding claim 15:
Chen further teaches:
the test input signal is output to the at least two second test terminals through:
the plurality of first lower pads (115);
the plurality of first conductive lines (e.g. horizontal 114);
the plurality of first conductive vias (e.g. vertical 114);
the connection structures (111);
the plurality of second conductive lines (e.g. horizontal 119; horizontal 165);
the plurality of second conductive vias (e.g. 117; vertical 115); and
the plurality of second upper pads (e.g. topmost 119; topmost 165), figs. 1 and 14.
Liu further teaches:
wherein the at least two first test terminals and the at least two second test terminals are provided in the first areas (e.g. see corner region in figs. 38 and 41).
Chen further teaches:
16. The package-on-package of claim 15, wherein the plurality of second upper pads (e.g. topmost 119) to which the test input signal is input are electrically connected to the connection structures (111) and in direct contact with the package connection terminals (e.g. 141 of the second semiconductor package), fig. 1
Regarding claim 20
Chen further teaches:
20. The package-on-package of claim 14, wherein the connection structures (111) comprise one of: a through-mold via (TMV); a conductive solder; a conductive pillar; and a conductive bump, fig. 1.
Regarding claim 7:
Chen and Liu teach the limitations as applied to claim 14 above.
Regarding claim 8:
Chen further teaches:
8. The semiconductor package of claim 7, wherein the plurality of electrical paths are not electrically connected to external connection terminals other than the external connection test terminals (e.g. “Typically, the segment under test…will be electrically isolated from or independent of other electrical paths” at para. [0076]. [0080]).
Regarding claims 9 and 10:
Chen and Liu teach the limitations as applied to claim 15 above.
Regarding claim 11:
Chen and Liu teach the limitations as applied to claim 14 above.
Regarding claim 12:
Chen and Liu teach the limitations as applied to claims 14-15 above.
Regarding claim 13:
Chen and Liu teach the limitations as applied to claim 16 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Chen with the teachings of Liu because (i) “Using the applied current and measured voltage drop, the resistance of the BPB under test 624 may be calculated, and whether the BPB under test 624 forms an electrical connection may be determined.” (e.g. Liu at para. [0127]) ; and (ii) The external terminals are located at the corners and along a diagonal to align with the test and sense bumps of the chip (e.g. Liu at para. [0120]).
Claim(s) 2 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, as applied to claim 1 above, in view of Liu et al., US Publication No. 2012/0305916 A1.
Regarding claim 3:
Chen and Liu teach the limitations as applied to claim 14 above.
Regarding claim 5:
Chen and Liu teach the limitations as applied to claims 14 and 15 above.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Chen with the teachings of Liu because (i) “Using the applied current and measured voltage drop, the resistance of the BPB under test 624 may be calculated, and whether the BPB under test 624 forms an electrical connection may be determined.” (e.g. Liu at para. [0127]) ; and (ii) The external terminals are located at the corners and along a diagonal to align with the test and sense bumps of the chip (e.g. Liu at para. [0120]).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen, as applied to claim 1 above, in view of Lu et al., US Publication No. 2022/0271024 A1 (from the IDS).
Regarding claim 4:
Chen teaches all the limitations of claim 1 above, but does not expressly teach:
wherein each of the external connection test terminals is a dummy external connection terminal.
In an analogous art, Lu teaches:
(see fig. 9C) wherein each of the external connection test terminals (130a) is a dummy external connection terminal, para. [0069].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Chen with the teachings of Lu because a dummy external connection terminal enables detection of “poor electrical interconnection, short circuit, crack, delamination”. See Lu at para. [0069].
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu, as applied to claim 1 above, in view of Lu et al., US Publication No. 2022/0271024 A1 (from the IDS).
Regarding claim 4:
Liu teaches all the limitations of claim 1 above, but does not expressly teach:
wherein each of the external connection test terminals is a dummy external connection terminal.
In an analogous art, Lu teaches:
(see fig. 9C) wherein each of the external connection test terminals (130a) is a dummy external connection terminal, para. [0069].
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Liu with the teachings of Lu because a dummy external connection terminal enables detection of “poor electrical interconnection, short circuit, crack, delamination”. See Lu at para. [0069].
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Liu, as applied to claim 14 above, in further view of Long, WO 2023060732 A1 (see attached English machine translation).
Regarding claim 19:
Chen and Liu teach all the limitations of claim 14 above, but do not expressly teach:
wherein only one of an ampere meter and a voltmeter is electrically connected to the at least two first test terminals, and
wherein only one of the ampere meter and the voltmeter is electrically connected to the at least two second test terminals.
In an analogous art, Long teaches:
(see fig. 13) wherein only one of an ampere meter and a voltmeter (1308) is electrically connected to at least two first test terminals (1301, 1302), and
wherein only one of the ampere meter and the voltmeter (1308) is electrically connected to at least two second test terminals (1303, 1304). See Long at English machine translation pages 27-28.
It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the teachings of Chen and Liu with the teachings of Long in order to test for abnormality in the performance of a series structure. See Long at English machine translation pages 27-28.
Conclusion
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/Michele Fan/
Primary Examiner, Art Unit 2818
18 December 2025