DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 10 are rejected under 35 U.S.C. 103(a) as being unpatentable over Dabral et al. Publication No. US 2015/0270258, in view of Xavier Publication No. US 2020/0083705.
Regarding claims 1, 10, Dabral discloses an integrated circuit (IC) comprising:
a voltage divider [Fig. 3D, 22] comprising a resistor and a capacitor which are coupled in series with each other between a first interconnect [Fig. 3D, Vdd] and a second interconnect [Fig. 3D, ground], wherein the first interconnect and the second interconnect are to receive a first supply voltage and a second supply voltage, respectively;
a pull-up circuit [Fig. 3D, 33] and a pull-down circuit [Fig. 3D, 35] which are coupled in series with each other between the first interconnect and the second interconnect; and control circuitry [Fig. 3D, 26] coupled between the first interconnect and the second interconnect, wherein the control circuitry is coupled in a bridge configuration with the voltage divider, wherein the control circuitry is coupled to automatically perform a transition of the IC to a first mode based on an electrostatic discharge (ESD) event, and wherein, during the first mode, the pull-up circuit is disabled and the pull-down circuit is enabled [par. 0045];
wherein an RC circuit of the IC is to automatically transition the IC from the first mode [par. 0045; the circuit 3D shown automatically transition from a normal mode of operation to an ESD event, based on the detection 22 and trigger signal generated from 22].
However, Dabral does not disclose a voltage divider comprising capacitors which are coupled in series with each other between a first interconnect and a second interconnect.
Xavier discloses an ESD protection circuit comprising: a voltage divider that comprises a plurality of capacitors connected in series [Fig. 3; voltage divider 310].
Dabral and Xavier are analogous electrostatic discharge protection circuits comprising ESD detection circuits. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to incorporate Xavier’s voltage divider of capacitors, into Dabral, because capacitive voltage dividers have less resistance resulting in less dissipation of waste energy as heat, have optimized accuracy and precision compared to resistors and other dividers.
Claims 9, 15, and 20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Dabral et al. Publication No. US 2015/0270258, in view of Xavier Publication No. US 2020/0083705, and further in view of Zhou et al. Patent No. US 11,652,348 and Linetwyhe CN 105655331.
Regarding claims 9, 15, and 20, Dabral discloses a pull-up circuit and a pull-down circuit. However, Dabral does not disclose that the pull-up circuit comprises
p-channel metal-oxide semiconductor (PMOS) transistors which are coupled in series with each other between the first interconnect and a first node; the pull-down circuit comprises n-channel metal-oxide semiconductor (NMOS) transistors which are coupled in series with each other between the first node and the second interconnect.
Zhou discloses an ESD protection circuit, co a pull-up circuit and a pull-down circuit. Zhou discloses that the pull-up circuit [Fig. 4, 110] comprises p-channel metal-oxide semiconductor (PMOS) transistors [Fig. 4, M0..M5] which are coupled in series with each other between the first interconnect [Fig. 4, Vdd] and a first node [Fig. 4, N1/N2]; the pull-down circuit [Fig. 4, 120] comprises n-channel metal-oxide semiconductor (NMOS) transistors [Fig. 4, M1…M7] which are coupled in series with each other between the first node and the second interconnect.
All three teachings are analogous electrostatic protection circuits. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to incorporate Zhou’s plurality of series-connected pull-up and pull-down transistors, for the benefit of allowing for controlled switching between logic states, preventing floating states and providing good noise immunity.
Linetwyhe shows that ballast resistors connected between two terminals of a transistor is well known in the electrostatic discharge art. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to incorporate Linetwyhe’s ballast resistors connected to the pull-up and pull-down transistors terminals, for the benefit of limiting the current through the transistor and preventing the transistors from sustaining a destructive secondary breakdown.
the IC further comprises ballast resistors each corresponding to a different respective transistor of the PMOS transistors and the NMOS transistors; for each of the ballast resistors, the ballast resistor is coupled between a respective two terminals of the corresponding transistor.
Claim 16 is rejected under 35 U.S.C. 103(a) as being unpatentable over Dabral et al. Publication No. US 2015/0270258, in view of Xavier Publication No. US 2020/0083705, and further in view of Yang et al. Publication No. US 2013/0182356.
Regarding claim 16, Dabral discloses an integrated circuit (IC) comprising:
a voltage divider [Fig. 3D, 22] comprising a resistor and a capacitor which are coupled in series with each other between a first interconnect [Fig. 3D, Vdd] and a second interconnect [Fig. 3D, ground], wherein the first interconnect and the second interconnect are to receive a first supply voltage and a second supply voltage, respectively;
a pull-up circuit [Fig. 3D, 33] and a pull-down circuit [Fig. 3D, 35] which are coupled in series with each other between the first interconnect and the second interconnect; and control circuitry [Fig. 3D, 26] coupled between the first interconnect and the second interconnect, wherein the control circuitry is coupled in a bridge configuration with the voltage divider, wherein the control circuitry is coupled to automatically perform a transition of the IC to a first mode based on an electrostatic discharge (ESD) event, and wherein, during the first mode, the pull-up circuit is disabled and the pull-down circuit is enabled [par. 0045];
wherein an RC circuit of the IC is to automatically transition the IC from the first mode [par. 0045; the circuit 3D shown automatically transition from a normal mode of operation to an ESD event, based on the detection 22 and trigger signal generated from 22].
However, Dabral does not disclose a voltage divider comprising capacitors which are coupled in series with each other between a first interconnect and a second interconnect.
Xavier discloses an ESD protection circuit comprising: a voltage divider that comprises a plurality of capacitors connected in series [Fig. 3; voltage divider 310].
Dabral and Xavier are analogous electrostatic discharge protection circuits comprising ESD detection circuits. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to incorporate Xavier’s voltage divider of capacitors, into Dabral, because capacitive voltage dividers have less resistance resulting in less dissipation of waste energy as heat, have optimized accuracy and precision compared to resistors and other dividers.
Yang discloses an electrostatic discharge protection circuit comprising a voltage divider [Fig. 5, 302, 304], a pull-up circuit [Fig. 5, 504], and a pull-down circuit [Fig. 5, 506]; an ESD network [Fig. 5, Shunt network 508] coupled to the voltage converter via an output node which is between the pull-up circuit and the pull-down circuit; and a load circuit [Fig. 5, ESD-susceptible circuit] coupled to receive an output voltage from the output node, wherein the output voltage is based on the first supply voltage and the second supply voltage.
All three teachings are analogous electrostatic discharge protection circuits. It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to incorporate Yang’s shunt network having a high voltage shunt transistor, into Dabral as modified by Xavier, for the benefit of selectively shunting energy from the ESD event over another electrical path based on the shunt control signal.
Allowable Subject Matter
Claims 2-8, 11-14, 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance of claims 2, 11, 19: The prior art does not disclose that the first driver circuitry comprises a first capacitor and a first inverter circuit; wherein a gate terminal of the first transistor is coupled to receive a first gate signal which is generated with the first capacitor and the first inverter circuit based on the first input signal. This feature in combination with the rest of the claim limitations is not anticipated or rendered obvious by the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DHARTI PATEL whose telephone number is (571)272-8659. The examiner can normally be reached M - F 9 AM - 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached on 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
DHARTI PATEL
Primary Examiner
Art Unit 2836
/DHARTI H PATEL/Primary Examiner, Art Unit 2836
Prosecution Insights