DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action responds to the Response to Election/Restriction and amendment filed on 5/22/2026. Claims 1-20 are pending, wherein claims 10-20 are withdrawn from further consideration as being directed to non-elected invention without traverse.
Election/Restrictions
Applicant’s election without traverse of group I invention, claims 1-9 in the reply filed on 5/22/2026 is acknowledged.
Claims 10-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 5/22/2026.
Applicant is again reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i).
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated (see Applicant’s specification, paragraphs [0002], [0010]). See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshioka (US Patent No. 7,446,417 B2).
As per claim 1¸Fig. 2 illustrates the elements of the claims comprising:
a transistor layer comprising a plurality of operable transistors (the first 4 layers containing segments 13, 11, 9, 5, 14, 1 which are used to form transistors—see col. 6, lines 13-42); and
a metallization stack including: a plurality of metal layers (M1..M6 as shown) and a plurality of via layers (19, 21, 23, 25, 29) interleaved within the plurality of metal layers (M1..M6); and signal lines (31 shown here as representative of similar signal lines formed in the IC) formed from wires from different metal layers coupled to one another through vias from different via layers, the signal lines being coupled to at least some of the operable transistors (i.e., transistors formed in layers 13, 11, 9, 5, 3, 1); and thermal tower assemblages (35, 37) formed from wires from different metal layers coupled to one another through vias from different via layers, the thermal tower assemblages not being coupled to the operable transistors (see also col. 6, line 13 to col. 7, line 61).
As per claim 2, thermal tower assemblages (33) are coupled through contacts to unused transistor material in the transistor layer (13 by via 19, materials that are not connected to the signal transmission can be used for heat conduction—col. 7, lines 15-27).
As per claim 3, metallization stack includes metal fill pieces disposed within two or more of the plurality of metal layers (i.e., dummy metals—see col. 3, line 66 to col. 4, line 4; col. 7, line 48 to col. 8, line 9).
As per claim 4, wherein the thermal tower assemblages include a first set of assemblages having the same configurations and feature sizes (Fig. 4, 43 and 45) and a second set of assemblages (Fig. 4, 33, 37, 35) having different configurations from those of the first set.
As per claims 5-6, , wherein the thermal tower assemblages include a first set of assemblages consisting of wires from two adjacent metal layers and a second or third set of assemblages consisting of wires from three adjacent metal layers.is within the scope of Yoshioka because heat conduction could be placed between close or connect adjacent wiring layers (col. 4, lines 5-8), which can extend to cover all metal wiring layers M1..M6 (see Fig. 2, 33, 31, 35, 37 which conduct heats to various adjacent layers).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshioka (US Patent No. 7,446,417 B2) over Horiguchi et al., “Backside power delivery--How to power chips from the backside: benefits and building blocks of a backside power delivery network”, IMEC, https://www.imec-int.com/en/articles/how-power-chips-backside, published 11/25/2022, 42 pages).
As per claims 8-9, Yoshioka teach all of the elements of claim 1, from which the claim depend but failed to particularly teach that the metallization stack is a frontside metallization stack and the integrated circuit comprises a backside metallization stack having at least one metal layer to provide power to the operable transistors and the transistor layer is coupled to the frontside of the metallization stack. Horiguchi et al. teach that the power delivery network is decoupled from the signal network (which is placed in the frontside—i.e., metallization stack which forms the signal network connected or coupled to the transistors—see pages 3-4) by moving the entire power distribution network to the back side of the silicon wafer, enabling direct power delivery to the standard cells through wider, less resistive metal lines without the electrons needing to travel through the complex BEOL stack, improving power delivery performance, reducing congesting in the BEOL and allow for standard cell height (see pages 7-8). It would have been obvious to one of ordinary skilled in the art at the time of the effective filing date of the invention to further incorporate the teachings of Yoshioka because such incorporation would further enables direct power delivery to the standard cells through wider, less resistive metal lines without the electrons needing to travel through the complex BEOL stack, improving power delivery performance, reducing congesting in the BEOL and allow for standard cell height.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As per claim 7, the claims further recites inventive features in which the thermal tower assemblages having a wire section in the local metal layer (with wire sections disposed along spaced apart tracks) are at least two tracks away from a wire in that local metal layer of a signal line, in combination with the other elements as claimed, which the prior arts made of record failed to teach or suggest as claimed.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PHALLAKA KIK whose telephone number is (571)272-1895. The examiner can normally be reached Maxiflex Mon-Fri 8:30AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 5712727483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Any response to this action should be mailed to:
Commissioner for Patents
P. O. Box 1450
Alexandria, VA 22313-1450
or faxed to:
571-273-8300
/PHALLAKA KIK/Primary Examiner, Art Unit 2851 June 24, 2026
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