DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species I, embodiment in Figs. 1-8 claims 1-6 and 15-20, in the reply filed on 3/31/2026 is acknowledged. Claims 7-14 have been withdrawn from consideration.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tseng et al. (US 9607985 B1).
Regarding claim 1, Tseng teaches a manufacturing method (Figs. 5-9 of Tseng) of a semiconductor structure (structure in Fig. 9 of Tseng), comprising:
forming fin-shaped structures (101 in Fig. 5) by patterning a first region (region A in Fig. 5) of a semiconductor substrate (100);
forming a first shallow trench (trench formed by partially removing the fin in region C, as shown in Fig. 7) in a second region (region C) of the semiconductor substrate, wherein a part (top surface of bump 110c in Fig. 7 is exposed at the bottom 160c ) of the semiconductor substrate is exposed by a bottom of the first shallow trench; and
performing a first etching process (fourth step in the fin cut process as shown in Figs. 7-8), wherein at least a part of one of the fin-shaped structures (left fin in the region B in Fig. 6 of Tseng is removed, as shown in Fig. 8) is removed by the first etching process, and the part (bump 110c) of the semiconductor substrate exposed by the first shallow trench is partially removed by the first etching process for forming a first deep trench (240c in Fig. 8).
Regarding claim 2, Tseng teaches all limitations of the manufacturing method of the semiconductor structure according to claim 1, and also teaches wherein the first shallow trench extends downwards to become the first deep trench by the first etching process (as shown in Figs. 7-8 of Tseng).
Regarding claim 3, Tseng teaches all limitations of the manufacturing method of the semiconductor structure according to claim 1, and also teaches wherein the first etching process is a fin cut process (as shown in Figs. 7-8 of Tseng).
Regarding claim 4, Tseng teaches all limitations of the manufacturing method of the semiconductor structure according to claim 1, and also teaches wherein the bottom of the first shallow trench is lower than each of the fin-shaped structures in a vertical direction (as shown in Figs. 7 of Tseng).
Claims 1, 15 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et al. (US 10109531 B1).
Regarding claim 1, Hsu teaches a manufacturing method (Figs. 1-6 of Hsu) of a semiconductor structure, comprising:
forming fin-shaped structures (10F in Figs. 1-2 of Hsu) by patterning a first region (region covered by mask 33 in Fig. 2) of a semiconductor substrate (10);
forming a first shallow trench (right sub-trench 41 of the two left sub-trenches 41 are shown in Fig. 3) in a second region (left region R1 in Fig. 4) of the semiconductor substrate, wherein a part (part of substrate 10 directly underneath the sub-trenches 41 as shown in Fig. 3) of the semiconductor substrate is exposed by a bottom of the first shallow trench;
performing a first etching process (second etching 92 in Fig. 4-5 of Hsu), wherein at least a part of one of the fin-shaped structures (the middle fins 10F that are etched by process 92 in Figs. 4-5 of Hsu) is removed by the first etching process, and the part of the semiconductor substrate exposed by the first shallow trench is partially removed by the first etching process for forming a first deep trench (as shown in Fig. 5 of Hsu, some portion of substrate 10 near the right sub-trench 41 is removed).
Regarding claim 15, Hsu teaches all limitations of the manufacturing method of the semiconductor structure according to claim 1, and further comprising:
forming a second shallow trench (left sub-trench 41 of the right two sub-trenches 41 in Fig. 3 of Hsu) in a third region (right region R1 in Fig. 3) of the semiconductor substrate, wherein a part (part of substrate 10 directly underneath the right region R1) of the semiconductor substrate is exposed by a bottom of the second shallow trench, and the part of the semiconductor substrate exposed by the second shallow trench is partially removed by the first etching process for forming a second deep trench (as shown in Fig. 5 of Hsu, some portion of substrate 10 near the right sub-trench 41 is removed).
Regarding claim 18, Hsu teaches all limitations of the manufacturing method of the semiconductor structure according to claim 15, and also teaches wherein the first shallow trench and the second shallow trench are formed concurrently by the same process (as shown in Fig. 2-3 of Hsu), and the first deep trench and the second deep trench are formed concurrently by the same process (as shown in Fig. 5 of Hsu).
Claims 1, 5-6, 15-17, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liou et al. (US 2016/0329248 A1).
Regarding claim 1, Liou teaches a manufacturing method of a semiconductor structure (Figs. 1-7 of Liou), comprising:
forming fin-shaped structures (120 in Figs. 1-3 of Liou) by patterning a first region (region of fins 120 apart of region 103 and 105 shown in Fig. 4) of a semiconductor substrate (100);
forming a first shallow trench (trench shown in Fig. 3) in a second region (overlapped area between the middle opening 101 and the middle opening 105 as shown in Fig. 3) of the semiconductor substrate, wherein a part (part of substrate 100 that is an overlapped area between the middle opening 101 and the middle opening 105 as shown in Fig. 3) of the semiconductor substrate is exposed by a bottom (surface 104 in second region) of the first shallow trench;
performing a first etching process (second fin cut process in openings 103 and 105, as shown in Figs. 4-6 and described in [0025]-[0028]), wherein at least a part of one of the fin-shaped structures (part of the fins 120 in region 105 is removed, as shown in Figs. 4-5) is removed by the first etching process, and the part of the semiconductor substrate exposed by the first shallow trench is partially removed by the first etching process for forming a first deep trench (trench 108 in Fig. 6).
Regarding claim 5, Liou teaches all limitations of the manufacturing method of the semiconductor structure according to claim 1, and also teaches wherein a method of forming the first shallow trench comprises:
performing a second etching process (etching process described in [0023] of Liou) before the first etching process, wherein at least a part of another one (a fin 120 exposed by the opening 101 in Fig. 1) of the fin-shaped structures is removed by the second etching process (as shown in Figs. 1-3 and described in [0023] of Liou), and a part of the second region of the semiconductor substrate is removed by the second etching process for forming the first shallow trench (as shown in Fig. 3, the substrate 100 within the region exposed by the opening 101 is etched to forming dishing surface 104).
Regarding claim 6, Liou teaches all limitations of the manufacturing method of a semiconductor structure according to claim 5, and also teaches wherein the second etching process is a fin cut process (as described in [0023] of Liou).
Regarding claim 15, Liou teaches all limitations of the manufacturing method of the semiconductor structure according to claim 1, and further comprising:
forming a second shallow trench (122 in Fig. 3 of Liou) in a third region (region of substrate within the opening 103) of the semiconductor substrate, wherein a part (part of substrate 100 with surface 102 in the third region in Fig. 3) of the semiconductor substrate is exposed by a bottom (surface 102) of the second shallow trench, and the part of the semiconductor substrate exposed by the second shallow trench is partially removed by the first etching process for forming a second deep trench (106 in Fig. 6 of Liou).
Regarding claim 16, Liou teaches all limitations of the manufacturing method of the semiconductor structure according to claim 15, and also teaches wherein the bottom of the first shallow trench is lower than the bottom of the second shallow trench in a vertical direction (as shown in Fig. 3 of Liou, bottom surface 104 is lower than surface 102).
Regarding claim 17, Liou teaches all limitations of the manufacturing method of the semiconductor structure according to claim 15, and also teaches wherein a bottom of the first deep trench is lower than a bottom of the second deep trench in a vertical direction (as shown in Fig. 6 and stated in [0028] of Liou, bottom of 108 is lower than that of 106).
Regarding claim 19, Liou teaches all limitations of the manufacturing method of the semiconductor structure according to claim 15, and further comprising:
forming a first deep trench isolation structure (307 in Fig. 7 of Liou) in the first deep trench;
forming a second deep trench isolation structure (305) in the second deep trench; and
forming an isolation structure (301) between the fin-shaped structures, wherein the first deep trench isolation structure, the second deep trench isolation structure, and the isolation structure are formed concurrently by the same process (as described in [0030] of Liou).
Regarding claim 20, Liou teaches all limitations of the manufacturing method of the semiconductor structure according to claim 1, further comprising:
forming a recess (122 in Fig. 2-3 of Liou) in the second region of the semiconductor substrate before the first shallow trench is formed, wherein the first shallow trench overlaps the recess in a vertical direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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