DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment filed on 7/1/2026 is acknowledged. Claims 1, 16-17, 19 have been amended. Claims 7-14 remain withdrawn from consideration. Claims 2, 15 and 18 have been canceled.
Response to Arguments
Applicant's arguments filed 7/1/2026 have been fully considered but they are not persuasive. The amendment of claim 1 has not overcome all the possible rejections of based on the prior art of record. Please see the rejections below for more details.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-5, 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liou et al. (US 2016/0329248 A1).
Regarding claim 1, Liou teaches a manufacturing method of a semiconductor structure (Figs. 1-7 of Liou), comprising:
forming fin-shaped structures (120 in Figs. 1-3 of Liou) by patterning a first region (region of fins 120 exposed in the middle opening 101 in Fig. 1 of Liou) of a semiconductor substrate (100);
forming a first shallow trench (122) in a second region (region of fins 120 exposed in left opening 101 in Fig. 1 of Liou and overlapped by the region 105 in Fig. 4) of the semiconductor substrate, wherein a part of the semiconductor substrate is exposed by a bottom of the first shallow trench (part of substrate 100 at bottom of trench 122 shown in Fig. 3);
performing a first etching process (fin cut process in openings 103 and 105, as shown in Figs. 4-6 and described in [0025]-[0028]), wherein at least a part of one of the fin-shaped structures (part of the fins 120 in region 105 is removed, as shown in Figs. 4-5) is removed by the first etching process, the part of the semiconductor substrate exposed by the first shallow trench is partially removed by the first etching process for forming a first deep trench (trench 108 in Fig. 6), and the first shallow trench extends downwards to become the first deep trench by the first etching process (as shown in Figs. 3, 5 and 6 of Liou); and
forming a second shallow trench (trench 122 in Fig. 3 between the fins in the left opening 101 in Fig. 1) in a third region (overlapped area between the left opening 101 and the middle opening 105 as shown in Fig. 4) of the semiconductor substrate, wherein a part of the semiconductor substrate is exposed by a bottom of the second shallow trench (part of substrate 100 at bottom of trench 122 of the left opening 101 in Figs. 3-4), and the part of the semiconductor substrate exposed by the second shallow trench is partially removed by the first etching process for forming a second deep trench (108 in Fig. 6 of the opening 105 and left opening 101 in Fig. 4 of Liou),
wherein the first shallow trench and the second shallow trench are formed concurrently by the same process (as described in [0020]-[0021] of Liou, all the fins are formed at the same time), and the first deep trench and the second deep trench are formed concurrently by the same process (as indicated in Figs. 4-6 of Liou).
Regarding claim 3, Liou teaches all limitations of the manufacturing method of the semiconductor structure according to claim 1, and also teaches wherein the first etching process is a fin cut process (as shown in Figs. 4-6 of Liou).
Regarding claim 4, Liou teaches all limitations of the manufacturing method of the semiconductor structure according to claim 1, and also teaches wherein the bottom of the first shallow trench is lower than each of the fin-shaped structures is a vertical direction (as shown in Fig. 6 of Liou).
Regarding claim 5, Liou teaches all limitations of the manufacturing method of the semiconductor structure according to claim 1, and also teaches wherein a method of forming the first shallow trench comprises:
performing a second etching process (the etching process the forms the fin structures 120, as described in [0021] of Liou) before the first etching process, wherein at least a part of another one of the fin-shaped structures is removed by the second etching process, and a part of the second region of the semiconductor substrate is removed by the second etching process for forming the first shallow trench (as shown in Fig. 3 of Liou).
Regarding claim 19, Liou teaches all limitations of the manufacturing method of the semiconductor structure according to claim 1, and further comprising:
forming a first deep trench isolation structure (portion of isolation structure 307 in the middle opening 105 as shown in Fig. 7 of Liou) in the first deep trench;
forming a second deep trench isolation structure (portion of isolation structure 307 in the left opening 105 as shown in Fig. 7 of Liou) in the second deep trench; and
forming an isolation structure (301 in Fig. 7) between the fin-shaped structures, wherein the first deep trench isolation structure, the second deep trench isolation structure, and the isolation structure are formed concurrently by the same process (as shown in Fig. 7 and [0030] of Liou).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 are rejected under 35 U.S.C. 103 as being unpatentable over Liou, as applied to claim 1 above, and further in view of Miller et al. (US 6218309 B1).
Regarding claim 17, Liou teaches all limitations of the manufacturing method of the semiconductor structure according to claim 1, but does not teach explicitly wherein a bottom of the first deep trench is lower than a bottom of the second deep trench in a vertical direction.
Liou discloses that the middle opening 101 has greater width than the left opening 101 (see Fig. 2 of Liou).
Miller teaches a method of etching trenches in a semiconductor substrate (12 in Figs. 1A-1C of Miller). The wider trenches (32 in Fig. 1C of Miller) have an increased etch rate over narrow trench etch rate (column 2 lines 36-39 of Miller). As a result, the wider trenches have greater depth than the narrow trenches (see Fig. 1C of Miller).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the bottom of the first deep trench to be lower than the bottom of the second deep trench in a vertical direction since this is what naturally happens without any special intervention (which requires more work, thus, higher costs).
Allowable Subject Matter
Claims 6, 16 and 20 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 6, the prior art of record does not disclose or fairly suggest a manufacturing method of a semiconductor structure satisfying “wherein the second etching process is a fin cut process” along with other limitations of claim 5.
Regarding claim 16, the prior art of record does not disclose or fairly suggest a manufacturing method of a semiconductor structure satisfying “wherein the bottom of the first shallow trench is lower than the bottom of the second shallow trench in a vertical direction” along with other limitations of claim 1.
Regarding claim 20, the prior art of record does not disclose or fairly suggest a manufacturing method of the semiconductor structure that comprising: “forming a recess in the second region of the semiconductor substrate before the first shallow trench is formed, wherein the first shallow trench overlaps the recess in a vertical direction” along with other limitations of claim 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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