DETAILED ACTION
This office action is in response to the application filed on November 27, 2025. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
Applicant's amendments and arguments filed on November 27, 2025, in response to the office action mailed on August 27, 2025 are acknowledged. The present office action is made with all the suggested arguments being fully considered. Accordingly, claims 1-10, 12-21 are currently pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/14/2023, 4/2/2024 and 5/21/2024 are being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10, 12-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With respect to claim 1, it is unclear to the examiner is applicant is claiming with the limitation recited “wherein a thickness of the oxide layer is greater than 40% of a thickness of the uppermost metal pattern and is less than a thickness of the uppermost metal pattern.” Although there is support in the specification, there seems to be some confusing language that renders the claims indefinite. Clarification of the limitation is needed. Appropriate correction is required. For purpose of examination, the examiner interprets the claim to read “wherein a thickness of the oxide layer is equal to 40% or greater of a thickness of the uppermost metal pattern and wherein a thickness of the oxide layer is less than a thickness of the uppermost metal pattern.”
Claims 2-10, 12-14, 21 depend from Claim 1, thus inherit the deficiencies identified supra. Appropriate correction is required.
With respect to claim 15, it is unclear to the examiner is applicant is claiming with the limitation recited “wherein a thickness of the oxide layer is greater than 40% of a thickness of the uppermost metal pattern and is less than a thickness of the uppermost metal pattern.” Although there is support in the specification, there seems to be some confusing language that renders the claims indefinite. Clarification of the limitation is needed. Appropriate correction is required. For purpose of examination, the examiner interprets the claim to read “wherein a thickness of the oxide layer is equal to 40% or greater of a thickness of the uppermost metal pattern and wherein a thickness of the oxide layer is less than a thickness of the uppermost metal pattern.”
Claims 16-18 depend from Claim 15, thus inherit the deficiencies identified supra. Appropriate correction is required.
With respect to claim 19, it is unclear to the examiner is applicant is claiming with the limitation recited “wherein a thickness of the oxide layer is greater than 40% of a thickness of the uppermost metal pattern and is less than a thickness of the uppermost metal pattern.” Although there is support in the specification, there seems to be some confusing language that renders the claims indefinite. Clarification of the limitation is needed. Appropriate correction is required. For purpose of examination, the examiner interprets the claim to read “wherein a thickness of the oxide layer is equal to 40% or greater of a thickness of the uppermost metal pattern and wherein a thickness of the oxide layer is less than a thickness of the uppermost metal pattern.”
Claim 20 depends from Claim 19, thus inherit the deficiencies identified supra. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10, 12-18, 21 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2021/0104462) in view of Kim (US 2021/0375896) .
With respect to Claim 1, Lee shows (Fig. 5) most aspects of the current invention including a semiconductor device, comprising:
lower metal wirings (45,47) on a substrate (21), the lower metal wirings stacked in a plurality of layers;
a first upper insulating interlayer (53E) on the lower metal wirings;
a first upper wiring including a first upper via (61) in the first upper insulating interlayer and a first upper metal pattern (65) on the first upper insulating interlayer
a second upper insulating interlayer (53c) on the first upper insulating interlayer, the second upper insulating interlayer covering the first upper metal pattern;
an uppermost wiring including an uppermost via (71) in the second upper insulating interlayer and an uppermost metal pattern (75) on the second upper insulating interlayer
an oxide layer (55a) on the second upper insulating interlayer and covering the uppermost wiring
wherein a thickness of the uppermost via (71) is less than 40% of a thickness of the uppermost metal pattern (75)
Furthermore, Lee discloses than a thickness of the uppermost metal pattern is 2 μm to about 10 μm (20000 Å - 100000 Å). Additionally, although Lee discloses layer (55a) is an oxide layer such as HDP oxide, Lee fails to disclose the oxide layer for supplying hydrogen on the second upper insulating interlayer and wherein a thickness of the oxide layer is equal to 40% or greater of a thickness of the uppermost metal pattern and wherein a thickness of the oxide layer is less than a thickness of the uppermost metal pattern.
On the other hand, and in the same field of endeavor, Kim teaches (Fig. 2,14A-14B) a semiconductor device, comprising lower metal wirings (131,133,135) on a substrate (100), a first upper insulating interlayer (LK3), a second upper insulating interlayer (150) on the first upper insulating interlayer, an uppermost wiring including an uppermost metal pattern (171) on the second upper insulating interlayer and an oxide layer (170) for supplying hydrogen on the second upper insulating interlayer, the oxide layer for supplying hydrogen covering the uppermost wiring (par 41,44) and further wherein a thickness of the oxide layer (that is a HDP layer) may be ≥8000 Å. Kim teaches doing so such that a hydrogen supply path is maintained through or to reach a cell array region to thereby reduce leakage current and also to help improve electrical characteristics of a cell array, and that the hydrogen supply to a peripheral circuit region is selectively blocked to help prevent a reduction in reliability of peripheral circuits (par 92).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the oxide layer for supplying hydrogen on the second upper insulating interlayer and wherein a thickness of the oxide layer is equal to 40% or greater of a thickness of the uppermost metal pattern and wherein a thickness of the oxide layer is less than a thickness of the uppermost metal pattern in the device of Lee, as taught by Kim such that a hydrogen supply path is maintained through or to reach a cell array region to thereby reduce leakage current and also to help improve electrical characteristics of a cell array, and that the hydrogen supply to a peripheral circuit region is selectively blocked to help prevent a reduction in reliability of peripheral circuits.
With respect to Claim 2, Lee shows (Fig. 5) wherein the thickness of the uppermost metal pattern (75) is 2 μm to about 10 μm (20000 Å - 100000 Å) (par 40).
With respect to Claim 3, Lee shows (Fig. 5) wherein the thickness of the uppermost via (71) is 20% to 35% of the thickness of the uppermost metal pattern (par 40).
With respect to Claim 4, Lee shows (Fig. 5) wherein a metal included in the first upper wiring (65) and a metal included in the uppermost wiring (75) are different from a metal included in the lower metal wirings (45b,45c,45d).
With respect to Claim 5, Lee shows (Fig. 5) wherein the metal included in the lower metal wiring includes copper (par 21).
With respect to Claim 6, Lee shows (Fig. 5) wherein the uppermost via (71) includes tungsten, and the uppermost metal pattern (75) includes aluminum (par 23-24).
With respect to Claim 7, Lee shows (Fig. 5) wherein each of the lower metal wirings includes a via (47a-47c) and a metal pattern (45a-45d) and wherein each of the lower metal wirings includes a via and a metal pattern, and a thickness of the via is 50% to 100% of a thickness of the metal pattern.
Regarding claim 7, the courts have held that differences in the thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the thicknesses and similar thicknesses are known in the art (see e.g. Lee), it would have been obvious to one of the ordinary skill in the art to use these values in the device Lee in view of Kim.
Criticality: The specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 8, Lee shows (Fig. 5) wherein an uppermost via thickness ratio may be less than or equal to a first upper via thickness ratio.
Regarding claim 8, the courts have held that differences in the ratios will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ratios are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the ratios and similar ratios are known in the art (see e.g. Lee), it would have been obvious to one of the ordinary skill in the art to use these values in the device Lee in view of Kim.
Criticality: The specification contains no disclosure of either the critical nature of the claimed ratios or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 9, Lee shows (Fig. 5) wherein a thickness of the first upper via (61) in the first upper metal wiring is 30% to 100% of a thickness of the first upper metal pattern (65).
Regarding claim 9, the courts have held that differences in the thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the thicknesses and similar thicknesses are known in the art (see e.g. Lee), it would have been obvious to one of the ordinary skill in the art to use these values in the device Lee in view of Kim.
Criticality: The specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 10, Kim teaches (Fig. 2,14A-14B) wherein the oxide layer for supplying hydrogen includes a high density plasma oxide layer.
With respect to Claim 12, Lee shows (Fig. 5,11) further comprising: an uppermost insulating interlayer (55b) on the oxide layer (55a), the uppermost insulating interlayer including silicon oxide and having a flat upper surface (par 43); and further an upper capping layer on the uppermost insulating interlayer (85; see Fig 11).
With respect to Claim 13, Lee shows (Fig. 1,4,5) further comprising a memory cell (MC) between the substrate and the lowermost metal pattern in a vertical direction. Additionally, Kim teaches (Fig. 2,14A-14B) further comprising memory cells (CTR/DSS) between the substrate and the lowermost metal pattern in a vertical direction.
With respect to Claim 14, Lee shows (Fig. 5,11,14) further comprising bump pads (85) and bumps (87) on the uppermost metal pattern (75).
With respect to Claim 15, Lee shows (Fig. 5,11) most aspects of the current invention including a semiconductor device, comprising:
A memory cell (MC) on a substrate (21)
lower metal wirings (45,47) on the memory cell (MC), the lower metal wirings stacked in a plurality of layers
a first upper insulating interlayer (53E) on the lower metal wirings;
a first upper wiring including a first upper via (61) in the first upper insulating interlayer and a first upper metal pattern (65) on the first upper insulating interlayer;
a second upper insulating interlayer (53c) on the first upper insulating interlayer,
an uppermost wiring including an uppermost via (71) in the second upper insulating interlayer and an uppermost metal pattern (75) on the second upper insulating interlayer;
an oxide layer (55a) on the second upper insulating interlayer and covering the uppermost wiring,
an uppermost insulating interlayer (55b) on the oxide layer, the uppermost insulating interlayer including silicon oxide and having a flat upper surface (par 43)
an upper capping layer on the uppermost insulating interlayer (85; see Fig 11) a stack structure including the oxide layer for supplying hydrogen and the uppermost insulating interlayer, the stack structure covering an upper surface of the uppermost metal pattern of the uppermost wiring
wherein a thickness of the uppermost via (71) is less than 40% of a thickness of the uppermost metal pattern (75)
Furthermore, Lee discloses than a thickness of the uppermost metal pattern is 2 μm to about 10 μm (20000 Å - 100000 Å). Additionally, although Lee discloses layer (55a) is an oxide layer such as HDP oxide, Lee fails to disclose memory cells on a substrate, the oxide layer for supplying hydrogen on the second upper insulating interlayer and wherein a thickness of the oxide layer is equal to 40% or greater of a thickness of the uppermost metal pattern and wherein a thickness of the oxide layer is less than a thickness of the uppermost metal pattern.
On the other hand, and in the same field of endeavor, Kim teaches (Fig. 2,14A-14B) a semiconductor device, comprising lower metal wirings (131,133,135) on a substrate (100), memory cells (CTR/DSS) on the substrate, a first upper insulating interlayer (LK3), a second upper insulating interlayer (150) on the first upper insulating interlayer, an uppermost wiring including an uppermost metal pattern (171) on the second upper insulating interlayer and an oxide layer (170) for supplying hydrogen on the second upper insulating interlayer, the oxide layer for supplying hydrogen covering the uppermost wiring (par 41,44) and further wherein a thickness of the oxide layer (that is a HDP layer) may be ≥8000 Å. Kim teaches doing so such that a hydrogen supply path is maintained through or to reach a cell array region to thereby reduce leakage current and also to help improve electrical characteristics of a cell array, and that the hydrogen supply to a peripheral circuit region is selectively blocked to help prevent a reduction in reliability of peripheral circuits (par 92).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have memory cells on a substrate, the oxide layer for supplying hydrogen on the second upper insulating interlayer and wherein a thickness of the oxide layer is equal to 40% or greater of a thickness of the uppermost metal pattern and wherein a thickness of the oxide layer is less than a thickness of the uppermost metal pattern in the device of Lee, as taught by Kim such that a hydrogen supply path is maintained through or to reach a cell array region to thereby reduce leakage current and also to help improve electrical characteristics of a cell array, and that the hydrogen supply to a peripheral circuit region is selectively blocked to help prevent a reduction in reliability of peripheral circuits.
With respect to Claim 16, Lee shows (Fig. 5,11) wherein an uppermost via thickness ratio may be less than or equal to a first upper via thickness ratio.
Regarding claim 16, the courts have held that differences in the ratios will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such ratios are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the ratios and similar ratios are known in the art (see e.g. Lee), it would have been obvious to one of the ordinary skill in the art to use these values in the device Lee in view of Kim.
Criticality: The specification contains no disclosure of either the critical nature of the claimed ratios or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
With respect to Claim 17, Lee shows (Fig. 5,11) wherein a thickness of the oxide layer (55a) is greater than the thickness of the uppermost via (71). With respect to an oxide layer for supplying hydrogen, see comments stated above in Par. 42-44 with regards to Claim 15, which are considered repeated here.
With respect to Claim 18, Lee shows (Fig. 5,11) wherein a thickness (T3) of the uppermost metal pattern (75) is greater than each of a thickness (T2) of the first upper wiring and a thickness (T1) of lower metal wiring.
With respect to Claim 21, Kim teaches (Fig. 2,14A-14B) a semiconductor device, comprising an oxide layer (170) for supplying hydrogen on the second upper insulating interlayer (150), the oxide layer for supplying hydrogen covering the uppermost wiring (par 41,44) and further wherein a thickness of the oxide layer (that is a HDP layer) may be ≥8000 Å. Furthermore, Kim teaches (One or both of the first and second upper interlayer dielectric layers 150 and 170 may be a dielectric layer with high concentration of hydrogen and high capability of hydrogen supply. In an implementation, the second upper interlayer dielectric layer 170 may be a dielectric layer whose concentration of hydrogen and capability of hydrogen supply are relatively greater than those of the first upper interlayer dielectric layer 150; par 44)
Kim teaches doing so such that a hydrogen supply path is maintained through or to reach a cell array region to thereby reduce leakage current and also to help improve electrical characteristics of a cell array, and that the hydrogen supply to a peripheral circuit region is selectively blocked to help prevent a reduction in reliability of peripheral circuits (par 92).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the first and second upper insulating interlayer under the uppermost metal pattern are not used as layers for supplying hydrogen in the device of Lee, as taught by Kim such that a hydrogen supply path is maintained through or to reach a cell array region to thereby reduce leakage current and also to help improve electrical characteristics of a cell array, and that the hydrogen supply to a peripheral circuit region is selectively blocked to help prevent a reduction in reliability of peripheral circuits.
Regarding claim 21, the courts have held that differences in the thicknesses will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such thicknesses are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the thicknesses and similar thicknesses are known in the art (see e.g. Lee), it would have been obvious to one of the ordinary skill in the art to use these values in the device Lee in view of Kim.
Criticality: The specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Suh (US 2021/0125955) in view of Lee (US 2021/0104462) and in further view of Kim (US 2021/0375896) .
With respect to Claim 19, Suh shows (Fig. 1a) most aspects of the current invention including a high-bandwidth memory device, comprising:
a package substrate (100)
a plurality of memory dies (300,400) stacked on a package substrate;
a logic die (500) on the plurality of memory dies;
a molding member (600) on the package substrate, the molding member covering the memory dies and a logic die,
However, Suh does not disclose wherein each of the plurality of memory dies includes: lower metal wirings on a substrate, the lower metal wirings stacked in a plurality of layers; a first upper wiring on the lower metal wiring, the first upper wiring including a first upper via and a first upper metal pattern; and an uppermost wiring on the first upper wiring, the uppermost wiring including an uppermost via and an uppermost metal pattern, an oxide layer for supplying hydrogen that covers a top surface of the uppermost metal pattern, wherein a thickness of the uppermost via is less than 40% of a thickness of the uppermost metal pattern, wherein a thickness of the oxide layer is equal to 40% or greater of a thickness of the uppermost metal pattern and wherein a thickness of the oxide layer is less than a thickness of the uppermost metal pattern.
On the other hand, and in the same field of endeavor, Lee teaches (Fig. 1-4, 14-16) a high-bandwidth memory device, comprising a plurality of memory dies (MD1-MD4) stacked on a package substrate (PC), wherein each of the plurality of memory dies includes lower metal wirings (45,47) on a substrate (base layer), the lower metal wirings stacked in a plurality of layers, a first upper wiring on the lower metal wiring, the first upper wiring including a first upper via (61) and a first upper metal pattern (65), and an uppermost wiring on the first upper wiring, the uppermost wiring including an uppermost via (71) and an uppermost metal pattern (75), an oxide layer (55a) that covers a top surface of the uppermost metal pattern, wherein a thickness of the uppermost via is less than 40% of a thickness of the uppermost metal pattern. Lee teaches an interconnection resistance may be reduced due to configurations of the plurality of first upper vias (61), first upper metal patterns (65), uppermost vias (71) and uppermost metal patterns (75) (par 44).
Accordingly, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein each of the plurality of memory dies includes: lower metal wirings on a substrate, the lower metal wirings stacked in a plurality of layers; a first upper wiring on the lower metal wiring, the first upper wiring including a first upper via and a first upper metal pattern; and an uppermost wiring on the first upper wiring, the uppermost wiring including an uppermost via and an uppermost metal pattern, an oxide layer covering a top surface of the uppermost metal pattern, wherein a thickness of the uppermost via is less than 40% of a thickness of the uppermost metal pattern, in the device of Suh, as taught by Lee, because an interconnection resistance may be reduced due to configurations of the plurality of first upper vias (61), first upper metal patterns (65), uppermost vias (71) and uppermost metal patterns (75).
Furthermore, Lee discloses than a thickness of the uppermost metal pattern is 2 μm to about 10 μm (20000 Å - 100000 Å). Additionally, although Lee discloses layer (55a) is an oxide layer such as HDP oxide, Lee fails to disclose the oxide layer for supplying hydrogen, and wherein a thickness of the oxide layer is equal to 40% or greater of a thickness of the uppermost metal pattern and wherein a thickness of the oxide layer is less than a thickness of the uppermost metal pattern.
On the other hand, and in the same field of endeavor, Kim teaches (Fig. 2,14A-14B) a semiconductor device, comprising lower metal wirings (131,133,135) on a substrate (100), memory cells (CTR/DSS) on the substrate, a first upper insulating interlayer (LK3), a second upper insulating interlayer (150) on the first upper insulating interlayer, an uppermost wiring including an uppermost metal pattern (171) on the second upper insulating interlayer and an oxide layer (170) for supplying hydrogen on the second upper insulating interlayer, the oxide layer for supplying hydrogen covering the uppermost wiring (par 41,44) and further wherein a thickness of the oxide layer (that is a HDP layer) may be ≥8000 Å. Kim teaches doing so such that a hydrogen supply path is maintained through or to reach a cell array region to thereby reduce leakage current and also to help improve electrical characteristics of a cell array, and that the hydrogen supply to a peripheral circuit region is selectively blocked to help prevent a reduction in reliability of peripheral circuits (par 92).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have memory cells on a substrate, the oxide layer for supplying hydrogen and wherein a thickness of the oxide layer is equal to 40% or greater of a thickness of the uppermost metal pattern and wherein a thickness of the oxide layer is less than a thickness of the uppermost metal pattern in the device of Suh and Lee, as taught by Kim such that a hydrogen supply path is maintained through or to reach a cell array region to thereby reduce leakage current and also to help improve electrical characteristics of a cell array, and that the hydrogen supply to a peripheral circuit region is selectively blocked to help prevent a reduction in reliability of peripheral circuits.
With respect to Claim 20, Suh shows (Fig. 1a) wherein each of the memory dies include: a through-silicon via (360,460) penetrating the dies.
Furthermore, Lee teaches (Fig. 1-4, 14-16) wherein each of the memory dies includes: a through-silicon via penetrating the substrate (base layer), a first bump pad (85) connected to the uppermost metal pattern and a second bump pad (93) connected to the through silicon via. Also, see comments stated above in Par. 59-64 with regards to Claim 19, which are considered repeated here.
Response to Arguments
Applicant’s arguments with respect to claims 1-10, 12-21 have been considered but are moot because the new ground of rejection that contains Kim (US 2021/0375896) teaches the matters specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814