DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 1 June 2026 has been entered.
Response to Amendment
The Office acknowledges receipt on 1 June 2026 of Applicants’ amendment in which claims 1 and 18 are amended. The Office withdraws the indefiniteness rejections identified in the Office Communication dated 1 April 2026 in view of the amendments.
Response to Arguments
Applicants’ arguments with respect to claim(s) 1 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 10, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuniga et al. (US20240413234A1) in view of Radway et al. (US20170301772A1), Kotani et al. (US20180068923A1), Hu et al. (US20240322029A1), Chen et al. (US9960264B1), and Jacquet et al. (US20180308966A1).
Regarding claim 1, Zuniga teaches in Fig. 2 a compound semiconductor heterostructure transistor device having at least one two-dimensional electron gas channel and buried heat shielding, the compound semiconductor heterostructure transistor device comprising:
a substrate (not shown) {[0023]};
an electrode region (region of 141, 151, 161, 201) having at least one gate electrode (161/201), the electrode region (region of 141, 151, 161, 201) formed over the substrate (not shown) {[0026-0028, 0035]};
a first buried two-dimensional electron gas (2DEG) channel (134), wherein the first buried 2DEG channel (134) is more electrically conductive than either a first semiconductor material layer (132) or a second semiconductor material layer (131) formed over the first semiconductor material (132) to form a first compound semiconductor heterostructure (133) {[0024]; see Examiner’s Note, below}; and
a buried heat shield layer (layer of 121) formed between the electrode region (region of 141, 151, 161, 201) and the first buried 2DEG channel (134) {[0024]}.
Zuniga does not teach the buried heat shield layer is more thermally resistive than the substrate and other layers adjacent to the buried heat shield layer, and wherein the buried heat shield layer is configured to reduce a channel temperature at the electrode region by blocking heat generated in the first buried 2DEG channel from reaching the electrode region.
However, Zuniga teaches in Fig. 2 the buried heat shield layer (layer of 121) is AlGaN, the two most closely adjacent layers (layers of 112, 122) are GaN, and the substrate is Si {[0023, 0025]}. AlGaN typically has a thermal conductivity of about 9.7 to 11.2 at room temperature, and its thermal conductivity is inversely proportional to its aluminum content. See, e.g., Radway [0094] for teaching an exemplary thermal conductivity of 30 W/mK and Jacquet [0110] for teaching the inverse proportionality. GaN typically has a thermal conductivity of 200 W/mK, which may vary based on a defect density of the GaN. See, e.g., Kotani [0060] for teaching an exemplary thermal conductivity of 160 W/mK. Si typically has a thermal conductivity of 148 W/mK, which may vary based on the purity of the Si. See, e.g., Hu [0064, 0065] for teaching an exemplary thermal conductivity of 150 W/mK. In an analogous art, Chen teaches in ll. 28-32 of col. 1 that the performance and reliability of a HEMT transistor are inversely proportional to an amount of heat generated at a channel of the HEMT transistor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s transistor device based on the teachings of Radway, Kotani, Hu, Chen, and Jacquet for discovering an optimum or workable range of: (1) thermal conductivity for each of Zuniga’s AlGaN layer, two GaN layers, and Si substrate; (2) transistor reliability; and/or (3) transistor performance – such that Zuniga’s buried heat shield layer is more thermally resistive than the substrate and other layers adjacent to the buried heat shield layer, and the buried heat shield layer is configured to reduce a channel temperature at the electrode region by blocking heat generated in the first buried 2DEG channel from reaching the electrode region – because where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP §2144.05(II)(A).
Zuniga does not teach the second semiconductor material layer has a first aluminum content, and wherein the buried heat shield layer has a second aluminum content greater than the first aluminum content.
Chen teaches in ll. 28-32 of col. 1 that the performance and reliability of a HEMT transistor are inversely proportional to an amount of heat generated at a channel of the HEMT transistor. Jacquet teaches in paragraph [0110] that the percentage content of Al in AlGaN is inversely proportional to the thermal conductivity of the AlGaN. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s transistor device as modified by Radway, Kotani, Hu, Chen, and Jacquet based on the further teachings of Chen and Jacquet for discovering an optimum or workable range of: (1) thermal conductivity for each of Zuniga’s modified buried heat shield layer and second semiconductor material layer, (2) transistor reliability, and/or (3) transistor performance – such that the second semiconductor material layer has a first aluminum content, and wherein the buried heat shield layer has a second aluminum content greater than the first aluminum content – because where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP §2144.05(II)(A).
Examiner’s Note: the first buried two-dimensional electron gas (2DEG) channel (134) is implicitly more electrically conductive than either the first semiconductor material layer (132) or the second semiconductor material layer (131) formed over the first semiconductor material (132) to form the first compound semiconductor heterostructure (133) because the electrons within the 2DEG channel are confined to a quantum well that increases their mobilities and reduces their scattering (in a third dimension) relative to the semiconductor layers forming the heterojunction.
Regarding claim 2, Zuniga as modified by Radway, Kotani, Hu, Chen, and Jacquet teaches the compound semiconductor heterostructure transistor device of claim 1, and Zuniga further teaches comprising:
a third semiconductor material layer (111) formed over a fourth semiconductor material layer (112), wherein the fourth semiconductor material layer (112) is formed over the substrate (not shown), to form a second compound semiconductor heterostructure (113) having a topside second 2DEG channel (114), wherein the topside second 2DEG channel (114) is more electrically conductive than either the third semiconductor material layer (111) or the fourth semiconductor material layer (112) {[0024]; see Examiner’s Note, below}.
Examiner’s Note: the topside second 2DEG channel (114) is implicitly more electrically conductive than either third semiconductor material layer (111) or the fourth semiconductor material layer (112) of the second compound semiconductor heterostructure (113) because the electrons within the 2DEG channel are confined to a quantum well that increases their mobilities and reduces their scattering (in a third dimension) relative to the semiconductor layers forming the heterojunction.
Regarding claim 3, Zuniga as modified by Radway, Kotani, Hu, Chen, and Jacquet teaches the compound semiconductor heterostructure transistor device of claim 2, and Zuniga further teaches wherein the electrode region (region of 141, 151, 161, 201) includes:
a drain electrode (151) electrically coupled to the first semiconductor material layer (132) {[0027]};
a source electrode (141) electrically coupled to the topside second 2DEG channel (114) {[0026]}; and
a gate electrode (161/201) formed over the third semiconductor material layer (111) {[0028, 0035]}.
Regarding claim 4, Zuniga as modified by Radway, Kotani, Hu, Chen, and Jacquet teaches the compound semiconductor heterostructure transistor device of claim 2, and Zuniga further teaches wherein the heat shield layer (layer of 121) is formed between the fourth semiconductor material layer (112) and the second semiconductor material layer (131), and wherein the heat shield layer (layer of 121) includes a fifth semiconductor material layer (121) {Fig. 2; [0024]}.
Regarding claim 5, Zuniga as modified by Radway, Kotani, Hu, Chen, and Jacquet teaches the compound semiconductor heterostructure transistor device of claim 1, and Zuniga further teaches wherein the buried heat shield layer (layer of 121) includes aluminum gallium nitride {Fig. 2, [0025], AlGaN is aluminum gallium nitride}.
Regarding claim 10, Zuniga as modified by Radway, Kotani, Hu, Chen, and Jacquet teaches the compound semiconductor heterostructure transistor device of claim 1, and Zuniga further comprising:
a second buried two-dimensional electron gas (2DEG) channel (124), wherein the second buried 2DEG channel (124) is more electrically conductive than either a sixth semiconductor material layer (122) or a seventh semiconductor material layer (121) formed over the sixth semiconductor material (122) to form a second compound semiconductor heterostructure (123) {[0026]; see Examiner’s Note, below}.
Examiner’s Note: the second buried two-dimensional electron gas (2DEG) channel (124) is implicitly more electrically conductive than either the sixth semiconductor material layer (122) or the seventh semiconductor material layer (121) formed over the sixth semiconductor material layer (122) to form the second compound semiconductor heterostructure (123) because the electrons within the 2DEG channel are confined to a quantum well that increases their mobilities and reduces their scattering (in a third dimension) relative to the semiconductor layers forming the heterojunction.
Regarding claim 18, Zuniga teaches in Fig. 2 a semiconductor device having buried heat shielding, the semiconductor device comprising:
a substrate (not shown) {[0023]};
an electrode region (region of 141, 151, 161, 201) formed over the substrate (not shown) {[0026-0028, 0035]};
a buried current carrying layer (layer of 134) formed over the substrate (not shown) {[0024]}; and
a buried heat shield layer (layer of 121) formed between the electrode region (region of 141, 151, 161, 201) and the buried current carrying layer (layer of 134) {[0024]}.
Zuniga does not teach the buried heat shield layer is more thermally resistive than the substrate and other layers adjacent to the buried heat shield layer, and wherein the buried heat shield layer is configured to reduce a channel temperature at the electrode region by blocking heat generated in the buried current carrying layer from reaching the electrode region.
However, Zuniga teaches in Fig. 2 the buried heat shield layer (121) is AlGaN, the two most closely adjacent layers (112, 122) are GaN, and the substrate is Si {[0023, 0025]}. AlGaN typically has a thermal conductivity of about 9.7 to 11.2 at room temperature, and its thermal conductivity is inversely proportional to its aluminum content. See, e.g., Radway [0094] for teaching an exemplary thermal conductivity of 30 W/mK and Jacquet [0110] for teaching the inverse proportionality. GaN typically has a thermal conductivity of 200 W/mK, which may vary based on a defect density of the GaN. See, e.g., Kotani [0060] for teaching an exemplary thermal conductivity of 160 W/mK. Si typically has a thermal conductivity of 148 W/mK, which may vary based on the purity of the Si. See, e.g., Hu [0064, 0065] for teaching an exemplary thermal conductivity of 150 W/mK. Chen teaches in ll. 28-32 of col. 1 that the performance and reliability of a HEMT transistor are inversely proportional to an amount of heat generated at a channel of the HEMT transistor. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s transistor device based on the teachings of Radway, Kotani, Hu, Chen, and Jacquet for discovering an optimum or workable range of: (1) thermal conductivity for each of Zuniga’s AlGaN layer, two GaN layers, and Si substrate; (2) transistor reliability; and/or (3) transistor performance – such that Zuniga’s buried heat shield layer is more thermally resistive than the substrate and other layers adjacent to the buried heat shield layer, and the buried heat shield layer is configured to reduce a channel temperature at the electrode region by blocking heat generated in the buried current carrying layer from reaching the electrode region – because where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP §2144.05(II)(A).
Zuniga does not teach at least one layer adjacent to the buried heat shield layer has a first aluminum content, and wherein the buried heat shield layer has a second aluminum content greater than the first aluminum content.
Chen teaches in ll. 28-32 of col. 1 that the performance and reliability of a HEMT transistor are inversely proportional to an amount of heat generated at a channel of the HEMT transistor. Jacquet teaches in paragraph [0110] that the percentage content of Al in AlGaN is inversely proportional to the thermal conductivity of the AlGaN. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s semiconductor device as modified by Radway, Kotani, Hu, Chen, and Jacquet based on the further teachings of Chen and Jacquet for discovering an optimum or workable range of: (1) thermal conductivity for each of Zuniga’s modified buried heat shield layer and second semiconductor material layer, (2) transistor reliability, and/or (3) transistor performance – such that at least one layer adjacent to the buried heat shield layer has a first aluminum content, and wherein the buried heat shield layer has a second aluminum content greater than the first aluminum content – because where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. MPEP §2144.05(II)(A).
Regarding claim 19, Zuniga as modified by Radway, Kotani, Hu, Chen, and Jacquet teaches the semiconductor device of claim 18, and Zuniga further teaches wherein the buried heat shield layer (layer of 121) includes aluminum gallium nitride {Fig. 2, [0025], AlGaN is aluminum gallium nitride}.
Claim(s) 6 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuniga in view of Radway, Kotani, Hu, Chen, and Jacquet as applied to claim 5 (for claim 6) and claim 19 (for claim 20) above, and further in view of Saxler et al. (US20070269968A1).
Regarding claim 6, Zuniga as modified by Radway, Kotani, Hu, Chen, and Jacquet teaches the compound semiconductor heterostructure transistor device of claim 5, but Zuniga does not teach wherein an aluminum content of the aluminum gallium nitride is within a range of 25-80%.
In an analogous art, Saxler teaches an aluminum content of aluminum gallium nitride is within a range of 25%. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s transistor device as modified by Radway, Kotani, Hu, Chen, and Jacquet based on the teachings of Saxler – such that an aluminum content of the aluminum gallium nitride is within a range of 25-80% – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Moreover, all the claimed elements (e.g., aluminum content, aluminum gallium nitride) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Saxler) with no change in their respective functions (e.g., AlGaN barrier layer of a heterojunction), and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Regarding claim 20, Zuniga as modified by Radway, Kotani, Hu, Chen, and Jacquet teaches the semiconductor device of claim 19, but Zuniga does not teach wherein an aluminum content of the aluminum gallium nitride is within a range of 25-80%.
Saxler teaches an aluminum content of aluminum gallium nitride is within a range of 25%. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s semiconductor device as modified by Radway, Kotani, Hu, Chen, and Jacquet based on the teachings of Saxler – such that an aluminum content of the aluminum gallium nitride is within a range of 25-80% – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Moreover, all the claimed elements (e.g., aluminum content, aluminum gallium nitride) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Saxler) with no change in their respective functions (e.g., AlGaN barrier layer of a heterojunction), and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuniga in view of Radway, Kotani, Hu, Chen, and Jacquet as applied to claim 1 above, and further in view of Klowak et al. (US20160240471A1).
Regarding claim 7, Zuniga as modified by Radway, Kotani, Hu, Chen, and Jacquet teaches the compound semiconductor heterostructure transistor device of claim 1, and Zuniga further teaches wherein
the electrode region (region of 141, 151, 161, 201) includes a source electrode (141) {[0026]}.
Zuniga does not teach the compound semiconductor heterostructure transistor device comprising: at least one heat pad coupled to the source electrode.
In an analogous art, Klowak teaches in Fig. 2D and paragraph [0060] a heat pad (142) coupled to a source electrode (132). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s transistor device as modified by Radway, Kotani, Hu, Chen, and Jacquet based on the teachings of Klowak – such that at least one heat pad is coupled to the source electrode – to provide heat dissipation. Klowak [0086].
Regarding claim 8, Zuniga as modified by Radway, Kotani, Hu, Chen, Jacquet, and Klowak teaches the compound semiconductor heterostructure transistor device of claim 7, but Zuniga does not teach wherein the at least one heat pad includes copper.
Klowak teaches in Fig. 2D and paragraph [0060] a heat pad (142) includes copper. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s transistor device as modified by as modified by Radway, Kotani, Hu, Chen, Jacquet, and Klowak based on the further teachings of Klowak – such that at least one heat pad is coupled to the source electrode – to provide heat dissipation. Klowak [0086]. Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuniga in view of Radway, Kotani, Hu, Chen, Jacquet, and Klowak as applied to claim 8 above, and further in view of Inumiya et al. (US20190295957A1).
Regarding claim 9, Zuniga as modified by Radway, Kotani, Hu, Chen, Jacquet, and Klowak teaches the compound semiconductor heterostructure transistor device of claim 8, but Zuniga does not teach wherein the copper has a thickness in range of 20-50 micrometers.
In an analogous art, Inumiya teaches in Figs. 1 and 2 and paragraphs [0024] and [0030] a copper heat pad has a thickness between 5 μm and 50 μm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s transistor device as modified by Radway, Kotani, Hu, Chen, Jacquet, and Klowak based on the teachings of Inumiya – such that the copper has a thickness in range of 20-50 micrometers – [t]o suppress a rise in the temperature caused by heat generation {Inumiya [0004]} that could lead to a degradation in reliability {Inumiya [0003]}. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin et al. (US10217854B1) teaches a semiconductor device includes a first III-V compound layer disposed over a substrate and a second III-V compound layer disposed over the first III-V compound layer, wherein a first carrier channel is formed in the interface between the first III-V compound layer and the second III-V compound layer. The semiconductor device also includes a third III-V compound layer disposed over the second III-V compound layer and a fourth III-V compound layer disposed over the third III-V compound layer, wherein a second carrier channel is formed in an interface between the third III-V compound layer and the fourth III-V compound layer. The semiconductor device includes a gate structure and S/D regions disposed on two opposite sides of the gate structure, wherein the first carrier channel and the second carrier channel are extended between the S/D regions.
Conclusion
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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