DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Office acknowledges receipt on 10 February 2026 of Applicants’ amendment in which claims 1, 3, 11, 13, and 18 are amended.
Response to Arguments
Applicants’ arguments with respect to claim(s) 1 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1, lines 11 and 14-15, recites two instances of “the buried 2DEG channel,” each of which is indefinite because it lacks a proper antecedent basis. For the purpose of compact prosecution, each instance will be interpreted as “the first buried 2DEG channel.” Claims 2-10 are rejected due to their dependence from base claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 10, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuniga et al. (US20240413234A1) in view of Radway et al. (US20170301772A1), Kotani et al. (US20180068923A1), and Hu et al. (US20240322029A1).
Regarding claim 1, as interpreted in view of the indefiniteness rejection, Zuniga teaches in Fig. 2 a compound semiconductor heterostructure transistor device having at least one two-dimensional electron gas channel and buried heat shielding, the compound semiconductor heterostructure transistor device comprising:
a substrate (not shown) {[0023]};
an electrode region (region of 141, 151, 161, 201) having at least one gate electrode (161/201), the electrode region (region of 141, 151, 161, 201) formed over the substrate (not shown) {[0026-0028, 0035]};
a first buried two-dimensional electron gas (2DEG) channel (134), wherein the first buried 2DEG channel (134) is more electrically conductive than either a first semiconductor material layer (132) or a second semiconductor material layer (131) formed over the first semiconductor material (132) to form a first compound semiconductor heterostructure (133) {[0024]; see Examiner’s Note, below}; and
a buried heat shield layer (layer of 121) formed between the electrode region (region of 141, 151, 161, 201) and the first buried 2DEG channel (134) {[0024]}.
Zuniga does not teach the buried heat shield layer is more thermally resistive than the substrate and other layers adjacent to the buried heat shield layer, and wherein the buried heat shield layer is configured to reduce a channel temperature at the electrode region by blocking heat generated in the first buried 2DEG channel from reaching the electrode region.
However, Zuniga teaches in Fig. 2 the buried heat shield layer (layer of 121) is AlGaN, the two most closely adjacent layers (layers of 112, 122) are GaN, and the substrate is Si {[0023, 0025]}.
In analogous art: (1) Radway teaches in paragraph [0094] an AlGaN layer having a thermal conductivity of 30 W/mK, Kotani teaches in paragraph [0060] a GaN layer having a thermal conductivity of 160 W/mK, and Hu teaches in paragraphs [0064, 0065] a substrate of Si having a thermal conductivity of 150W/mK. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s transistor device based on the teachings of Radway, Kotani, and Hu – such that Radway’s AlGaN layer is substituted for Zuniga’s, Kotani’s GaN layer is substituted for Zuniga’s, and Hu’s Si substrate is substituted for Zuniga’s – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Moreover, one of ordinary skill in the art could have substituted each known element (e.g., AlGaN, GaN, Si) for Zuniga’s corresponding element (e.g., AlGaN, GaN, Si), and the results of the substitution would have been predictable. MPEP §2143(I)(B). And because thermal conductivity is the inverse of thermal resistivity, it follows that consequences of the above-identified modifications are that Zuniga’s modified buried heat shield layer is more thermally resistive than Zuniga’s modified substrate and Zuniga’s modified other layers adjacent to the modified buried heat shield layer. And because Zuniga’s modified buried heat shield layer has a higher thermal resistivity than its modified adjacent layers and the modified substrate, it further follows that Zuniga’s modified buried heat shield layer is configured to reduce a channel temperature at the electrode region by blocking heat generated in the first buried 2DEG channel from reaching the electrode region because Zuniga’s modified buried heat shield layer is disposed between the first buried 2DEG channel (e.g., 134) and the electrode region (e.g., region of 141, 151, 161, 201).
Examiner’s Note: the first buried two-dimensional electron gas (2DEG) channel (134) is implicitly more electrically conductive than either the first semiconductor material layer (132) or the second semiconductor material layer (131) formed over the first semiconductor material (132) to form the first compound semiconductor heterostructure (133) because the electrons within the 2DEG channel are confined to a quantum well that increases their mobilities and reduces their scattering (in a third dimension) relative to the semiconductor layers forming the heterojunction.
Regarding claim 2, Zuniga as modified by Radway, Kotani, and Hu teaches the compound semiconductor heterostructure transistor device of claim 1, and Zuniga further teaches comprising:
a third semiconductor material layer (111) formed over a fourth semiconductor material layer (112), wherein the fourth semiconductor material layer (112) is formed over the substrate (not shown), to form a second compound semiconductor heterostructure (113) having a topside second 2DEG channel (114), wherein the topside second 2DEG channel (114) is more electrically conductive than either the third semiconductor material layer (111) or the fourth semiconductor material layer (112) {[0024]; see Examiner’s Note, below}.
Examiner’s Note: the topside second 2DEG channel (114) is implicitly more electrically conductive than either third semiconductor material layer (111) or the fourth semiconductor material layer (112) of the second compound semiconductor heterostructure (113) because the electrons within the 2DEG channel are confined to a quantum well that increases their mobilities and reduces their scattering (in a third dimension) relative to the semiconductor layers forming the heterojunction.
Regarding claim 3, Zuniga as modified by Radway, Kotani, and Hu teaches the compound semiconductor heterostructure transistor device of claim 2, and Zuniga further teaches wherein the electrode region (region of 141, 151, 161, 201) includes:
a drain electrode (151) electrically coupled to the first semiconductor material layer (132) {[0027]};
a source electrode (141) electrically coupled to the topside second 2DEG channel (114) {[0026]}; and
a gate electrode (161/201) formed over the third semiconductor material layer (111) {[0028, 0035]}.
Regarding claim 4, Zuniga as modified by Radway, Kotani, and Hu teaches the compound semiconductor heterostructure transistor device of claim 2, and Zuniga further teaches wherein the heat shield layer (layer of 121) is formed between the fourth semiconductor material layer (112) and the second semiconductor material layer (131), and wherein the heat shield layer (layer of 121) includes a fifth semiconductor material layer (121) {Fig. 2; [0024]}.
Regarding claim 5, Zuniga as modified by Radway, Kotani, and Hu teaches the compound semiconductor heterostructure transistor device of claim 1, and Zuniga further teaches wherein the buried heat shield layer (layer of 121) includes aluminum gallium nitride {Fig. 2, [0025], AlGaN is aluminum gallium nitride}.
Regarding claim 10, Zuniga as modified by Radway, Kotani, and Hu teaches the compound semiconductor heterostructure transistor device of claim 1, and Zuniga further comprising:
a second buried two-dimensional electron gas (2DEG) channel (124), wherein the second buried 2DEG channel (124) is more electrically conductive than either a sixth semiconductor material layer (122) or a seventh semiconductor material layer (121) formed over the sixth semiconductor material (122) to form a second compound semiconductor heterostructure (123) {[0026]; see Examiner’s Note, below}.
Examiner’s Note: the second buried two-dimensional electron gas (2DEG) channel (124) is implicitly more electrically conductive than either the sixth semiconductor material layer (122) or the seventh semiconductor material layer (121) formed over the sixth semiconductor material layer (122) to form the second compound semiconductor heterostructure (123) because the electrons within the 2DEG channel are confined to a quantum well that increases their mobilities and reduces their scattering (in a third dimension) relative to the semiconductor layers forming the heterojunction.
Regarding claim 18, Zuniga teaches in Fig. 2 a semiconductor device having buried heat shielding, the semiconductor device comprising:
a substrate (not shown) {[0023]};
an electrode region (region of 141, 151, 161, 201) formed over the substrate (not shown) {[0026-0028, 0035]};
a buried current carrying layer (layer of 134) formed over the substrate (not shown) {[0024]}; and
a buried heat shield layer (layer of 121) formed between the electrode region (region of 141, 151, 161, 201) and the buried current carrying layer (layer of 134) {[0024]}.
Zuniga does not teach the buried heat shield layer is more thermally resistive than the substrate and other layers adjacent to the buried heat shield layer, and wherein the buried heat shield layer is configured to reduce a channel temperature at the electrode region by blocking heat generated in the buried current carrying layer from reaching the electrode region.
However, Zuniga teaches in Fig. 2 the buried heat shield layer (121) is AlGaN, the two most closely adjacent layers (112, 122) are GaN, and the substrate is Si {[0023, 0025]}.
In analogous art: (1) Radway teaches in paragraph [0094] an AlGaN layer having a thermal conductivity of 30 W/mK, Kotani teaches in paragraph [0060] a GaN layer having a thermal conductivity of 160 W/mK, and Hu teaches in paragraphs [0064, 0065] a substrate of Si having a thermal conductivity of 150W/mK. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s semiconductor device based on the teachings of Radway, Kotani, and Hu – such that Radway’s AlGaN layer is substituted for Zuniga’s, Kotani’s GaN layer is substituted for Zuniga’s, and Hu’s Si substrate is substituted for Zuniga’s – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Moreover, one of ordinary skill in the art could have substituted each known element (e.g., AlGaN, GaN, Si) for Zuniga’s corresponding element (e.g., AlGaN, GaN, Si), and the results of the substitutions would have been predictable. MPEP §2143(I)(B). And because thermal conductivity is the inverse of thermal resistivity, it follows that consequences of the above-identified modifications are that Zuniga’s modified buried heat shield layer is more thermally resistive than Zuniga’s modified substrate and Zuniga’s modified other layers adjacent to the modified buried heat shield layer. And because Zuniga’s modified buried heat shield layer has a higher thermal resistivity than its modified adjacent layers and the modified substrate, it further follows that Zuniga’s modified buried heat shield layer is configured to reduce a channel temperature at the electrode region by blocking heat generated in the first buried 2DEG channel from reaching the electrode region because Zuniga’s modified buried heat shield layer is disposed between the first buried 2DEG channel (e.g., 134) and the electrode region (e.g., region of 141, 151, 161, 201).
Regarding claim 19, Zuniga as modified by Radway, Kotani, and Hu teaches the semiconductor device of claim 18, and Zuniga further teaches wherein the buried heat shield layer (layer of 121) includes aluminum gallium nitride {Fig. 2, [0025], AlGaN is aluminum gallium nitride}.
Claim(s) 6 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuniga in view of Radway, Kotani, and Hu as applied to claim 5 (for claim 6) and claim 19 (for claim 20) above, and further in view of Saxler et al. (US20070269968A1).
Regarding claim 6, Zuniga as modified by Radway, Kotani, and Hu teaches the compound semiconductor heterostructure transistor device of claim 5, but Zuniga does not teach wherein an aluminum content of the aluminum gallium nitride is within a range of 25-80%.
In an analogous art, Saxler teaches an aluminum content of aluminum gallium nitride is within a range of 25%. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s transistor device as modified by Radway, Kotani, and Hu based on the teachings of Saxler – such that an aluminum content of the aluminum gallium nitride is within a range of 25-80% – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Moreover, all the claimed elements (e.g., aluminum content, aluminum gallium nitride) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Saxler) with no change in their respective functions (e.g., AlGaN barrier layer of a heterojunction), and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Regarding claim 20, Zuniga as modified by Radway, Kotani, and Hu teaches the semiconductor device of claim 19, but Zuniga does not teach wherein an aluminum content of the aluminum gallium nitride is within a range of 25-80%.
Saxler teaches an aluminum content of aluminum gallium nitride is within a range of 25%. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s semiconductor device as modified by Radway, Kotani, and Hu based on the teachings of Saxler – such that an aluminum content of the aluminum gallium nitride is within a range of 25-80% – because [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07. Moreover, all the claimed elements (e.g., aluminum content, aluminum gallium nitride) were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods (e.g., as taught by Saxler) with no change in their respective functions (e.g., AlGaN barrier layer of a heterojunction), and the combination yielding nothing more than predictable results to one of ordinary skill in the art. MPEP §2143(I)(A).
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuniga in view of Radway, Kotani, and Hu as applied to claim 1 above, and further in view of Klowak et al. (US20160240471A1).
Regarding claim 7, Zuniga as modified by Radway, Kotani, and Hu teaches the compound semiconductor heterostructure transistor device of claim 1, and Zuniga further teaches wherein
the electrode region (region of 141, 151, 161, 201) includes a source electrode (141) {[0026]}.
Zuniga does not teach the compound semiconductor heterostructure transistor device comprising: at least one heat pad coupled to the source electrode.
In an analogous art, Klowak teaches in Fig. 2D and paragraph [0060] a heat pad (142) coupled to a source electrode (132). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s transistor device as modified by Radway, Kotani, and Hu based on the teachings of Klowak – such that at least one heat pad is coupled to the source electrode – to provide heat dissipation. Klowak [0086].
Regarding claim 8, Zuniga as modified by Radway, Kotani, Hu, and Klowak teaches the compound semiconductor heterostructure transistor device of claim 7, but Zuniga does not teach wherein the at least one heat pad includes copper.
Klowak teaches in Fig. 2D and paragraph [0060] a heat pad (142) includes copper. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s transistor device as modified by as modified by Radway, Kotani, Hu, and Klowak based on the further teachings of Klowak – such that at least one heat pad is coupled to the source electrode – to provide heat dissipation. Klowak [0086]. Moreover, [t]he selection of a known material based on its suitability for its intended use [is] … prima facie obviousness. MPEP §2144.07.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zuniga in view of Radway, Kotani, Hu, and Klowak as applied to claim 8 above, and further in view of Inumiya et al. (US20190295957A1).
Regarding claim 9, Zuniga as modified by Radway, Kotani, Hu, and Klowak teaches the compound semiconductor heterostructure transistor device of claim 8, but Zuniga does not teach wherein the copper has a thickness in range of 20-50 micrometers.
In an analogous art, Inumiya teaches in Figs. 1 and 2 and paragraphs [0024] and [0030] a copper heat pad has a thickness between 5 μm and 50 μm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Zuniga’s transistor device as modified by Radway, Kotani, Hu, and Klowak based on the teachings of Inumiya – such that the copper has a thickness in range of 20-50 micrometers – [t]o suppress a rise in the temperature caused by heat generation {Inumiya [0004]} that could lead to a degradation in reliability {Inumiya [0003]}. In the case where the claimed ranges “overlap or lie inside ranges disclosed by the prior art” a prima facie case of obviousness exists. MPEP §2144.05(I).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.W.W./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
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