DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1 December 2025.
Information Disclosure Statement
This office acknowledges receipt of the following items from the applicant: Information Disclosure Statements (IDS) filed on 12 May 2024 and 26 December 2025. The references cited on the PTOL 1449 forms have been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Huang et al. (U.S. Patent Application Publication 2022/0310455).
Referring to Claim 1, Huang teaches a semiconductor structure comprising: a plurality of gate-all-around field effect transistors, each of the gate-all-around field effect transistors including: a first source-drain region and a second source-drain region (232S and 232D); at least one channel region (208) interconnecting the first and second source-drain regions (232S and 232D); and a gate structure (242/244) surrounding the at least one channel region (208); a direct backside contact (266) located below one of the first source-drain region and the second source-drain.
Claims 1 and 10 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Yu et al. (U.S. Patent Application Publication 2021/0408247).
Referring to Claim 1, Yu teaches in Fig. 29A-29C for example, a semiconductor structure comprising: a plurality of gate-all-around field effect transistors, each of the gate-all-around field effect transistors including: a first source-drain region and a second source-drain region (92 and 92’; par. 48-53 and 68); at least one channel region (54 of 55; par. 12, 19, 21 and 22) interconnecting the first and second source-drain regions (92); and a gate structure (100/102; par. 13 and 58-61) surrounding the at least one channel region (54); a direct backside contact (170; par. 46; Fig. 27B-29C) located below one of the first source-drain region (92) and the second source-drain region (92), the direct backside contact (170) having an upper portion; and a dielectric liner (166) wrapped around the upper portion of the direct backside contact (170). It is noted that the device gets flipped during manufacturing between Fig. 21C and Fig. 22A. The interpretation with respect to the relative terms, i.e. upper or below, is with respect to Fig. 29A-29C rotated 180 degrees shown below (the original orientation up through Fig. 21C).
PNG
media_image1.png
749
576
media_image1.png
Greyscale
PNG
media_image2.png
756
579
media_image2.png
Greyscale
Fig. 29A Fig. 29B
PNG
media_image3.png
665
739
media_image3.png
Greyscale
Fig. 29C
Referring to Claim 10, Yu teaches in Fig. 29A-29C and Fig. a semiconductor structure comprising: a plurality of gate-all-around field effect transistors, each of the gate-all-around field effect transistors including: a first source-drain region and a second source-drain region (92 and 92’; par. 48-53 and 68); at least one channel region (54 of 55; par. 12, 19, 21 and 22) interconnecting the first source-drain region and the second source-drain region (92 and 92’); and a gate structure (100/102; par. 13 and 58-61) surrounding the at least one channel region (54); a direct backside contact (170; par. 46; Fig. 27B-29C) located below one (92’) of the first source-drain region and the second source-drain region, the direct backside contact (170) having an upper portion; a placeholder structure (162; par. 83) located below another one (92) of the first source-drain region and the second source-drain region, the placeholder structure (162) having an upper portion; and a dielectric liner (160) wrapped around the upper portion of the placeholder (162). It is noted that the device gets flipped during manufacturing between Fig. 21C and Fig. 22A. The interpretation with respect to the relative terms, i.e. upper or below, is with respect to Fig. 29A-29C rotated 180 degrees shown above (the original orientation up through Fig. 21C). "The identical invention must be shown in as complete detail as is contained in the ... claim." Richardson v. Suzuki Motor Co., 868 F.2d 1226, 1236, 9 USPQ2d 1913, 1920 (Fed. Cir. 1989). The elements must be arranged as required by the claim, but this is not an ipsissimis verbis test, i.e., identity of terminology is not required. In re Bond, 910 F.2d 831, 15 USPQ2d 1566 (Fed. Cir. 1990). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Allowable Subject Matter
Claims 2-9 and 11-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 2, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor structure further comprising: bottom dielectric isolation (BDI) below gate structures; and backside interlayer dielectric (BILD) (89) below the plurality of gate-all-around field effect transistors, wherein a portion of the BILD comprises protector BILD between a corresponding one of the gate structures and the direct backside contact, wherein the dielectric liner is between the upper portion of the direct backside contact and the BDI in combination with all of the limitations of Claim 1 and 2. Claims 3-9 include the limitations of claim 2.
Regarding Claim 11, the prior art of record alone or in combination neither teaches nor makes obvious the invention of the semiconductor structure further comprising backside interlayer dielectric (BILD) below the plurality of gate-all-around field effect transistors, wherein a portion of the (BILD) comprises protector BILD between a corresponding one of the gate structures and the direct backside contact in combination with all of the limitations of Claim 10 and 11. Claims 12-17 include the limitations of claim 11.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EARL N TAYLOR whose telephone number is (571)272-8894. The examiner can normally be reached M-F, 9:00am-5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached on (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EARL N TAYLOR/Primary Examiner, Art Unit 2896
EARL N. TAYLOR
Primary Examiner
Art Unit 2896