DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statements filed on 06/15/2023 and 02/06/2026 have been considered.
Drawings
The drawings filed on 06/15/2023 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 06/15/2023 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-7, 9-14, 16, 19, 20 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Choe .
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Regarding claim 1, Choe discloses:
A semiconductor device comprising:
a first semiconductor chip (210, ¶0052) having a first through silicon via (TSV)(214, ¶0065);
a second semiconductor chip (220, ¶0052) arranged on the first semiconductor chip (210) and including a second TSV (224, ¶0065) positioned on a same vertical line as the first TSV (figure 5, ¶0082);
a conductive pad (216, 227, ¶0065, ¶0064) disposed on each of the first TSV (214) and the second TSV (224), the conductive pad (216, 227) electrically connecting the first semiconductor chip (200) and the second semiconductor chip (210) to each other; and
a warpage prevention metal structure (228, ¶0089 discloses the dummy pads 228 prevent warpage during a bonding process) disposed on an upper surface of the second semiconductor chip 220.
Regarding claim 4, Choe further discloses:
a protective layer (passivation 212, 222, ¶0065) on upper surfaces of each of the first semiconductor chip (210) and the second semiconductor chip (220), wherein the warpage prevention metal structure (228) is disposed directly on the protective layer (222).
Regarding claim 5, Choe further discloses:
wherein the warpage prevention metal structure (228, 218) is electrically insulated from the first semiconductor chip (210) and the second semiconductor chip (220).
Regarding claim 6, Choe further discloses:
wherein the warpage prevention metal structure (218, 228) has a substantially same height as the conductive pad (216, 226, ¶0006).
Regarding claim 7, Choe further discloses:
wherein the warpage prevention metal structure is composed of a same material as the conductive pad (¶0012).
Regarding claim 9, Choe further discloses:
an upper semiconductor chip (300, ¶0052) arranged on the second semiconductor chip (220), the upper semiconductor chip (300) having a thickness greater than thicknesses of each of the first semiconductor chip (210) and the second semiconductor chip (220, figure 1).
Regarding claim 10, Choe further discloses:
an under fill material (219, 229, 239, ¶0064, ¶0068) filling a space among the first semiconductor chip (210), the second semiconductor (220), and the upper semiconductor chip (300), the under fill material surrounding a periphery thereof (figure 1).
Regarding claim 11, Choe further discloses:
a conductive bump (241, ¶0055) arranged between the conductive pad (216) disposed on an upper end of the first TSV (214) and the conductive pad (227) disposed on a lower end of the second TSV (224), the conductive bump is electrically connected to the conductive pad on each of the first TSV and the second TSV (figure 1).
Regarding claim 12, Choe discloses:
A semiconductor device comprising:
a plurality of inner substrates (200, 210, 220, ¶0052) including semiconductor devices;
a through silicon via (TSV) (204, 214, 224, ¶0062) arranged to vertically penetrate each of the plurality of inner substrates (200, 210, 220);
a protective layer (202, 212, 222, ¶0058, ¶0065) disposed on an upper surface of each of the plurality of inner substrates (200, 210, 220), the protective layer surrounding a side surface of the TSV (figure 1);
a conductive pad (206) arranged on the TSV (204); and
a warpage prevention metal structure (208, 218, 228, ¶0063, ¶0065, ¶0089) disposed on the protective layer (202, 2018, 228) of some of the plurality of inner substrates, the warpage prevention metal structure is electrically insulated (by passivation layer 202, 212, 222, figure 1) from the semiconductor devices of the plurality of inner substrates.
Regarding claim 13, Choe further discloses:
an upper substrate (300) arranged on an upper portion of the plurality of inner substrates, the upper substrate (300) is electrically connected to an uppermost inner substrate (230) among the plurality of inner substrates through the conductive pad (236), the upper substrate has a thickness greater than thicknesses of each of the plurality of inner substrates (figure 1).
Regarding claim 14, Choe further discloses:
wherein the warpage prevention metal structure is disposed at a substantially same height and is composed of a same material as the conductive pad (¶0006, ¶0012).
Regarding claim 16, Choe further discloses:
wherein the warpage prevention metal structure (218) is arranged on an upper inner substrate or a lower inner substrate with respect to a virtual horizontal line that divides the plurality of inner substrates in a vertical direction.
Regarding claim 19, Choe further discloses:
an under fill material (209, 219, 229) surrounding the conductive pad and the warpage prevention metal structure, the under fill material filling a space among the plurality of inner substrates (figure 1).
Regarding claim 20, Choe discloses:
A semiconductor device comprising:
a plurality of inner substrates (200, 210, 220, 230) including semiconductor devices;
a through silicon via (TSV) (204, 214, 224, 234) arranged to vertically penetrate each of the plurality of inner substrates;
a protective layer (202, 212, 222, 232) disposed on an upper surface of each of the plurality of inner substrates, the protective layer surrounding a side surface of the TSV (figure 1);
a conductive pad disposed on the TSV (206, 217, 218, 224, 226, 236, ¶0064, ¶0065);
a warpage prevention metal structure (208) disposed on the protective layer (202) of an lower inner substrate (200) based on a virtual horizontal line dividing the plurality of inner substrates in a vertical direction, the warpage prevention metal structure (208) is electrically insulated from the semiconductor devices of the plurality of inner substrate; and
an upper substrate (300, ¶0052) arranged on an upper portion of each of the plurality of inner substrates, the upper substrate is electrically connected to an uppermost inner substrate (230) among the plurality of inner substrates through the conductive pad (236), the upper substrate (300) has a thickness greater than thicknesses of each of the plurality of inner substrates (200, 210, 220, 230, figure 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3, 8, 15, 17 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choe.
Regarding claim 2, Choe does not disclose “wherein the warpage prevention metal structure surrounds a peripheral circumference of the first TSV or the second TSV. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met.
Regarding claim 3, Choe does not disclose “wherein the warpage prevention metal structure is arranged in a frame shape”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met.
Regarding claim 8, Choe does not disclose “wherein the warpage prevention metal structure has a different size from that of the conductive pad”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met.
Regarding claim 15, Choe further discloses:
a plurality of warpage prevention metal structures (208, 218, 228) is disposed on the protective layer (202, 212, 222) of some of the plurality of inner substrates.
Choe does not disclose “an area of each of the plurality of warpage prevention metal structures decreases as a distance to a circumference of some of the plurality of inner substrates decreases”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met.
Regarding claim 17, Choe does not disclose ”the warpage prevention metal structure includes a plurality of warpage prevention metal structures; and each of the plurality of warpage prevention metal structures has a long rod shape in a first direction, the plurality of warpage prevention metal structures is arranged parallel to each other in a second direction perpendicular to the first direction”.
However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met.
Regarding claim 18, Choe discloses:
the warpage prevention metal structure (208, 218, 228) includes a plurality of warpage prevention metal structures.
Choe does not disclose “each of the plurality of warpage prevention metal structures extends in a first direction or a second direction perpendicular to the first direction, wherein the plurality of warpage prevention metal structures has a grid shape and is arranged along a shape of the plurality of inner substrates around a TSV circumference”. However, a change in size or shape or both is an unpatentable modification when it results in optimum conditions that differ from the prior art in degree but not in kind. In Re Rose, 220 F.2d 459, 105 USPQ 237, In reDailey, 357 F.2d 669, 149 USPQ 47). In the instant case the prior art device would not perform differently if modified to the claimed shape or size. Therefore the claimed limitations are considered met.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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/WILLIAM A HARRISTON/ Primary Examiner, Art Unit 2899
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